KR20000003922A - Method for forming a contact hole of semiconductor devices - Google Patents
Method for forming a contact hole of semiconductor devices Download PDFInfo
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- KR20000003922A KR20000003922A KR1019980025229A KR19980025229A KR20000003922A KR 20000003922 A KR20000003922 A KR 20000003922A KR 1019980025229 A KR1019980025229 A KR 1019980025229A KR 19980025229 A KR19980025229 A KR 19980025229A KR 20000003922 A KR20000003922 A KR 20000003922A
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- contact hole
- insulating film
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- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims description 7
- 238000009616 inductively coupled plasma Methods 0.000 claims description 7
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 6
- 239000005388 borosilicate glass Substances 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 229910052731 fluorine Inorganic materials 0.000 claims description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 239000005360 phosphosilicate glass Substances 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 238000009835 boiling Methods 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- -1 CF 4 Chemical compound 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 장치 제조 방법에 관한 것으로, 콘택홀 입구가 의도한 크기 이상으로 확대되는 것을 방지할 수 있는, 반도체 장치의 콘택홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device, which can prevent the contact hole inlet from expanding beyond its intended size.
반도체 소자의 집적도가 증가함에 따라 소자의 최소 설계 한계가 급격히 감소하여 노광장비의 한계보다 작은 미세 패턴의 형성이 요구된다. 콘택홀 형성의 경우 비록 0.10 ㎛ 이하의 미세 콘택홀을 형성하는 것이 가능할지라도 크기가 너무 작아짐으로 인하여 콘택 저항이 증가하여 소자의 전기적 특성 저하를 유발한다.As the degree of integration of semiconductor devices increases, the minimum design limit of the device is drastically reduced, so that the formation of fine patterns smaller than the limits of the exposure equipment is required. In the case of contact hole formation, although it is possible to form a fine contact hole of 0.10 μm or less, the contact resistance increases due to the size being too small, leading to a decrease in electrical characteristics of the device.
따라서, 콘택홀 소정 크기 이상 확보하기 위하여 여러 가지 형태의 자기정렬 콘택(self align contact, SAC) 방법이 제시되고 있다. 특히, 질화막을 장벽막으로 이용한 자기정렬 콘택홀 형성 방법은 통상적인 콘택홀 형성 기술에 비해 비교적 적은 공정 단계의 추가로 용이하게 고집적 소자의 콘택홀을 형성할 수 있다. 그러나, 질화막을 장벽막으로 이용한 자기정렬 콘택홀 형성 방법에서, 층간절연막을 건식식각 방법으로 제거하여 콘택홀을 형성하는데, 이때 질화막에 대한 높은 선택비를 얻기 위해 많은 양의 중합체(polymer)를 이용함에 따라 중합체로 인한 식각 멈춤(etch stop)을 동시에 조절해야하는 어려움이 있다. 상기와 같은 문제점을 해결하기 위하여, 산화막을 장벽막으로 이용하는 자기정렬 콘택홀 형성 방법이 제시되었다.Accordingly, various types of self align contact (SAC) methods have been proposed to secure a contact hole of a predetermined size or more. In particular, the self-aligned contact hole forming method using the nitride film as a barrier film can form contact holes of a highly integrated device easily with the addition of a relatively small process step, compared to conventional contact hole forming techniques. However, in the method of forming a self-aligned contact hole using a nitride film as a barrier film, the interlayer insulating film is removed by dry etching to form a contact hole, in which a large amount of polymer is used to obtain a high selectivity for the nitride film. As a result, there is a difficulty in controlling the etch stop due to the polymer at the same time. In order to solve the above problems, a method of forming a self-aligned contact hole using an oxide film as a barrier film has been proposed.
산화막을 장벽막으로 이용하는 종래의 자기정렬 콘택홀 형성 공정을 도1을 참조하여 설명한다.A conventional self-aligning contact hole forming process using an oxide film as a barrier film will be described with reference to FIG.
먼저, 반도체 기판(10) 상에 전도막 패턴(11)을 형성하고, 전도막 패턴(11)을 감싸는 제1 산화막(12)을 형성한 다음, 층간절연 및 평탄화를 위하여 반도체 기판(10) 전면에 제1 산화막(12)과 식각 특성이 다른 제2 산화막(13)을 형성한다.First, the conductive film pattern 11 is formed on the semiconductor substrate 10, and the first oxide film 12 surrounding the conductive film pattern 11 is formed. Then, the entire surface of the semiconductor substrate 10 is formed for interlayer insulation and planarization. A second oxide film 13 having an etching characteristic different from that of the first oxide film 12 is formed.
다음으로, 건식 경사식각 공정으로 제2 산화막(13)을 선택적으로 제거하여 반도체 기판(10) 표면을 노출하는 0.1 ㎛ 이하의 미세 콘택홀을 형성한다. 도2에서 점선은 건식 경사식각 공정 후의 프로파일(profile)을 나타낸다.Next, the second oxide layer 13 is selectively removed by a dry gradient etching process to form a fine contact hole of 0.1 μm or less that exposes the surface of the semiconductor substrate 10. The dashed line in FIG. 2 shows the profile after the dry gradient etching process.
이어서, 제2 산화막(13)에 대한 높은 식각 선택비를 갖는 식각제를 이용하는 등방성 식각 공정으로 제2 산화막(13)을 식각하여 콘택홀의 크기를 넓힌다.Subsequently, the second oxide film 13 is etched by an isotropic etching process using an etchant having a high etching selectivity with respect to the second oxide film 13 to increase the size of the contact hole.
상기와 같은 종래의 콘택홀 형성 방법은, 콘택홀의 크기를 넓히기 위해 등방성 식각 공정을 실시함으로 인하여 원하는 폭(A)보다 넓은 폭(B)의 콘택홀 입구를 얻게되어 이후에 형성되는 전도막 패턴과의 정렬 문제가 대두되고 있다.The conventional method for forming a contact hole as described above is performed by an isotropic etching process to increase the size of the contact hole, thereby obtaining a contact hole inlet having a width (B) wider than the desired width (A) and then forming a conductive film pattern. 'S alignment problem is on the rise.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 콘택홀 형성을 위한 건식 경사식각 공정 후에 콘택홀의 크기를 넓히기 위해 부가적으로 실시되는 등방성 식각으로 인하여 콘택홀 입구의 폭이 원하지 않는 크기까지 확대되는 것을 방지할 수 있는 반도체 장치의 콘택홀 형성 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is that the width of the contact hole inlet is expanded to an undesired size due to the isotropic etching additionally performed to increase the size of the contact hole after the dry slope etching process for forming the contact hole. It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device which can be prevented.
도1은 종래 기술에 따른 반도체 장치의 콘택홀 형성 공정 단면도1 is a cross-sectional view of a process for forming a contact hole in a semiconductor device according to the related art.
도2a 내지 도2d는 본 발명의 바람직한 일실시예에 따른 반도체 장치의 콘택홀 형성 공정 단면도2A to 2D are cross-sectional views of a contact hole forming process of a semiconductor device according to an embodiment of the present invention.
도3a 및 도3b는 본 발명의 일실시예에 따라 형성된 콘택홀의 단면을 보이는 SEM 사진3A and 3B are SEM photographs showing a cross section of a contact hole formed according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
20: 반도체 기판 21: 전도막 패턴20: semiconductor substrate 21: conductive film pattern
22: 제1 절연막 23: 제2 절연막22: first insulating film 23: second insulating film
24: 제3 절연막 25: 감광막 패턴24: third insulating film 25: photosensitive film pattern
상기와 같은 목적을 달성하기 위한 본 발명은, 반도체 기판 상에 형성된 다수의 전도막 패턴을 감싸는 제1 절연막을 형성하는 제1 단계; 상기 제1 절연막에 보다 식각 선택비가 큰 제2 절연막을 형성하는 제2 단계; 상기 제2 절연막 상에, 상기 제2 절연막보다 식각 선택비가 적은 제3 절연막을 형성하는 제3 단계; 상기 제3 절연막 및 제2 절연막을 건식 경사식각하여 상기 반도체 기판을 노출시키는 콘택홀을 형성하는 제4 단계; 및 상기 제3 절연막보다 제2 절연막에 대한 식각 선택비가 높은 식각제를 사용한 등방성 식각을 실시하여, 상기 제4 단계에서 형성된 콘택홀의 크기를 확대시키면서 상기 제3 절연막 부분의 콘택홀 폭이 상기 제2 절연막 부분의 콘택홀 폭보다 상대적으로 작은 콘택홀을 형성하는 제5 단계를 포함하는 반도체 장치의 콘택홀 형성 방법을 제공한다.The present invention for achieving the above object, a first step of forming a first insulating film surrounding a plurality of conductive film patterns formed on a semiconductor substrate; Forming a second insulating film having a larger etching selectivity on the first insulating film; Forming a third insulating film on the second insulating film, the third insulating film having an etching selectivity lower than that of the second insulating film; A fourth step of forming a contact hole exposing the semiconductor substrate by dry oblique etching the third insulating film and the second insulating film; And isotropic etching using an etchant having a higher etching selectivity with respect to the second insulating film than the third insulating film, thereby increasing the size of the contact hole formed in the fourth step and increasing the contact hole width of the third insulating film portion. Provided is a method of forming a contact hole in a semiconductor device, the method including forming a contact hole relatively smaller than the contact hole width of the insulating layer portion.
이하, 본 발명의 바람직한 일실시예에 따른 반도체 장치의 콘택홀 형성 단면도인 도2a 내지 도2d를 참조하여 본 발명을 설명한다.Hereinafter, the present invention will be described with reference to FIGS. 2A to 2D, which are sectional views of forming contact holes in a semiconductor device according to an embodiment of the present invention.
먼저, 도2a에 도시한 바와 같이 트랜지스터 등의 전도막 패턴(21) 형성이 완료된 반도체 기판(20) 상에 전도막 패턴을 감싸는 제1 절연막(22)을 형성한다.First, as shown in FIG. 2A, a first insulating film 22 surrounding the conductive film pattern is formed on the semiconductor substrate 20 on which conductive film patterns 21 such as transistors are completed.
다음으로, 도2b에 도시한 바와 같이 전체 구조 상에 층간절연 및 평탄화를 위한 제2 절연막(22)을 형성하되, 제1 절연막(22)과 식각 특성이 다른 물질로 제2 절연막(23)을 형성한다. 이어서, 제2 절연막(23) 상에 제2 절연막(23)과 식각 특성이 다른 제3 절연막(24)을 형성한 후, 제3 절연막(24) 상에 콘택홀을 형성하기 위한 감광막 패턴(25)을 형성한다. 이때, 이후의 콘택홀 형성으로 전도막 패턴(21)이 단락되지 않도록 상기 감광막 패턴(25)을 정의하여야 한다.Next, as shown in FIG. 2B, a second insulating film 22 for interlayer insulation and planarization is formed on the entire structure, and the second insulating film 23 is made of a material different from that of the first insulating film 22. Form. Subsequently, after the third insulating film 24 having different etching characteristics from the second insulating film 23 is formed on the second insulating film 23, the photoresist film pattern 25 for forming contact holes on the third insulating film 24 is formed. ). In this case, the photosensitive film pattern 25 should be defined so that the conductive film pattern 21 is not short-circuited by subsequent contact hole formation.
상기 제1 절연막(22) 및 제3 절연막(24)은 불순물이 도핑되지 않은 TEOS(tetra-ethyl-ortho-silicate)계 산화막, 저온 산화막(low temperature oxide), 중온 산화막(medium temperature oxide), 고온 산화막(high temperature oxide) 등으로 형성하고, 제2 절연막(23)은 BPSG(borophosphosilicate glass), PSG(phosphosilicate glass), BSG(borosilicate glass) 등으로 형성한다. 또는, 제1 절연막(22), 제2 절연막(23) 및 제3 절연막(24)을 모두 도핑된 산화막으로 형성하되, 제2 절연막(23)막의 불순물 도핑 농도가 제1 절연막(22) 및 제3 절연막(24)의 불순물 도핑 농도보다 높도록 한다.The first insulating layer 22 and the third insulating layer 24 may be formed of a tetra-ethyl-ortho-silicate (TEOS) oxide, a low temperature oxide, a medium temperature oxide, An oxide film or the like, and the second insulating film 23 is formed of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), or the like. Alternatively, the first insulating film 22, the second insulating film 23, and the third insulating film 24 are all formed of a doped oxide film, and the impurity doping concentration of the second insulating film 23 film is the first insulating film 22 and the first film. 3 It is higher than the impurity doping concentration of the insulating film 24.
다음으로, 도2c에 도시한 바와 같이 감광막 패턴(25)을 식각장벽으로 제3 및 제2 절연막(24, 23)을 건식 경사식각하여 전도막 패턴(21) 사이의 반도체 기판(20) 표면을 노출하는 콘택홀을 형성한다. 상기 건식 경사식각은, 가열된 실리콘 루프(heated silicon roof)가 장착된 ICP(Inductively Coupled Plasma) 방식의 고밀도 플라즈마 발생 장비에서 C3F8및 CO 가스를 식각제로 사용하여 실시한다. 이때, 실리콘 루프의 온도는 220 ℃ 내지 290 ℃이며, ICP의 RF 전력은 1600 W 내지 2800 W이고, 바이어스(bias) 전력은 600 W 내지 1800W로 한다. 또한, C3F8:CO의 비는 1:0.5 내지 1:5이며, 전체 가스량은 30 sccm 내지 150 sccm인 조건에서 건식 경사식각을 실시한다. 상기 건식 경사식각에서 식각제로 CF4, CHF3, CH3F, C2F6, C3F8, C4F8, CH2F2등과 같은 탄소 및 불소가 함유된 식각 가스를 사용하기도 한다.Next, as shown in FIG. 2C, the third and second insulating layers 24 and 23 are dry etched using the photoresist pattern 25 as an etch barrier, thereby forming a surface of the semiconductor substrate 20 between the conductive layer patterns 21. A contact hole for exposing is formed. The dry gradient etching is performed using C 3 F 8 and CO gas as an etchant in an inductively coupled plasma (ICP) type high density plasma generating apparatus equipped with a heated silicon roof. In this case, the temperature of the silicon loop is 220 ° C to 290 ° C, the RF power of the ICP is 1600 W to 2800 W, and the bias power is set to 600 W to 1800 W. In addition, the ratio of C 3 F 8 : CO is 1: 0.5 to 1: 5, and dry gradient etching is performed under the condition that the total amount of gas is 30 sccm to 150 sccm. In the dry gradient etching, an etching gas containing carbon and fluorine such as CF 4 , CHF 3 , CH 3 F, C 2 F 6 , C 3 F 8 , C 4 F 8 , and CH 2 F 2 may be used as an etchant. .
다음으로, 도2d에 도시한 바와 같이 제3 절연막(24)보다 제2 절연막(23)이 빨리 식각되는 조건으로 등방성 식각을 실시하여, 콘택홀의 크기를 확대시키면서도 콘택홀 입구의 폭을 원하는 크기로 형성한다.Next, as shown in FIG. 2D, the isotropic etching is performed under the condition that the second insulating film 23 is etched faster than the third insulating film 24, thereby increasing the size of the contact hole to a desired size. Form.
상기 등방성 식각은 인산(H3PO4) 용액 또는 NH4OH, H2O2및H2O가 혼합된 용액을 사용하여 습식식각을 실시하며 식각 온도는 상온 내지 식각 용액의 비등점이 되도록 한다. 또한, 등방성 식각을 CF4, CHF3, CH3F, C2F6, C3F8, C4F8, CH2F2등과 같은 탄소 및 불소가 함유된 식각 가스 또는 NH3가스를 사용하여 MDS(microwave down stream) 방식, ICP 방식, ECR(electron cyclotron resonance) 방식, HELICAL 방식 또는 TCP(transformer coupled plasma) 방식으로 실시하기도 한다.The isotropic etching is performed by wet etching using a solution of phosphoric acid (H 3 PO 4 ) or a mixture of NH 4 OH, H 2 O 2, and H 2 O, and the etching temperature is a boiling point of the room temperature to the etching solution. In addition, isotropic etching is performed using an etching gas or NH 3 gas containing carbon and fluorine such as CF 4 , CHF 3 , CH 3 F, C 2 F 6 , C 3 F 8 , C 4 F 8 , CH 2 F 2, etc. For example, it may be performed by a microwave down stream (MDS) method, an ICP method, an electron cyclotron resonance (ECR) method, a HELICAL method, or a TCP (transformer coupled plasma) method.
첨부된 도면 도3a 및 도3b는 상기와 같은 본 발명의 일실시예 따라 형성된 콘택홀의 단면을 보이는 SEM(scanning electron microscope) 사진으로, 도3a는 건식 경사식각을 한 후를 나타내며, 도3b는 등방성 식각을 실시한 후를 나타낸다. 도3b에서 알 수 있듯이 본 발명을 통하여 콘택홀의 크기를 넓히면서도 콘택홀 입구가 원하는 크기 이상으로 확대되는 것을 방지할 수 있다.3A and 3B are scanning electron microscope (SEM) photographs showing a cross section of a contact hole formed according to an embodiment of the present invention as described above. FIG. 3A shows a dry gradient etching, and FIG. 3B is isotropic. It shows after performing etching. As can be seen in Figure 3b through the present invention it is possible to prevent the contact hole entrance to extend beyond the desired size while increasing the size of the contact hole.
전술한 본 발명의 일실시예에서는 건식 경사식각으로 콘택홀을 형성한 후 습식식각을 실시하여 콘택홀을 확대하는 것을 설명하였지만, 습식식각 공정은 건식 경사식각 후의 세정 공정으로 대신될 수 있다. 즉, 세정 공정시 제2 절연막(23)이 제3 절연막(24)보다 빠르게 제거되도록 함으로써 콘택홀의 크기를 넓히면서도 콘택홀 입구가 의도한 이상으로 확대되는 것을 방지한다.In the above-described embodiment of the present invention, the contact hole is enlarged by performing wet etching after the contact hole is formed by the dry gradient etching, but the wet etching process may be replaced by the cleaning process after the dry gradient etching. That is, the second insulating film 23 is removed faster than the third insulating film 24 during the cleaning process, thereby preventing the contact hole entrance from expanding beyond the intended size while increasing the size of the contact hole.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 비교적 간단한 공정으로 콘택홀의 크기를 넓히면서도 콘택홀의 입구의 폭을 의도하는 크기 이상 확대되지 않도록 함으로써 콘택 저항 증가를 방지함과 동시에 후속으로 형성되는 전도막 패턴을 용이하게 정렬할 수 있다.The present invention as described above is a relatively simple process to increase the size of the contact hole, but not to increase the width of the inlet of the contact hole by more than the intended size to prevent the increase in contact resistance and at the same time easily align the subsequently formed conductive film pattern can do.
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| CN113517223B (en) * | 2021-06-29 | 2024-03-15 | 上海华力集成电路制造有限公司 | Method for manufacturing active area metal zero layer |
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