CN113517223A - Method for manufacturing active region metal zero layer - Google Patents
Method for manufacturing active region metal zero layer Download PDFInfo
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- CN113517223A CN113517223A CN202110723734.2A CN202110723734A CN113517223A CN 113517223 A CN113517223 A CN 113517223A CN 202110723734 A CN202110723734 A CN 202110723734A CN 113517223 A CN113517223 A CN 113517223A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 113
- 239000002184 metal Substances 0.000 title claims abstract description 113
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 87
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 238000001259 photo etching Methods 0.000 claims abstract description 11
- 238000004140 cleaning Methods 0.000 claims abstract description 6
- 239000011261 inert gas Substances 0.000 claims abstract description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 15
- 229910052721 tungsten Inorganic materials 0.000 claims description 15
- 239000010937 tungsten Substances 0.000 claims description 15
- 239000004020 conductor Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 239000011148 porous material Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 230000004888 barrier function Effects 0.000 description 4
- 238000002203 pretreatment Methods 0.000 description 4
- 238000007781 pre-processing Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003344 environmental pollutant Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 231100000719 pollutant Toxicity 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011165 process development Methods 0.000 description 1
- 230000026676 system process Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a manufacturing method of an active area metal zero layer, which comprises the following steps: step one, providing a semiconductor substrate for completing the front-end process. And step two, defining a forming area of the metal zero layer of the active area by photoetching. And step three, etching the interlayer film of the forming region of the active region metal zero layer to form a first middle section connecting groove. And fourthly, carrying out pretreatment before metal filling by adopting inert gas bombardment and plasma cleaning, and enlarging the size of the first middle section connecting groove by utilizing the pretreatment before metal filling and finally controlling the size and the shape of the first middle section connecting groove. And step five, filling metal in the first middle connecting groove to form an active area metal zero layer. The invention can well control the size and the appearance of the middle-section connecting groove, can improve the filling performance of the metal zero layer of the active region, and can simultaneously prevent the short circuit between the metal zero layer of the active region and the grid and the contact area with the active region from being too small.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing an active metal zero layer (M0A).
Background
After the front end of line (FEOL) process is completed, a middle of line (MOL) process is required, in which contact structures of the source region, the drain region and the top of the gate structure are formed, in order to realize a smaller contact structure, M0A is used for realizing contact with the source region and the drain region, and a gate connecting metal zero layer (M0P) is used for realizing contact with the gate structure. Both M0A and M0P are implemented by forming a middle connecting groove and then filling the middle connecting groove with metal, typically tungsten.
As line widths of advanced semiconductor processes are further reduced, the size of middle connecting trenches becomes smaller, and in 14nm fin transistor (FinFET) processes, the distance between gates of SRAM regions has been reduced to 90nm, and the size of middle connecting trenches has been smaller than 30 nm. The profile and size of the middle connection groove become a critical problem restricting the yield improvement of the advanced system process development, and the resistance and parasitic capacitance value of the device connection section are obviously influenced. Too small a dimension of the middle connection trench may cause an open circuit (open) with the active region; too large a dimension of the middle connection trench significantly increases the parasitic capacitance (C) and in severe cases even short circuits (short) to the gate, the dimension and profile of the middle connection trench also affects the filling of the subsequent metal, such as tungsten.
As the line width of advanced semiconductor processes further shrinks, the problem of tungsten filling in the middle connecting trench becomes more and more significant. Because middle section size is too little when tungsten is filled, seal at the top easily when the tungsten block is filled, lead to subsequent tungsten can not further be filled, and then lead to the inside gap and the cavity that exists of tungsten of filling, this can increase the resistance of linkage segment, gap and cavity in the tungsten also can further influence the filling of back end contact hole.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a manufacturing method of an active area metal zero layer, which can well control the size and the shape of a middle-section connecting groove, improve the filling performance of the active area metal zero layer, and simultaneously prevent short circuit between the active area metal zero layer and a grid electrode and over small contact area with an active area.
In order to solve the above technical problem, the method for manufacturing an active region metal zero layer provided by the present invention comprises the following steps:
step one, providing a semiconductor substrate for completing the front-stage process, forming a grid structure on the semiconductor substrate, and filling an interlayer film in a spacer of the grid structure.
And step two, defining a forming area of the metal zero layer of the active area by photoetching.
And step three, etching the interlayer film in the forming region of the active region metal zero layer to form a first middle section connecting groove.
And fourthly, carrying out pretreatment before metal filling by adopting inert gas bombardment and plasma cleaning, and utilizing the pretreatment before metal filling to enlarge the size of the first middle section connecting groove and finally control the size and the shape of the first middle section connecting groove.
And fifthly, filling metal in the first middle connecting groove to form the active area metal zero layer.
In a further improvement, in the first step, a drain region and a source region are formed in the semiconductor substrate on both sides of the gate structure, and the metal zero layer of the active region is formed on the top of both the drain region and the source region and forms a good contact.
In a further improvement, in step five, the metal material of the active region metal zero layer includes tungsten.
In a further improvement, in the fifth step, before the tungsten is formed, a step of forming a Ti layer and a TiN layer is further included.
The further improvement is that the photoetching definition in the second step ensures that short circuit cannot occur between the first middle section connecting groove and the grid structure after the etching in the third step is finished.
In a further improvement, in the fourth step, the pre-metal-filling pretreatment is to increase the top opening of the first middle-section connecting groove, and the pre-metal-filling pretreatment is required to ensure that the final size and shape of the first middle-section connecting groove can not generate pores or voids in the metal filling in the fifth step.
In a further improvement, the pre-metal fill pretreatment is required to ensure that the bottom area of the first middle segment connection trench is increased to reduce the contact resistance of the active region metal zero layer and the active region to a desired value.
In a further improvement, in the first step, the semiconductor substrate comprises a silicon substrate.
In a further improvement, a fin is further formed on the semiconductor substrate.
The further improvement is that the grid structure is formed by overlapping a grid dielectric layer and a grid conducting material layer.
In a further improvement, the gate dielectric layer comprises a high dielectric constant layer, and the gate conductive material layer comprises a metal gate.
In a further improvement, the metal gate comprises a metal work function layer and a metal conductive material layer.
A further improvement is that the top surface of the gate structure is also covered with the interlayer film.
The further improvement is that after the step three is completed and before the step four is performed, the method further comprises the following steps:
and forming a second middle connecting groove penetrating through the interlayer film on the top of the grid structure by adopting a photoetching and etching process.
And in the fourth step, the second middle section connecting groove is also treated by pretreatment before metal filling.
And step five, filling metal in the second middle connecting groove and forming a gate connecting metal zero layer.
The further improvement is that the step five comprises the following sub-steps:
the deposited metal completely fills the first and second middle section connecting grooves, and the metal also extends to the outside of the first and second middle section connecting grooves.
And carrying out a metal chemical mechanical polishing process to remove metal outside the first middle section connecting groove and the second middle section connecting groove.
According to the invention, the size and the appearance of the middle section connecting groove, namely the first middle section connecting groove, at the top of the active region such as a source region or a drain region are not directly determined through a photoetching and etching process, but the photoetching and etching process is adopted to form the first middle section connecting groove with a smaller size, so that short circuit between the first middle section connecting groove and the grid electrode can be well prevented; and then, preprocessing the first middle connecting groove before metal filling, namely preprocessing before metal filling, wherein the preprocessing before metal filling combines inert gas bombardment and plasma cleaning, so that pollutants in the etching process of the first middle connecting groove can be processed, the size of the first middle connecting groove can be enlarged, and the appearance with reduced top end necking can be formed.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a flow chart of a method for fabricating an active region metal zero layer according to an embodiment of the present invention;
fig. 2A-2F are schematic diagrams of device structures in steps of a method for manufacturing an active region metal zero layer according to an embodiment of the present invention.
Detailed Description
Fig. 1 is a flow chart of a method for manufacturing an active metal zero layer 110 according to an embodiment of the present invention; fig. 2A to fig. 2E are schematic diagrams of device structures in the steps of the method for manufacturing the active region metal zero layer 110 according to the embodiment of the present invention; the manufacturing method of the active region metal zero layer 110 of the embodiment of the invention comprises the following steps:
step one, as shown in fig. 2A, a semiconductor substrate 101 with a front-end process completed is provided, a gate structure 103 is formed on the semiconductor substrate 101, and an interlayer film 106 is filled in a spacer of the gate structure 103.
In the embodiment of the present invention, a drain region and a source region are formed in the semiconductor substrate 101 on both sides of the gate structure 103, and in fig. 2A, the source region and the drain region are symmetrically disposed on both sides of the gate structure 103 and are composed of source and drain regions 102. Typically, an embedded epitaxial layer is also formed in the source drain region 102.
The semiconductor substrate 101 includes a silicon substrate.
A fin is also formed on the semiconductor substrate 101. The fin body is formed by performing patterned etching on the semiconductor substrate 101, and the cross-sectional view of fig. 2A is a cross-sectional view along the length direction of the fin body.
The gate structure 103 is formed by stacking a gate dielectric layer and a gate conductive material layer.
The gate dielectric layer comprises a high dielectric constant layer 1031, and the gate conductive material layer comprises a metal gate.
The metal gate includes a metal work function layer 1032 and a metal conductive material layer 1034. Typically, there is also an interfacial layer between the high dielectric constant layer 1031 and the semiconductor substrate 101, a bottom barrier layer at the bottom of the high dielectric constant layer 1031, and a top barrier layer between the metal work function layer 1032 and the metal conductive material layer 1034.
The top surface of the gate structure 103 is also covered with the interlayer film 106.
In addition, the material of the metal conductive material layer 1034 includes tungsten or aluminum. Typically, the metal gate is formed using a gate-last process. After the metal gate is formed, the metal gate needs to be etched back, and a top dielectric layer 107 is formed on the top of the metal gate after etching back, where the top dielectric layer 107 is usually made of silicon nitride.
An etching barrier layer 105 is further formed on the outer surface of the semiconductor substrate 101 outside the gate structure 103, and the etching barrier layer 105 is typically made of silicon nitride.
Step two, as shown in fig. 2B, a forming region of the active region metal zero layer 110 is defined by photolithography.
In the embodiment of the present invention, the active region metal zero layer 110 is formed on top of both the drain region and the source region, and the active region metal zero layer 110 needs to form a good contact with the drain region and the source region.
The photolithographic definition in the second step ensures that no short circuit occurs between the first middle connection groove 108a and the gate structure 103 after the etching in the third step is completed.
Step three, as shown in fig. 2B, the interlayer film 106 in the formation region of the active region metal zero layer 110 is etched to form a first middle connection groove 108 a.
In the embodiment of the present invention, the etching of the interlayer film 106 is stopped on the etch stop layer 105. Then, as shown in fig. 2C, the etch stop layer 105 is further etched to expose the surface of the source/drain region 102 at the bottom.
And fourthly, as shown in fig. 2D, performing pretreatment before metal filling by adopting inert gas bombardment and plasma cleaning, and expanding the size of the first middle section connecting groove 108 by utilizing the pretreatment before metal filling and finally controlling the size and the shape of the first middle section connecting groove 108. In fig. 2D, the first middle connecting groove after the pre-treatment before the metal filling is individually marked with reference numeral 108.
In the embodiment of the present invention, the pre-treatment before the metal filling increases the top opening of the first middle connecting groove 108a, and the pre-treatment before the metal filling requires that the final size and shape of the first middle connecting groove 108a can not generate a void or a cavity in the metal filling in the subsequent step five. Meanwhile, the pre-treatment before metal filling is required to ensure that the bottom area of the first middle connection groove 108a is increased to reduce the contact resistance of the active region metal zero layer 110 and the active region to a required value.
Step five, as shown in fig. 2F, filling metal in the first middle connection groove 108 to form the active region metal zero layer 110.
In an embodiment of the present invention, the metal material of the active region metal zero layer 110 includes tungsten.
As shown in fig. 2E, before forming tungsten, a step of forming a Ti layer and a TiN layer 109 is further included.
After the third step is completed and before the fourth step is performed, the method further comprises the following steps:
a second middle connection trench (not shown) is formed through the interlayer film 106 on the top of the gate structure 103 by using a photolithography and etching process.
And in the fourth step, the second middle section connecting groove is also treated by pretreatment before metal filling.
And step five, filling metal in the second middle connecting groove and forming a gate connecting metal zero layer.
The fifth step comprises the following sub-steps:
the deposited metal completely fills the first and second middle connecting grooves 108a and extends to the outside of the first and second middle connecting grooves 108a and 108 b.
And performing a metal chemical mechanical polishing process to remove metal outside the first middle connecting groove 108a and the second middle connecting groove.
In the embodiment of the invention, the size and the appearance of the middle connecting groove at the top of the active region such as a source region or a drain region, namely the first middle connecting groove 108a, are not directly determined by a photoetching and etching process, but the first middle connecting groove 108a with a smaller size is formed by adopting the photoetching and etching process, so that the first middle connecting groove 108a and the grid electrode can be well ensured not to be short-circuited; and then, the first middle connection groove 108a is pretreated before metal filling, namely pretreatment before metal filling is carried out, and the pretreatment before metal filling combines with inert gas bombardment and plasma cleaning, so that pollutants in the etching process of the first middle connection groove 108a can be treated, the size of the first middle connection groove 108a can be enlarged, and the appearance with reduced top end necking can be formed, therefore, the embodiment of the invention can well control the size and the appearance of the middle connection groove, can improve the filling performance of the active area metal zero layer 110 so as to prevent filling defects such as gaps or cavities, can also prevent short circuit between the active area metal zero layer 110 and a grid electrode, and can also prevent the contact area between the active area metal zero layer 110 and an active area from being too small so as to reduce contact resistance.
The present invention has been described in detail with reference to the specific embodiments, but these are not to be construed as limiting the invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A method for manufacturing an active area metal zero layer is characterized by comprising the following steps:
step one, providing a semiconductor substrate for finishing a front-stage process, forming a grid structure on the semiconductor substrate, and filling an interlayer film in a spacer of the grid structure;
step two, defining a forming area of the metal zero layer of the active area by photoetching;
etching the interlayer film in the forming region of the active region metal zero layer to form a first middle section connecting groove;
carrying out pretreatment before metal filling by adopting inert gas bombardment and plasma cleaning, and expanding the size of the first middle section connecting groove by utilizing the pretreatment before metal filling and finally controlling the size and the shape of the first middle section connecting groove;
and fifthly, filling metal in the first middle connecting groove to form the active area metal zero layer.
2. The method of claim 1, wherein: in the first step, a drain region and a source region are formed in the semiconductor substrate on two sides of the gate structure, and the metal zero layer of the active region is formed on the tops of the drain region and the source region and forms a contact.
3. The method of claim 2, wherein: in the fifth step, the metal material of the active region metal zero layer comprises tungsten.
4. The method of claim 3, wherein: in the fifth step, before forming tungsten, a step of forming a Ti layer and a TiN layer is further included.
5. The method of claim 1, wherein: and step two, photoetching definition ensures that short circuit cannot occur between the first middle section connecting groove and the grid structure after etching in step three is completed.
6. The method of claim 5, wherein: in the fourth step, the opening at the top of the first middle connecting groove is increased by the pretreatment before metal filling, and the pretreatment before metal filling is required to ensure that the final size and shape of the first middle connecting groove can not generate pores or cavities in the metal filling in the fifth step.
7. The method of claim 6, wherein: the pretreatment before metal filling is required to ensure that the bottom area of the first middle section connecting groove is increased to reduce the contact resistance of the active region metal zero layer and the active region to a required value.
8. The method of claim 1, wherein: in the first step, the semiconductor substrate comprises a silicon substrate.
9. The method of claim 8, wherein: a fin body is also formed on the semiconductor substrate.
10. The method of claim 1, wherein: the grid structure is formed by superposing a grid dielectric layer and a grid conductive material layer.
11. The method of claim 10, wherein: the gate dielectric layer comprises a high dielectric constant layer, and the gate conductive material layer comprises a metal gate.
12. The method of claim 11, wherein: the metal gate comprises a metal work function layer and a metal conductive material layer.
13. The method of claim 11, wherein: the interlayer film is also covered on the top surface of the gate structure.
14. The method of claim 13, wherein: after the third step is completed and before the fourth step is performed, the method further comprises the following steps:
forming a second middle section connecting groove penetrating through the interlayer film on the top of the grid structure by adopting a photoetching and etching process;
in the fourth step, the pretreatment before metal filling also processes the second middle section connecting groove at the same time;
and step five, filling metal in the second middle connecting groove and forming a gate connecting metal zero layer.
15. The method of fabricating an active area metal zero layer of claim 14, wherein: the fifth step comprises the following sub-steps:
depositing metal to completely fill the first and second mid-section connecting slots, the metal also extending outside the first and second mid-section connecting slots;
and carrying out a metal chemical mechanical polishing process to remove metal outside the first middle section connecting groove and the second middle section connecting groove.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023082573A1 (en) * | 2021-11-15 | 2023-05-19 | 长鑫存储技术有限公司 | Contact structure forming method, semiconductor structure and memory |
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| US20050112869A1 (en) * | 2003-11-21 | 2005-05-26 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device |
| CN1725511A (en) * | 2004-05-24 | 2006-01-25 | 三星Sdi株式会社 | Semiconductor device and method of fabricating the same |
| CN108400109A (en) * | 2018-02-07 | 2018-08-14 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of contact hole |
| CN112017963A (en) * | 2019-05-31 | 2020-12-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000003922A (en) * | 1998-06-30 | 2000-01-25 | 김영환 | Method for forming a contact hole of semiconductor devices |
| US20050112869A1 (en) * | 2003-11-21 | 2005-05-26 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device |
| CN1725511A (en) * | 2004-05-24 | 2006-01-25 | 三星Sdi株式会社 | Semiconductor device and method of fabricating the same |
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| WO2023082573A1 (en) * | 2021-11-15 | 2023-05-19 | 长鑫存储技术有限公司 | Contact structure forming method, semiconductor structure and memory |
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