KR20000002753A - Real time clock watching device of exchanger - Google Patents

Abstract

PURPOSE: A real time clock watching device of an exchanger is provided to perform a prior maintenance by generating a real time clock error detection signal before duplexing division is performed. CONSTITUTION: A system comprises: a dummy cycle sensor(2) to sense the dummy cycle after receiving the dummy cycle information from its own CPU whenever the real time clock is generated; a counter(4) cleared whenever the dummy cycle is sensed and to count; a first comparator(6) to output a real time clock error detection signal; and a second comparator(8) to output an interrupt signal to perform the duplexing division.

Description

Real time clock monitoring device of the exchange

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for monitoring a real time clock of an exchange, and in particular, two boards each equipped with a central processing unit (CPU) in an exchange operate with redundancy of active and standby. The present invention relates to a real-time clock monitoring device of an exchange to monitor real-time clocks on the active and standby sides.

In this regard, the exchange processor board uses a real-time clock to perform periodic real-time tasks. For example, a real-time clock for performing periodic real-time tasks such as a telephony processor (TP) scanning subscriber lines every few milliseconds or reading interprocessor communication (IPC) data accumulated in a queue. Use

Therefore, if the real time clock is not normally provided to the processor board of the exchanger, problems will occur in the real time operation as in the above example.

In general, a processor's processor board monitors a real-time clock and generates a so-called "watch doc" if a real-time clock does not occur in a specified period, and attempts to perform redundant switching by transmitting a fault signal to the standby processor board.

If a "watch doc" occurs like this, it means that the active processor board cannot operate normally. If a "watch doc" occurs, a level 7 interrupt is generated. Allow two redundant processor boards to switch over, allowing the standby processor board to become active processor board.

In a switch system according to the related art, two boards each having a CPU operate in a redundant operation and standby mode, so that a counter is cleared every time a real time clock occurs on the active side and counted again from this time point. At this time, if a real-time clock is generated and the counter is not cleared and counts up to a specified threshold, a "watch doc" interrupt is generated, which eventually causes a level 7 interrupt to switch between the two redundant processor boards.

However, in this conventional technique, there is a problem in generating a real time clock, and if the counter is not cleared and counts up to a prescribed limit, a "watch doc" interrupt is generated. The only maintenance was to perform a redundancy switchover.

The present invention has been made to solve the above-mentioned shortcomings. In a system in which two boards each having a CPU at an exchange operate in a dual operation of active and standby, when a problem occurs in generation of a real time clock on the active side, a "watch doc" It is an object of the present invention to provide a real-time clock monitoring device of an exchange that can generate a real-time clock error detection signal before an interrupt occurs and the redundant switching is performed so that maintenance can be performed in advance.

In order to achieve the above object, the present invention provides a system in which two boards each having a CPU at an exchange operate in a redundant operation and standby, and receive dummy cycle information from their CPU whenever a real time clock is generated. A dummy cycle detection unit for detecting a dummy cycle, a counter that is cleared and counted every time the dummy cycle detection unit detects a dummy cycle, and a count value of the counter is determined by comparing the count value of the counter with a first reference count value. When the reference count value is exceeded, a first comparator for outputting a real-time clock error detection signal for preliminary maintenance before performing redundant switching, and comparing the counter value with the second reference count value of the counter If the count value exceeds the second reference count value, redundancy switching is performed. And a second comparator for outputting an interrupt signal to the controller.

1 is a block diagram showing an embodiment of a real time clock monitoring apparatus of an exchange according to the present invention;

2 is a timing diagram for explaining the operation of the real-time clock monitoring apparatus of the switch according to FIG.

<Description of the symbols for the main parts of the drawings>

2 dummy cycle detection unit 4 counter

6,8: first and second comparison unit

Hereinafter, the embodiment of the present invention as described in detail as follows.

1 is a block diagram showing an embodiment of a real time clock monitoring apparatus of an exchange according to the present invention. First, the dummy cycle detection unit 2 performs a dummy cycle from its CPU whenever a real time clock is generated as shown in FIG. 2B for a real time operation. Upon receiving the information, a dummy cycle as shown in FIG. 2C is sensed, and a clear signal is applied to the counter 4 at this time.

2A is a reference clock.

For example, the dummy cycle detector 2 receives dummy cycle information from its CPU when the first real time clock of FIG. 2b is generated, senses the first dummy cycle of FIG. 2c, and applies a clear signal to the counter 4. .

In addition, the dummy cycle detection unit 2 receives dummy cycle information from its CPU when the second real time clock of FIG. 2B is generated, detects the second dummy cycle of FIG. 2C, and applies a clear signal to the counter 4.

Next, the counter 4 repeatedly counts from "0" to "k" as shown in FIG. 2D whenever it is cleared according to the clear signal of the dummy cycle detecting unit 2.

At this time, "k" is any number.

Subsequently, the first comparator 6 compares the count value of the counter 4 with its preset reference count value n so that the count value of the counter 4 exceeds "k" as shown in FIG. 2E. When the reference count value is exceeded, a real time clock error detection signal is output at the "n" count as shown in FIG. 2F for preliminary maintenance before the redundant switching is performed, so that the system can be used for maintenance.

Then, the second comparison unit 8 compares the count value of the counter 4 with its own reference count value n + m, and the count value of the counter 4 becomes as shown in FIG. If exceeds, the "watch doc" interrupt signal is output at the "n + m" th count as shown in FIG. 2G to perform the redundant switching.

At this time, the reference count value (n + m) of the second comparator 8 is larger than the reference count value (n) of the first comparator 6, the technique for monitoring the real-time clock of the active side as described above It may be applied to the standby side to notify the active side when a problem occurs in the real time clock of the standby side so that the active side can know the state of the standby side.

As described above, in the present invention, in a system in which two boards each having a CPU at an exchange are operated with dual redundancy of active and standby, a "watch doc" interrupt is generated when a problem occurs in generation of a real time clock at the active side. Since the maintenance is performed in advance by generating a real-time clock error detection signal before the switching is performed, the number of redundant switching can be reduced, thereby reducing the possibility of service interruption.

In addition, the real-time clock error detection signal of the first comparator 6 may be separately managed through a means such as displaying a real-time clock failure for the exchange operator to see.

Claims (1)

In a system where two boards, each with a CPU at the exchange, operate with active and standby redundancy: A dummy cycle detection unit configured to detect dummy cycles by receiving dummy cycle information from a CPU whenever a real time clock is generated; A counter that is cleared and counted each time the dummy cycle detection unit detects a dummy cycle; Comparing the count value of the counter with the first reference count value and outputting a real time clock error detection signal for preliminary maintenance before performing the redundant switching when the count value of the counter exceeds the first reference count value. A first comparator; A second comparator including a second comparator configured to compare the count value of the counter with a second reference count value and output an interrupt signal for performing redundancy switching when the count value of the counter exceeds the second reference count value; Clock monitoring device.