KR19990031056U - Clock switching device using multiplexer - Google Patents

Abstract

The present invention relates to a clock switching device using a multiplexer, and more particularly, to a clock switching device that receives two identical clocks and automatically selects and uses a good clock among them.

The present invention includes a clock check circuit A for receiving and checking a clock on the A surface; A clock check circuit B for receiving and checking a clock on the B surface; And a clock select circuit for receiving a clock on the A plane, a clock on the B plane, and an output of the clock check circuits A and B to select a clock to be used in the system.

The present invention configured as described above can be usefully used in a system requiring fast clock switching and can be configured with a simple circuit. It is also possible to switch to any clock as well as to input clocks of 4.096MHz and 8KHz frame pulses.

Description

Clock switching device using multiplexer

The present invention relates to a clock switching device using a multiplexer (MUX), and more particularly, to a clock switching device that receives two identical clocks and automatically selects and uses a good clock.

The clock switching method according to the related art uses a method of processing a clock switching using a processor. The clock check circuit always monitors two incoming clocks. When an error occurs in either clock, the clock check circuit generates a clock failure signal. The processor periodically polls the output of the clock check circuit, and sends a control signal to select the normal clock when a clock failure signal is detected.

The clock switching method according to the related art, which operates as described above, performs switching using software in the processor, thereby simplifying hardware implementation. However, efficiency is reduced because the processor must poll the output of the clock check circuit periodically. In addition, since the clock switching is performed in software, a problem arises in that the clock switching time becomes long.

Therefore, in order to solve the problems described above, the present invention enables the processor in charge of clock switching to perform the switching by hardware by detecting this immediately in the clock selection circuit without periodically polling the state of the clock. It is an object of the present invention to provide a clock switching device using a multiplexer which prevents the degradation of the circuit and reduces the switching time.

1 is a block diagram of a clock switching device according to the present invention.

2 is an operation diagram of a clock selection circuit according to the present invention.

Explanation of symbols for the main parts of the drawings

110,120: clock check circuit

130: clock selection circuit

One preferred embodiment of the present invention designed to achieve the object as described above,

A clock check circuit A for receiving and checking a clock on the A surface;

A clock check circuit B for receiving and checking a clock on the B surface; And

A clock selection circuit is provided to select a clock to be used in the system by receiving the clock on the A side, the clock on the B side, and the outputs of the clock check circuits A and B.

In one embodiment of the present invention, the clock of the A surface and the clock of the B surface is preferably a clock having a different source and the same timing,

The clock check circuit A is provided with one or more A-plane clock signals, and if any one of the signals is abnormal, the clock check circuit A determines that the clock is a failure. If one signal is lost more than one clock, it is preferable to determine that the signal is abnormal,

Preferably, the clock check circuit B receives one or more B-plane clock signals, and determines that the clock on the corresponding surface is an error if any one of the signals is abnormal. The clock check circuit B is one of the one or more B-plane clock signals. If one signal is lost more than one clock, it is preferable to determine that the signal is abnormal,

Preferably, the clock selection circuit is a multiplexer (MUX) whose output signals of the clock check circuit A and the clock check circuit B are selected terminals.

Preferably, the clock selection circuit selects a clock on the A surface when both the clock on the A surface and the clock on the B surface are normal, and selects the clock on the normal surface when only one of the A and B surfaces is normal.

Preferably, the clock selection circuit selects a clock generated internally by the clock switching device when both the clock on the A surface and the clock on the B surface are abnormal.

1 is a block diagram of a clock switching device according to the present invention. As shown, the clock check circuit 110, 120 for detecting the state of the input clock; And a clock selection circuit 130 for selecting a normal clock. The input clocks include 4M_A, FP_A, 4M_B, and FP_B. Let 4M_A and FP_A be A side clocks, and 4M_B and FP_B be B side clocks. At this time, the A side clock and the B side clock are divided by a source. However, the A side clock and the B side clock are clocks having the same timing. In the device of the present invention, these clocks are input to select the preferred clock of the A side and the B side.

Hereinafter, the operation of the present invention will be described in detail with reference to the accompanying drawings. The A side and B side clocks are input to the clock check circuits 110 and 120, respectively. Each clock check circuit measures 4M and FP clock signals inputted, and determines that a failure is detected if any one of these signals is lost by more than one clock. For the clock signal determined to be a failure, 'high' is applied to the corresponding selection terminal of the clock selection circuit 130.

2 shows an operation diagram of a clock selection circuit according to the present invention. As shown in the drawing, the A side clock and the B side clock are input and have a structure of a multiplexer having the checked clock selection signals S0 and S1 as selection terminals. The clock selection circuit determines which of the A and B surfaces is selected by S0 and S1. The outputs according to the selection terminals S0 and S1 of the multiplexer are shown in Table 1.

S0 S1 Z0 Z1 0 0 A0 A1 0 One B0 B1 One 0 C0 C1 One One D0 D1

2, A0 and B0 are FP_A, and A1 and B1 are 4M_A. C0 is FP_B and C1 is 4M_B. I_FP and I_4M are self-generated clocks used in cases where both A and B sides are abnormal. That is, the operation of the entire apparatus according to the present invention is shown in Table 2.

S0 S1 Clock status Clock selection 0 0 A and B both normal 4M_A, FP_A optional 0 One Only A is normal One 0 B only normal 4M_B, FP_B optional One One A and B both abnormal Select I_4M, I_FP

If both A and B clocks are normal, select the A clock. If only one of A side and B side is normal, select clock of normal side. If both A and B sides are abnormal, the device selects its own 4M and FP clocks.

The present invention operating as described above can be usefully used in a system requiring fast clock switching and can be configured with a simple circuit. In addition, when the input clock is 4.096MHz and 8KHz frame pulse (Frame Pulse), it is possible to switch to any clock.

Claims (9)

A clock check circuit A for receiving and checking a clock on the A surface; A clock check circuit B for receiving and checking a clock on the B surface; And A clock switching device comprising a clock selection circuit for selecting a clock to be used in a system by receiving a clock on the A side and a clock on the B side and the outputs of the clock check circuits A and B. The clock switching apparatus of claim 1, wherein the clock on the A surface and the clock on the B surface are clocks having different sources and having the same timing. The clock switching device of claim 1, wherein the clock check circuit A receives one or more A-plane clock signals, and determines that the clock on the corresponding plane is an error if any one of the signals is abnormal. 4. The clock switching apparatus of claim 3, wherein the clock check circuit A determines that the corresponding signal is abnormal when any one of the one or more A-plane clock signals is lost by one or more clocks. The clock switching device of claim 1, wherein the clock check circuit B receives one or more B-plane clock signals, and determines that the clock on the corresponding plane is an error if any one of the signals is abnormal. The clock switching device of claim 5, wherein the clock check circuit B determines that a corresponding signal is abnormal when any one of one or more B-plane clock signals is lost by at least one clock. The clock switching device according to claim 1, wherein the clock selection circuit is a multiplexer (MUX) whose output signals of the clock check circuit A and the clock check circuit B are selected terminals. The clock selection circuit of claim 1, wherein the clock selection circuit selects a clock of the A surface when both the clock of the A surface and the clock of the B surface are normal, and selects the clock of the normal surface when only one of the A and B surfaces is normal. , Clock switching device using multiplexer. The clock switching device of claim 1, wherein the clock selection circuit selects a clock generated by the clock switching device when the clock on the A surface and the clock on the B surface are abnormal.