KR20010094293A - Managing method of the state of processors - Google Patents

Abstract

PURPOSE: A method for managing a status of a processor is provided to reduce a load of a system by reducing the IPC(Interprocess Communication) sending/receiving number of two seconds period corresponding to a normal processor. CONSTITUTION: An OMP(operation and maintenance processor) performs an answer-back test per 6-seconds period to a normal status processor(101). In the answer-back test, a "NOK(Not OK) message is displayed when no reply is progressed in 1¯2 times, and the corresponding processor is decided as the abnormal status when no reply is progressed in more than 3 times. If a power fail is generated in a processor, a H/W alarm control processor for sensing a hardware alarm senses the power fail as a hardware alarm bus, and a processor down is reported by the OMP(102). Thus, the OMP processes the corresponding processor as the abnormal status. If a managing-objected processor is the abnormal status, the OMP performs an answer-back test per 2-second period(103). If the abnormal processor normally replies continuously at 3 times in the answer-back test per 2-second period after load or by other reason, the OMP processes the corresponding processor as the normal status(104). Thus, the answer-back test is performed per 6-second period to a normal processor, and the answer-back test is performed per 2-second period to an abnormal processor(105).

Description

How to manage processor state {MANAGING METHOD OF THE STATE OF PROCESSORS}

The present invention relates to a method for managing the state of a processor in an electronic switchboard employing multiple processors.

A general structure of an exchange, which is one of the multiprocessor systems, may be represented as shown in FIG. 1 in terms of processor state management. The Operation and Maintenance Processor (OMP) 10 scans the state of all the processors 12, 14, and 16 periodically through the internal switching network to test the state by scanning the state. Manage it.

2 is a state transition diagram of a processor to be managed according to state management of a conventional all-electronic exchange. Currently, processor state management of exchanges such as the TDX-1B system is accomplished through a pure software method. That is, referring to FIG. 2, the OMP determines whether the processor is in a normal state through the answer-back of continuously receiving the response from each processor at the interval of 2 seconds. At this time, when no response is made once or twice, the message “NOK (Not OK)” is determined. When no response is made three times or more, the processor is determined to be an abnormal state. In the normal state recovery of an abnormal processor, the answer-back test as described above in a 2-second cycle shows an "OK" message for one or two responses and a normal (for three or more consecutive responses). normal).

As described above, the OMP processes the processor in an abnormal state when it continues to be unresponsive three times. In this way, the processor is abnormally treated six seconds after the processor is down. Likewise, since the processor is processed as normal in response to three abnormalities in case of abnormality, the processor is treated as normal only after six seconds.

The processor state management method as described above processes the processor in an abnormal / normal state when no response / response is performed more than three times, and thus it is impossible to inform the operator of the immediate down / recover state of the processor. There is no choice but to. In addition, because of the continuous sending and receiving of IPCs to all processors every two seconds, the increase in the Inter Processor Communication (IPC) load for state management increases. In addition, the processor can be abnormally managed in an instant due to non-response processing due to internal message delay.

Accordingly, an object of the present invention is to provide a processor management method that can reduce the system load by reducing the number of IPC send / receive (send / receive) of the normal processor for 2 seconds.

Another object of the present invention is to provide a processor management method that can notify an operator of a status change immediately upon down / recovery of a processor, thereby improving efficiency in system operation.

In order to achieve the above object, the present invention provides a state management method of a processor in an operation maintenance processor connected to an alarm control processor connected to a hardware bus and a processor for state management to monitor and notify of power failure. When the target processor is in a normal state, it performs an end-back test every 6 seconds to manage the state.The processor is treated as abnormal by the power fail detection signal from the alarm control processor, and the processor to be managed is abnormal. In one case, the state-management is performed by performing an end-back test every two seconds.

1 is a block diagram of an electro-electric exchanger as seen from the conventional state management aspect.

2 is a state transition diagram of a processor to be managed according to state management of a conventional all-electronic exchange.

Figure 3 is a block diagram of the electronic switchboard in terms of state management in accordance with an embodiment of the present invention.

4 is a flowchart illustrating a state management operation of an electronic switch according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, specific test cycles and specific details are shown, which are provided to help a more general understanding of the present invention. Such specific matters may be changed or changed within the scope of the present invention. It will be obvious to those of ordinary skill in the field.

Figure 3 is a block diagram of the electronic switch exchange in the state management aspect according to an embodiment of the present invention. Referring to FIG. 3, an operation maintenance processor (OMP) 10 manages the states of all processors 12, 14, and 16. In this case, the hardware bus is connected to each of the processors 12, 14, and 16 via a hardware bus to monitor the power fail of each of the processors 12, 14, and 16, and inform the OMP 10 of the failure. Is equipped with a hardware alarm control processor (SAIP) (HIP).

The OMP 10 makes an immediate state change using hardware alerts provided from the SAIP 18 upon power down / recovery of the processor. In addition, the normal processor performs state management through an end-back test of 6 seconds. If it is determined to be abnormal, the end-back test of 2 seconds is performed until it returns to a normal state. If the hardware alert is not detected due to a problem of the SAIP 18 itself, the existing state management method is followed. Hereinafter, the above operation will be described in more detail with reference to FIG. 4.

4 is a flowchart illustrating a state management operation of an electronic switch according to an embodiment of the present invention. Referring to FIG. 4, an OMP performs an answer-back test every six seconds for a processor that is in a normal state in step 101. Such an end-back test is a test for determining a "NOK (Not OK)" message in response to one or two non-responses as in the prior art, and determining the processor as an abnormal state in response to three or more non-responses. By the way, in the prior art, the end-back test was performed at a period of 2 seconds, but in the present invention, the end-back test is performed at a longer period, for example, 6 seconds. This is because SAIP can instantly recognize abnormal conditions of processors such as power failing.

That is, when a power fail occurs in the processor as in step 102, the SAIP that detects a hardware alert detects it as a hardware alert bus and reports the processor down to the OMP. As a result, OMP treats the processor as abnormal.

If the processor to be managed is in an abnormal state, the OMP performs an end-back test for 2 seconds until the processor becomes normal in step 103. Thereafter, in step 104, if an abnormal processor continues to respond three times in an end-back test of a two-second period normally after completion of loading or other causes, the OMP processes the processor as normal.

Afterwards, as in step 105, the OMP performs an end-back test on the processor every six seconds. Eventually, an end-back test is performed every 6 seconds for a normal processor and 2 seconds for a abnormal processor to manage the state. When the normal processor goes down, SAIP sends hardware alerts to OMP for immediate state management. . This state transition can be briefly expressed as follows.

Normal-> Abnormal: 6-second cycle of En-back test and hardware alarm

Abnormal-> Normal: Use Ensor-Back test with a 2-second cycle

On the other hand, if the hardware alarm is not detected due to the down of the SAIP processor, the existing six-second end-back test is performed during normal power failure of the normal processor. State management is performed, and when it returns to normal, it performs another six-second end-back test.

By the processor state management according to the features of the present invention as described above to reduce the system stabilization and system load. In this case, the number of IPCs for processor status check can be reduced by 66% compared to the conventional method. That is, the number of IPCs per hour for the conventional state check was 45,000 times when the 25 processors to be managed by the state were installed. However, according to the present invention, the number of processors was reduced to 15,000. This is calculated as follows.

Conventional Status Check IPC Count: 25 X 30 Times (1 Minute) X 60 Minutes = 45,000 Times

Number of IPCs according to the present invention: 25 X 10 times (1 minute) X 60 minutes = 15,000 times

In addition, according to the present invention, a system message "F391 NO ANSWER BACK", which is generated even when the processor is in a normal state due to a processor internal processing delay, is compensated for.

Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be defined by the described embodiments, but by the claims and equivalents of the claims.

As described above, the present invention can reduce the system load by reducing the number of conventional two-second IPC send / receive cycles to a normal processor, and also immediately change the status when the processor is down / recovered. The operator can be informed to improve the efficiency of system operation.

Claims (2)

In the processor state management method in the operation maintenance processor of the electronic switchboard which is pre-equipped with an alarm control processor connected to the hardware bus and the processor for state management to monitor and notify the power failure, Performing state management by performing an end-back test at a first preset period when the state management target processor is in a normal state, and processing the processor as an abnormal state by a power fail detection signal from the alarm control processor; And managing the state by performing an end-back test at a second preset period when the state-managed processor is in an abnormal state. The processor state management method of claim 1, further comprising: performing a state management by performing an end-back test at a third predetermined period when a problem occurs in the alarm control processor.