KR20000000876A - Thin film transistor substrate for lcd and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A thin film transistor substrate is provided to decrease the breakdown of a thin film transistor caused by the static electricity, to simplify the process and to decrease the disconnection of a wire. CONSTITUTION: The thin film transistor substrate manufacturing method composes the steps of; forming a gate line(20) to the horizontal wise on a transparent insulating substrate(100); forming a gate pad(22) on the end of the gate line(20); connecting a gate line connecting unit(24) with the gate pad(22) to connect the gate pad(22) each other; and covering the gate lines(20, 21, 22, 24) and common lines(10, 11) with a gate insulating film(30) consisting of the nitride silicon and the like.

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for manufacturing the same, and more particularly, to a liquid crystal display device having an electrode structure for applying a horizontal electric field and a thin film transistor that is an electric field application means.

The prior art as a liquid crystal driving method by a horizontal electric field is shown in US Patent No. 5,598, 285.

However, the liquid crystal display device disclosed in US Pat. No. 5,598,285 has uneven rubbing in the process of rubbing an alignment layer formed on the electrode by a step between two electrodes for applying a horizontal electric field, that is, a common electrode and a pixel electrode. This leaking problem is occurring.

In addition, the liquid crystal display device disclosed in US Pat. No. 5,598,285 has a structure in which both electrodes for forming a horizontal electric field are formed on one substrate, and thus have a structure vulnerable to static electricity flowing from the outside. There is a problem that a phenomenon occurs that is destroyed by.

To solve this problem, a method of electrically shorting the gate wiring and the data wiring during the process and separating them at the completion stage of the product is used. However, in this case, a process of connecting the wiring to each other is added, thereby increasing the number of processes.

An object of the present invention is to eliminate the light leakage phenomenon in the liquid crystal display device of the horizontal electric field drive method.

Another object of the present invention is to reduce the destruction of the thin film transistor by static electricity.

Another object of the present invention is to simplify the process of the liquid crystal display device of the horizontal electric field driving method.

Another object of the present invention is to reduce the disconnection of the wiring.

Another object of the present invention is to improve the mounting reliability by strengthening the contact force when mounting the drive driver.

1 is a layout view of an entire substrate for a liquid crystal display according to a first embodiment of the present invention;

FIG. 2 is a layout view illustrating a unit pixel, a gate pad, a gate pad connector, a data pad, and a data pad connector of a substrate for a liquid crystal display according to a first exemplary embodiment of the present invention.

3 to 7 are cross-sectional views taken along the lines III-III ', IV-IV', V-V ', VI-VI', and VII-VII 'of FIG. 2, respectively.

8A to 11E are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention.

12A to 14E are cross-sectional views illustrating a method of manufacturing a liquid crystal display according to another exemplary embodiment of the present invention.

15 is a layout view illustrating a unit pixel, a gate pad, a gate pad connector, a data pad, and a data pad connector of a substrate for a liquid crystal display according to another exemplary embodiment of the present invention.

16 to 20 are cross-sectional views taken along the lines XVI-XVI ', XVII-XVII', XVIII-XVIII ', XIX-XIX', and XX-XX 'of FIG. 15, respectively.

21 is a plan view illustrating a unit pixel and a pad unit of a substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 22 is a cross-sectional view taken along the line XXII-XXII 'of FIG. 21,

FIG. 23 is an equivalent circuit diagram of the structure shown in FIG. 22,

24 is a plan view of a substrate for a liquid crystal display according to a third exemplary embodiment of the present invention.

In order to solve the above technical problem, in the present invention, a gate wiring including a gate line, a gate electrode, a gate pad, and a gate line connecting portion is formed on a substrate, and a gate insulating film is formed on the gate wiring and the common wiring. A semiconductor layer and an ohmic contact layer are formed on the gate insulating layer on the gate electrode, and a data line including a source and drain electrode, a data line, a data pad, and a data line connection part and a pixel electrode are formed thereon as a first conductive layer. A protective film is formed on the data line and the pixel electrode, and a redundant data line including a redundancy data line, a redundant data pad, and a redundant data line connection part is formed as a second conductive layer on the protective layer. do. The redundant data line is electrically connected to the data line through a contact window formed in the passivation layer, and the redundant gate pad and the redundant gate line connection part are electrically connected to the gate pad and the gate line connection part through the contact window formed in the gate insulating film and the passivation layer. The redundant gate line connection unit and the redundant data line connection unit are connected to each other to short-circuit the gate and the data line on the substrate.

After completing the substrate, the substrate is subjected to the usual manufacturing process such as alignment film printing and rubbing, and then the edge of the substrate is cut to remove the gate line connecting portion and the data line connecting portion.

The pixel electrode may be formed in the process of forming the redundant data line using the second conductive layer instead of forming the data line using the first conductive layer, and the pixel electrode may be 500 Å or less. good.

The redundant data line may be formed as a single layer or a double layer, and the single layer or the upper layer constituting the redundant data line may be formed of a pad material that is not easily disconnected during the manufacturing process.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

First, the structure of the liquid crystal display substrate according to the first embodiment of the present invention will be described. 1 is a layout view briefly illustrating an entire configuration of a liquid crystal display according to a first exemplary embodiment of the present invention.

As shown in FIG. 1, a plurality of gate lines 20 are formed in a horizontal direction on the substrate 100, and a plurality of common electrode lines 10 are formed in parallel with the gate line 20. Gate pads 22 connected to gate drivers (not shown) are formed at the ends of the gate lines 20, and the gate pads 22 are all connected by the gate line connectors 24. In the vertical direction, the plurality of data lines 60 are formed to be insulated from and cross the gate line 20 and the common electrode line 10, and are connected to a data driver (not shown) at the end of the data line 60. The data pads 63 are formed, and the data pads 63 are also connected to each other by the data line connectors 64. The gate line connecting portion 24 and the data line connecting portion 64 are connected to each other with a resistance therebetween so that the gate line 20 and the data line 60 of the entire substrate are short-circuited by the connecting portions 24 and 64. . The connection of all the wirings is to protect the thin film transistors by effectively dissipating static electricity generated during the manufacturing process of the liquid crystal display substrate. When the liquid crystal display substrate is completed, it is along the cutting line 200 indicated by a dotted line on the drawing. The outer portions of the pads 22 and 63 are cut to separate the wires from each other.

Each pixel is defined by the intersection of the gate line 20 and the data line 60, the substrate is divided into a plurality of pixels, and a linear pixel electrode and a common electrode are alternately formed in each pixel area.

Now, the structure of the unit pixel of the liquid crystal display according to the first embodiment of the present invention will be described in detail. FIG. 2 is a layout view illustrating a unit pixel, a gate pad, a gate pad connector, a data pad, and a data pad connector of the liquid crystal display as shown in FIG. 1, and FIGS. 3 to 7 are III-III ′ and IV of FIG. 2, respectively. Sections along the lines IV ', V-V', VI-VI ', VII-VII'.

2 to 7, the gate line 20 is formed in the horizontal direction on the transparent insulating substrate 100, and the gate pad 22 is formed at the end of the gate line 20. Part of the gate line 20 becomes the gate electrode 21. The common electrode line 10 is formed in parallel with the gate line 20, and a plurality of common electrodes 11 are connected to the common electrode line 10 in the pixel area to receive a common signal from the common electrode line 10. ) Is formed. On the other hand, a gate line connecting portion 24 connecting the gate pads 22 to each other is connected to the gate pads 22.

The gate insulating film 30 made of silicon nitride or the like is covered on the gate wirings 20, 21, 22, 24 and the common wirings 10, 11.

The channel layer 40 of the thin film transistor made of amorphous silicon is formed on the gate insulating layer 30 on the gate electrode 21, and the amorphous silicon doped with high concentration of phosphorus (P) or the like is formed on the amorphous silicon layer 40. The ohmic contacts 51 and 52 are formed on both sides of the gate electrode 21.

A source electrode 61 and a drain electrode 62 made of metal are formed on the ohmic contact layers 51 and 52, respectively, and the source electrode 61 is formed in the vertical direction on the gate insulating layer 30. 60, the drain electrode 62 is connected to the pixel electrode 65 that is linearly formed alternately with the common electrode 11 in the pixel area. A data pad 63 for receiving an image signal from the outside is formed at the end of the data line 60, and the data pads 63 are all connected by the data line connection unit 64.

The gate electrode 21, the gate insulating film 30, the amorphous silicon layer 40, the ohmic contact layers 51 and 52, the source and drain electrodes 61 and 62 form a thin film transistor, and the thin film transistor and the remaining data wirings. The protective film 70 covering the (60, 63, 64, 65) is made of silicon nitride or the like.

In the passivation layer 70, contact windows 71, 73, and 75 are formed to expose portions of the data line 60, the data pad 63, and the data line connection unit 64, respectively. Contact windows 72 and 74 are formed at 30 to expose the gate pad 22 and the gate line connecting portion 24, respectively.

The metal patterns 80 and 83 are formed on the passivation layer 70 in the same manner as the data lines 60 and 63, and the data lines 60 and 63 are formed through the contact windows 71 and 73 formed in the passivation layer 70. And redundancy data lines 80 and 83 are connected to each other. Other metal patterns 85 and 84 formed long in the horizontal direction and the vertical direction are formed on the passivation layer 70, and the horizontal metal pattern 85 is connected to the redundant data pad unit 83. The metal patterns 84 are connected to the gate line connecting portions 24 through the contact windows 74, respectively. Meanwhile, a metal pattern 82 overlapping the gate pad 22 is also formed on the passivation layer 70 and connected to the gate pad 22 through the contact window 72.

Now, a method of manufacturing the liquid crystal display substrate according to the first embodiment of the present invention will be described. 8A to 11E are cross-sectional views illustrating a process of manufacturing a substrate for a liquid crystal display as shown in FIGS. 1 to 7. The manufacturing method according to the embodiment of the present invention is a manufacturing method using five masks, and the alphabets a to e shown in the reference numerals refer to a pixel region, a thin film transistor region, a gate pad region, a data pad region, It shows that the gate line connection portion is shown.

First, as shown in FIGS. 8A to 8E, a metal layer having a thickness of about 3000 μs is deposited on a transparent insulating substrate 100 such as glass, and patterned using a first mask to form a gate line 20 and a gate electrode 21. The gate pad 22, the gate line connection part 24, the common electrode 11, and the common electrode line 10 are formed. In this case, various conductive materials may be used as the gate wiring metal, and chromium, aluminum, aluminum alloy, molybdenum, or the like may be used, or the gate wiring may be formed by a double layer combining these metals.

Next, as shown in FIGS. 9A to 9E, an insulating gate insulating film 30 such as silicon nitride or an organic insulating film is formed on the entire surface of the substrate to a thickness of 3,000 to 5,000 GPa, and an amorphous silicon layer having a thickness of about 500 to 2,000 GPa ( 40) and an amorphous silicon layer 50 heavily doped with impurities such as phosphorous having a thickness of about 500 GPa are sequentially deposited. The doped amorphous silicon layer 50 and the amorphous silicon layer 40 are patterned together using a second mask to form an island shape on the gate electrode 21.

As shown in FIGS. 10A to 10E, a metal layer such as chromium, an aluminum alloy, or molybdenum is deposited at about 500 GPa or less and patterned using a third mask to pattern the data line 60 crossing the gate line 20. Source and drain electrodes 61 and 62, a data pad 63, a data line connector 64, and a pixel electrode 65 are formed. Next, the doped amorphous silicon layer 50 is etched by etching the doped amorphous silicon layer 50 using the source electrode 61 and the drain electrode 62 as a mask, and the resistive contact layer 51 is separated from each other by the gate electrode 21. , 52).

As shown in FIGS. 11A through 11E, a protective film 70 having a thickness of 1,500 to 2,500 Å is formed on the entire surface of the substrate using silicon nitride or an organic insulating film, and patterned using a fourth mask to form a data line 60 and a data pad ( The contact windows 71 and 73 respectively exposing the 63 are formed, and the gate insulating film 30 and the protective film 70 on the gate pad 22 and the gate line connecting portion 24 are also removed to remove the contact windows 72 and 74. To form.

Finally, as shown in FIG. 3 to FIG. 7, a single film or a plurality of films of molybdenum, molybdenum alloy, or aluminum alloy is deposited to a thickness of 2,000 to 2,500 Pa, and patterned using a fifth mask to form a data line 60. ), Redundant data lines 80, 83, 85, 82, 84 similar to the data pad 63, the gate pad 22, and the gate line connecting portion 24 are formed.

Thereafter, an alignment layer is formed on the surface of the substrate and subjected to a rubbing process to give the orientation of the liquid crystal material. Finally, the gate line connection unit and the data line connection unit are separated and removed.

In the liquid crystal display device according to the first embodiment of the present invention, the pixel electrode is made as thin as possible to about 500 kHz, thereby reducing the step difference between layers and reducing the uneven alignment caused by the rubbing process, thereby reducing the light leakage phenomenon, and redundant data wiring. The portion is a portion other than the pixel region, and the thickness is less than that of the pixel electrode layer, so that the portion is formed thicker to about 2,000-2,500 GHz to lower the resistance of the wiring. In addition, since the redundant data wiring portion constitutes the pad portion, it is preferable to use a material having high contact reliability when mounting the driver integrated circuit.

Redundant data wiring may use indium tin oxide (ITO), or if the upper layer is formed of ITO with another metal layer underneath, the contact reliability with the driver may be further improved.

By changing the process order in the above first embodiment, as shown in FIGS. 12A to 13E, the data lines 60, 61, 62, and 63 are first formed on the gate insulating film 30, and then the protective film 70 is formed. And forming contact windows 71, 72, 73, 74, 75, and 76 in the passivation layer 70, and then, as shown in FIGS. 14A through 14E, the pixel electrode 65 and the pixel electrode line 66 on the passivation layer 70. ), Redundant data wirings 80, 82, 83, and 84 may be formed. In this case, it is advantageous to form the thickness of the pixel electrode at about 500 mW or less in terms of preventing light leakage. On the other hand, in this case, since the metal forming the pixel electrode forms the pad portion, it is preferable to form the pixel electrode with chromium, molybdenum, molybdenum alloy or the like which can have reliability as the pad portion.

In addition, unlike the first embodiment of the present invention in which a portion of the passivation layer on the data line is removed to be electrically connected to the redundant data line, as shown in FIGS. 15 to 20, the passivation layer formed on the data lines 60, 63, and 64. When all the 70 are removed and the redundant data wirings 80, 83, 85 are formed thereon, the contact resistance between the data wirings 60, 63, 64 and the redundant data wirings 80, 83, 85 is reduced, The data wires 80, 83, 85 enter the space between the passivation layers 70, thereby reducing the step difference.

In the first embodiment of the present invention, both the gate line connection part and the data line connection part are formed in double, and the redundant gate line connection part and the redundant data line connection part are connected to each other to short the gate line and the data line. Rather than forming one or both of the redundant data line connection parts, a pattern for connecting the data line connection part and the gate line connection part may be formed when the redundant data line is formed.

Meanwhile, the liquid crystal display according to the second exemplary embodiment of the present invention provides a structure capable of preventing a short circuit between the gate line and the common electrode line.

FIG. 21 is a plan view illustrating a structure of a unit pixel of a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 22 is a cross-sectional view taken along the line XXII-XXII 'of FIG. 21.

As shown in FIG. 21 and FIG. 22, one common electrode line 10 transmitting a common signal is formed for each pixel row in the horizontal direction. The pixel electrode lines 67 connecting the pixel electrodes 65 to each other are formed to overlap the common electrode line 10 with the gate insulating layer 30 interposed therebetween, and one pixel electrode line 67 is also formed per unit pixel. On the passivation layer 70 on the pixel electrode line 67, a storage capacitor metal layer 87 made of the same metal as the redundant data line 80 is formed to overlap the pixel electrode line 77 with the passivation layer 70 therebetween. The metal layer 87 for storage capacitance is electrically connected to the common electrode line 10 through the contact hole 77 formed in the protective film 70.

As shown in FIG. 21, since only one common electrode line 10 is formed above the pixel, there is no fear that the gate line 20 and the common electrode line 10 below the pixel are short-circuited.

On the other hand, when only one common electrode line 10 is formed, the storage capacitance is reduced compared to the liquid crystal display device according to the second embodiment of the present invention. However, as shown in FIGS. 24 and 25, the common electrode line 10 is connected to the common electrode line 10. By forming the storage capacitor electrode 87 overlapping with the pixel electrode line 67 in the same layer as the redundant data line, sufficient storage capacitance can be ensured.

FIG. 23 is an equivalent circuit diagram showing the storage capacitance when the storage capacitor electrode 87 is electrically connected to the common electrode line 10 as shown in FIGS. 21 and 22. Since a constant voltage is applied to the common electrode line from the outside, the common electrode line is marked as ground. As shown in FIG. 23, the common electrode line 10 and the storage capacitor electrode 87 that receive a common signal become one terminal of both storage capacitors Cst1 and Cst2, respectively, and the opposite terminals of the two storage capacitors are pixel electrode lines ( 67). The pixel voltage Vp is applied to the pixel electrode line 67. Therefore, in the third embodiment of the present invention, even if the common electrode line 10 is formed on only one side, one storage capacitor Cst2 is further formed by the storage capacitor electrode 87 formed on the passivation layer 70 and the two storage capacitors ( Since Cst1 and Cst2 are connected in parallel, it is possible to secure a holding capacity similar to the case where two common electrode lines 10 are formed.

Shortening between the gate line and the common electrode line can be further reduced by forming the pixel structure symmetrically so that the common electrode lines of adjacent pixels are adjacent to each other so that the gate line is not close to the common electrode line.

24 is a plan view of a liquid crystal display according to a fourth exemplary embodiment of the present invention. In FIG. 24, only the gate line, the common electrode line, the data line, the pixel electrode, and the common electrode are illustrated, and the thin film transistor and the like are not shown in detail. The remaining structure, which is not shown in detail, is similar to the third embodiment of the present invention shown in FIG.

As shown in FIG. 24, a gate line 20 and a common electrode line 10 are formed in a horizontal direction on a substrate, and gate lines 20 of adjacent pixels are adjacent to each other, and common electrode lines 10 of adjacent pixels are adjacent to each other. The common electrode lines 10 are adjacent to each other. Therefore, in the liquid crystal display having the above structure, since the gate line 20 and the common electrode line 10 are not adjacent to each other, there is no fear that the gate line 20 and the common electrode line 10 are short-circuited.

The common electrode line 10 overlaps the pixel electrode line 67 with a gate insulating film (not shown) interposed therebetween, and the pixel electrode line 67 is again provided with a protective film (not shown) with the redundant data line 80 interposed therebetween. It overlaps with the storage capacitor electrode 88 which consists of a layer like this. In the fourth exemplary embodiment of the present invention illustrated in FIG. 24, the storage capacitor electrode 88 is formed to overlap the pixel electrode line 67 of two adjacent pixels, and the common electrode line is formed through a contact hole (not shown) formed in the passivation layer. Electrically connected with 10. In this way, as in the third embodiment, two storage capacitors connected in parallel for one pixel are formed, thereby ensuring sufficient storage capacitance.

In the fourth embodiment of the present invention, the storage capacitor electrode 88 is formed so as to overlap the pixel electrode line 67 of two adjacent pixels, but without doing so, the two storage cells overlapping the pixel electrode line 67 of each pixel. Capacitive electrodes may be formed. In addition, it is also possible to form a combination of two adjacent common electrode lines for transmitting a common signal to two adjacent pixels.

When the redundant data line is formed as in the liquid crystal display according to the present invention, the disconnection of the data line can be prevented, and the thin film transistor can be formed in a uniform pattern by forming a thin thickness of the source and drain electrodes. In addition, the process can be simplified by forming a liquid crystal display device having redundant data wiring using five masks, and by using a pad material on the upper portion of the pad portion or the redundant pad portion, the contact force when mounting the driving driver is enhanced. The mounting reliability can be improved. In the two adjacent pixels, the gate lines are formed so that the common electrode lines are adjacent to the common electrode lines, thereby preventing a short circuit between the gate line and the common electrode line.

Claims (8)

Board, A gate line formed on the substrate and transferring a scan signal from the outside; A gate electrode connected to the gate line, A common electrode line formed separately from the gate line on the substrate and transferring a common signal from the outside; A common electrode connected to the common electrode line; A gate insulating film covering the gate line, the gate electrode, the common electrode line, and the common electrode, A semiconductor layer formed on the gate insulating film corresponding to the gate electrode; Source and drain electrodes formed on both sides of the gate electrode on the semiconductor layer; A data line formed on the gate insulating layer to cross the gate line and connected to the source electrode; A pixel electrode formed on the gate insulating film in a pixel region defined by the intersection of the gate line and the data line, and connected to the drain electrode; A pixel electrode line connected to the pixel electrode and overlapping the common electrode line with the gate insulating layer interposed therebetween; A passivation layer covering the pixel electrode, the pixel electrode line, the source and drain electrodes, and the data line; A storage capacitor electrode overlapping the pixel electrode line and the passivation layer; The passivation layer and the gate insulating layer have a first contact hole exposing the common electrode line so that the storage capacitor electrode and the common electrode line are electrically connected through the first contact hole. In claim 1, And a redundant data line formed on the passivation layer so as to overlap the data line. The passivation layer has a second contact hole for exposing the data line, and the redundant data line and the data line are electrically connected to each other through the second contact hole. In claim 2, And the storage capacitor electrode and the redundant data line are formed of the same conductive layer. Board, A plurality of gate lines formed parallel to each other on the substrate, A plurality of common electrode lines formed separately from the gate lines on the substrate, A plurality of data lines insulated from and intersecting the gate line and the common electrode line; A pixel region in which a common electrode and a pixel electrode are formed to face each other at a predetermined interval in an area defined by the intersection of the gate line and the data line; A thin film transistor having a gate electrode, a source electrode, and a drain electrode connected to the gate line, the data line, and the pixel electrode; A pixel electrode line connecting the pixel electrodes to each other and overlapping the common electrode line; An insulating film formed in contact with the pixel electrode line, A storage capacitor electrode overlapping the pixel electrode and the insulating layer therebetween and electrically connected to the common electrode line; Each of the gate line and the common electrode line is paired with each other so that the two paired gate lines are adjacent to each other, and the paired two common electrode lines are adjacent to each other, thereby forming the pair of two gate lines or And a gate line and a common electrode line arranged in a symmetrical form with respect to the pair of two common electrode lines. In claim 4, And a plurality of redundant data lines formed on the insulating layer to overlap the data lines. And the redundant data line is electrically connected to the data line. In claim 5, And the storage capacitor electrode and the redundant data line are formed of the same conductive layer. Forming a gate line and a common electrode line on the substrate, Forming a gate insulating film covering the gate line and the common electrode line; Forming a pixel electrode, a pixel electrode line, and a data line on the gate insulating layer; Forming a passivation layer covering the pixel electrode, the pixel electrode line, and the data line; And forming a storage capacitor electrode overlapping the pixel electrode line on the passivation layer. In claim 7, And forming a redundant data line overlapping the data line in the step of forming a storage capacitor electrode on the passivation layer.