KR19990071006A - Digital Output Board Fault Safety Circuit - Google Patents

Abstract

A digital output board having a comparator, a decoder, and a buffer, the digital output board comprising: a signal detector for detecting a signal output from the comparator, first and second OR gates for ORing the signal decoded by the decoder; First and second latching units receiving and latching data output from the buffer and decoder, and first and second receiving and multiplexing data output from the buffer and data latched from the first and second latching units; A second multiplexer, third and fourth input data output by performing an OR operation on the first and second OR gates, and data multiplexed by the first and second multiplexers and output to the field; It detects the output signal of the comparator, including the latch part, and judges the failure of the CPU or the interface circuit, thereby preventing safety accidents. It is possible to increase the effect.

Description

Digital Output Board Fault Safety Circuit

The present invention relates to a digital output board, and more particularly to a failure safety circuit of the digital output board.

In general, various equipments used for factory automation use digital output boards to operate field devices as desired. If a fault occurs in the CPU or the interface circuit between the CPU and the digital output board during operation, all current digital output boards maintain the output state just before the fault.

Hereinafter, the prior art will be described with reference to the accompanying drawings.

1 is a block diagram showing a digital output board according to the prior art.

As shown in Fig. 1, a comparator 1, a decoder 2, a buffer 3, and first to fourth latch portions 4, 5, 6 and 7 are comprised.

The comparator 1 compares the control signal output from the CPU (not shown) with the address of the digital output board, and generates a / mybd signal when the value compared with the comparator 1 matches. The / mybd signal enables the buffer 3 to accept data.

The decoder 2 decodes the lower address input from the CPU (not shown) so that the first output DCD1 is used as clock pulses of the first and second latch units 4 and 5, and the second output DCD2. ) Are used as clock pulses of the third and fourth latch parts 6 and 7, and the first to fourth latch parts 4, 5, 6, and 7 are output from the buffer 3. It receives data and outputs it to the field.

Therefore, the CPU (not shown) always maintains the state before transmitting new data to the digital output board.

The digital output board according to the prior art does not receive new data from the CPU when the CPU or the interface device between the CPU and the digital output board fails. Therefore, the digital output board must be kept constant at all times. Maintaining this may adversely affect the entire production process.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and by detecting a signal of a comparator, it is possible to determine a failure of a CPU or an interface device, and to detect a digital output board fault detection circuit that can output safe data remaining on the digital output board. The purpose is to provide.

1 is a block diagram showing a digital output board according to the prior art

Figure 2 is a block diagram showing a digital output board failsafe circuit according to the present invention

Explanation of symbols for main parts of the drawings

11: comparator 12: decoder

13: buffer 21a: first or gate

21b: second or gate 22: signal detection unit

23: first multiplexer 24: second multiplexer

25: first latch portion 26: second latch portion

27: third latch portion 28: fourth latch portion

R1: resistor C1: capacitor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital output board, comprising: a signal detector for detecting a signal output from the comparator, and a logical sum (OR) operation of the signal decoded by the decoder First and second latch gates for receiving and latching first and second OR gates, data output from the buffer and decoder, data output from the buffer and the first and second latch units First and second multiplexers for receiving and multiplexing data output from the data, OR and OR data output from the first and second OR gates, and data multiplexed and output from the first and second multiplexers. It comprises a third and fourth latch unit for receiving the input and output to the field, it is characterized by.

Hereinafter, with reference to the accompanying drawings as follows.

2 is a block diagram showing a failure safety circuit of the digital output board according to the present invention.

As shown in FIG. 2, the present invention provides a signal detector for detecting a signal output from the comparator 11 in a digital output board including a comparator 11, a decoder 12, and a buffer 13. (22), resistors R1 and capacitors C1 for determining the time constant of the signal detector 22, and first and second orders for ORing the signals decoded by the decoder 12. OR gates 21a and 21b, first and second latches 25 and 26 for receiving and latching data output from the buffer 13 and decoder 12, and the buffer ( 13 and the first and second multiplexers 23 and 24 which receive and multiplex the data output from the first and second latch units 25 and 26.

In addition, the upper address is connected to the comparator 11 from the CPU (not shown), the lower address is connected to the decoder 12, and the data bus is connected to the buffer 13.

The output signal / mybd of the comparator 11 is input to the / EN terminals of the decoder 12 and the buffer 13 and connected to the input signal of the signal detector 22.

The outputs cp1, cp2, and preset1 of the decoder 12 are input signals of the first or second gate 21a and the second or gate 21b, respectively, and the first latch unit 25 and the first latch unit 25. 2 is input to the clock pulse terminal of the latch section 26.

The output cpa of the signal detector 22 is connected to the inputs of the first or second gate 21a and the second or gate 21b, and the output emg is the first and second multiplexers 23 and 24. Is connected to the select terminal of and the / EN terminals of the first and second latch portions 25 and 26.

In addition, the output dat of the buffer 13 is connected to the first and second multiplexers 23 and 24 and the first and second latch portions 25 and 26, respectively, and the first multiplexer ( The output Idata1 of 23 is connected to the third latch unit 27, and the output Idata2 of the second multiplexer 24 is connected to the fourth latch unit 28.

The outputs of the first and second latch units 25 and 26 are input to the first and second multiplexers 23 and 24.

The operation of the failsafe circuit of the digital output board configured as described above is as follows.

It is determined whether or not the upper address generated by the CPU (not shown) matches the address preset in the comparator 11, and if it matches according to the determination result, an output signal (/ mybd) is generated to enable the decoder 12. Let's do it.

When the output signal / mybd is generated, the output cp1 is generated high by the decoder 12 and the output cpa of the signal detector 22 becomes low, thereby providing the first or gate. 21a outputs cp1.

At this time, the signal dat input from the buffer 13 is input to the second multiplexer 23, and outputs Idata1 because the output emg signal of the signal detector 22 is high.

Therefore, if a failure occurs, the output signal / mybd of the comparator 11 is not generated, and thus the decoder 12 and the buffer 13 are not enabled. In addition, since there is no input of the signal detector 22, the output signal emg goes low and the output signal cpa goes high.

Since the output emg is LOW, the first and second latches 25 and 26 are enabled and set in advance to output high data. At this time, the first and second multiplexers 23 and 24 0 data is output by the output signal emg.

Further, another output signal cpa of the signal detection unit 22 goes high and is output to the first and second ore gates 21a and 21b so that the third and fourth latch units 27 ( It is input with the clock pulse of 28).

The time constant of the signal detector 22 is set by adjusting the resistor R1 and the capacitor C1 between about three and five times the time periodically accessed by the CPU (not shown).

The digital output board according to the present invention can detect the output signal of the comparator and determine the failure of the CPU or the interface circuit to prevent the safety accident in advance and increase the effect of the production process of the product.

Claims (2)

A digital output board having a comparator, a decoder and a buffer, A signal detector for detecting an output signal (/ mybd) of the comparator; First and second OR gates for ORing the signals decoded by the decoder; First and second latch units receiving and latching data output from the buffer and decoder; First and second multiplexers configured to receive and multiplex data output from the buffer and data output from the first and second latch units; And a third and fourth latch unit configured to receive data output by performing an OR operation on the first and second or gates and to output data multiplexed and output from the first and second multiplexers to the field. Failure safety circuit of a digital output board, characterized in that. The method of claim 1, The output signal cpa of the signal detector is input to the first and second or gates, and the output signal emg is input to the first and second multiplexers and the first and second latch units. Fault safety circuit.