KR930007474B1 - D-bus address detecting circuit in electronic exchanges - Google Patents

Abstract

The invention detects the obstruction node and its exact address when there is a obstruction in data signals and control signals. The circuit comprises D-BUS sensing section (16) for detecting an error signal on D-bus and operating an obstructing signal, ASTCLK control section (17) for generating clock signal (ASTCLK1) using a control clock (ASTCCK) and a bus control signal (AST*), counter section (18) for decreasing initial values by clock signal (ASTCLK1) and data latch section (19) for latching a data of counter output by obstruction signal.

Description

D-bus fault node address detection circuit of electronic switch

1 is a diagram of a communication network connection between processors in an electronic switchboard.

2 is a block diagram of a D-bus monitoring and control block to which the present invention is applied.

3 is a block diagram of a D-bus fault and node address sensing circuit in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

1: D-bus monitoring and control unit 2: D-bus

3: U-link 4: D-bus signal line

6: D-bus fault detection and faulty node address detector

7: D-bus border 8: D-bus utilization measuring circuit

9: alarm monitoring circuit 10: main control

11: address decoder 12: alarm signal

13 data line 14 address line

15: control signal 16: D-bus fault detection circuit

17: ASTCLK control unit 18: counter

19: data latch unit

The present invention provides a D-bus for detecting an address of a corresponding node when a tripled control signal and a data signal fail on a D-bus, which is a common serial bus of nodes providing communication paths between internal processors of an electronic switching system. It is a faulty node address sensing circuit.

Each unit network constituting the interprocessor intercommunication network of the electronic switch is composed of a maximum of 32 nodes, and each node is given a unique address value. Each node in the unit network transmits a message using a D-bus, which is a serial common bus of nodes, when a message received from a corresponding processor is transmitted to another processor.

At this time, the nodes are granted the D-bus license by round robin using the abitation method to the address of each node.

Accordingly, an object of the present invention is to provide a D-bus fault node address detection circuit for determining an exact address of a node when a fault node is detected on a bus in a D-bus monitoring and control apparatus in each unit network (hereinafter referred to as IPCU). The purpose is.

In order to achieve the above object, the present invention provides a method for detecting an address of a corresponding node in the event of a failure of a tripled control signal and data signal on a D-bus, which is a serial bus of nodes providing an interprocessor communication path. In the D-bus fault node address detection circuit of an electronic switch, D-bus fault detection detects when there is a malfunction signal among triplexed signals connected to the D-bus and drives a fault signal. Means, an ASTCLK control means for generating a clock signal ASTCLK1 using a bus occupancy control clock ASTMC and a bus control signal AST *; A counter means for reducing an initial value by a clock signal ASTCLK1 of a control means, and the D-bus fault detection means connected to the D-bus fault detection means and the counter means. To the failure signal generation stand consists of a data latch means for latching the data value output from the counter means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a connection diagram of an interprocessor communication network in an electronic switching system.

Block A represents any one IPCU, (1) represents a D-bus monitoring and control block present in each IPCU, and (2) represents a D-bus, a serial bus commonly used by nodes in an INPU. (3) shows a physical link (hereinafter referred to as U-link) connected between a node and a processor or a GW (GateWay).

Block B in block A represents the nodes connected to the D-bus 2, up to 32 possible. Block C in block A indicates each processor that is connected to the node and the U-link (3) and is the subject of communication. If the receiving processor of the data on the D-bus 2 is in block C, the message is received via that node, otherwise it is passed to the other IPCU via the GW (GateWay) node. And block D represents any other IPCU connected in GW with one IPCU in block A.

2 is a block diagram of the D-bus monitoring and control block of FIG. 1 to which the present invention is applied.

(2) represents the D-bus, ASTCLK (a, b, c), which is the clock that controls bus occupancy, FRS * (a, b, c), which controls bus occupancy, and AST * (a, b, which indicates bus occupancy , c), BRCLK (a, b, c), which is a data synchronization clock, and DATA (a, b, c), which are data on a bus, are tripled.

(7) is a D-bus signal bot that extracts two identical signals for each signal of the D-bus 2 that is tripled, and (4) is a voted D-bus signal line Indicates. (6) detects this phenomenon and detects the address of the corresponding node when an error occurs in one signal line for each signal of a, b, c of the triplexed D-bus, and detects the node address. It is a sensing unit. (8) is a bus utilization measuring circuit that has a function of measuring the bus utilization used within a certain time while monitoring the occupancy status of the D-bus in the IPCU.

(9) has a function of collecting alarm signals 12 from each node of block B of FIG. 1 as an alarm monitoring circuit. Denoted at 10 is a main controller and 11 is an address decoder. Reference numeral 13 denotes a data line commonly connected to each functional block, and reference numeral 14 denotes a control signal for reading a data value of each functional block.

3 is a block diagram of a D-bus fault node address detecting circuit according to the present invention, 16 is a D-bus fault detecting circuit, 17 is an ASTCLK control unit, 18 is a counter, and 19 is a data latch unit.

In the figure, the D-bus fault detection circuit shown by (16) shows the tripled DATA (a, b, c), BRCLK (a, which is carried on the bus when any one node sends a message on the D-bus. b, c), AST * (a, b, c) This circuit monitors the state of the signal and is implemented as PAL (Programmable Array Logic). Among the above-mentioned arbitrary D-bus signals, the result of each state of the tripled a, b, and c is shown in Table 1 below.

TABLE 1

N in the result column indicates a normal state because the tripled a, b, and c signals have the same state, and E indicates an abnormal state because one of the three signals a, b, and c exists. As shown in Table 1, Clauses 1 and 8 are steady, Clauses 2 and 7 indicate signal c, Clauses 3 and 6 indicate signal b, and Clauses 4 and 5 indicate that signal a is wrong.

On the other hand, the a, b, c signals of each bus signal input from the D-bus to the D-bus fault detection circuit 16 may vary by several nsec (nanoseconds) depending on the characteristics of the output device. The sampling clock is used for the voted BRCLK signal 23 for DATA (a, b, c) and BRCLK (a, b, c) and the ASTCLK of (21) voted for AST * (a, b, c), respectively. did.

The ASTCLK control unit 17 is a circuit for generating the ASTCLK1 signal 25 by inputting the botted ASTCLK signal 21 and the AST * signal 22, and implemented as a programmable array logic (PAL). Output ASTCLK1 signal 25 is generated in the same form as the input ASTCLK signal 21 only when () is in a valid state, and the output signal 25 is high when the AST * signal 22 is not valid (high). Maintain state.

The counter 18 is a cascaded connection of two binary up / down counters and operates in down counter mode. When the valid state (low) of the FRS * signal 24 is input from the D-busbot 7, the initial value 26 is loaded into the counter and the value appears in the data line 27. At this time, the initial value is the largest value among the address values of nodes in one IPCU.

When the ASTCLK1 clock 25 is input to the counter 18, the values decremented by one from the initial value appear on the data line 27. If any node is communicating by occupying the D-bus 2, the ASTCLK1 clock 25 is stopped and the data value shown on the data line 27 refers to the address value of the node with which it is communicating. At this time, when the D-bus fault detecting circuit 16 generates a signal informing of a fault, the data latch unit 19 using the latch element latches the values indicated on the data line 27.

The main controller 10 outputs a corresponding address in order to read the values latched in the data latch unit 19, and the address decoder 11 generates an RD * signal 28 to convert the data value of the data line 13; Read

Claims (4)

D-bus of an electronic switch to detect the address of the corresponding node in the event of a failure of the tripled control and data signals on the D-bus (2), a serial bus of nodes that provide communication paths between internal processors A faulty node address sensing circuit, comprising: D-bus fault detection means 16 connected to the D-bus (2) to detect when there is a malfunction signal among the triplexed signals on the D-bus (2) to drive the fault signal 20, An ASTCLK control means 17 for generating a clock signal ASTCLK1 using a bus occupancy control clock ASTMC and a bus control signal AST *, and an ASTCLK control means 17 connected to the bus occupancy control signal FRS *. And the counter means 18 for reducing the initial value by the clock signal ASTCLK1 of the ASTCLK control means 17, and the D-bus fault detection means 16 and the counter means 18, respectively. D-bus fault node address detection circuit, characterized in that it comprises a data latch means (19) for latching the data value output from the counter means (18) with a fault signal generated by the bus fault detection means (16). 2. A D-bus fault node address detection circuit as claimed in claim 1, wherein said D-bus fault detection means (16) comprises a Programmable Array Logic (PAL). 2. The D-bus fault node address sensing circuit according to claim 1, wherein the counter means (18) operates in down counter mode with two binary up / down counters configured in cascade connection. The D-bus fault node address sensing circuit of claim 1, wherein the initial value is the largest value among the address values of each node.