KR100279930B1 - Method and apparatus for standby path test in interprocessor communication - Google Patents

Abstract

The present invention relates to a standby path test method and apparatus in interprocessor communication.

In the conventional interprocessor communication system, since the device for testing the standby path is not provided, it is impossible to check whether the standby path is normal, so that the smooth communication can be ensured when the man machine subsystem and the main processor are redundantly switched. There is a problem that can not be.

The present invention can test the standby path in advance in a system in which the communication path used for inter-processor communication is duplicated, thereby ensuring smooth communication when the man machine subsystem and the main processor are redundantly switched.

Description

Method and apparatus for standby path test in interprocessor communication

The present invention relates to inter-processor communication between processors in an exchange, and particularly, a standby path test method in inter-processor communication that enables a standby path to be tested in a system in which communication paths between processors are duplicated. Relates to a device.

In general, a large-scale system such as an exchanger includes a plurality of processors inside and operates to exchange data between corresponding processors to perform system-specific functions. In order to guarantee operation continuity, redundant communication paths between processors are provided. It is operated.

As an example of the inter-processor communication system in which the communication paths are duplicated as described above, the switchboard includes the man machine subsystems MMS1 and 2, the link boards SLNC1 and 2, and the link boards TLNC1 and 2, as shown in FIG. And an interprocessor communication system composed of main processors MP1 and 2. The man machine system MMS1 is connected to the linkboard SLNC1 via path A and at the same time connected to the linkboard SLNC2 via path B, and the man machine system MMS2 is connected to the link board SLNC1 through path C. ) Is connected to the link board SLNC2 via the path D. In addition, the main processor MP1 is connected to the link board TLNC1 through the path A and is connected to the link board TLNC2 through the path C, and the main processor MP2 is connected to the link board TLNC1 through the path B. ) Is connected to the link board (TLNC2) via the path D. In addition, the link boards SLNC1 and 2 are located in the space switch / link block, and the link boards TLNC1 and 2 are located in the time switch / link block, and the link boards SLNC1 and 2 and the link boards TLNC1 and 2 are located. Is connected one-to-one via an optical link to transfer data transmitted and received between two processors, a man machine subsystem (MMS1, 2) and a main processor (MP1, 2), and a man machine subsystem (MMS1, 2). ) And the link board (SLNC1, 2) is connected via cable to transfer data, and the path between main processor (MP1, 2) and link board (TLNC1, 2) is connected via cable to transfer data. do.

In the above-described interprocessor communication system, the man machine subsystems MMS1 and 2 and the main processors MP1 and 2, which serve as processors for processing predetermined data, are redundant, one operating in an active state and the other If the failure occurs while the active side is operating normally, the standby state is changed to the standby state and the standby side is switched to the active state to continue operation.

For example, assuming that the man machine subsystem MMS1 is active among the man machine subsystems MMS1 and 2 and the man machine subsystem MMS2 is in a standby state, and among the main processors MP1 and 2, the main processor ( Assuming that MP1) is active and the main processor MP2 is in a standby state, the linkboard SLNC1 transmits and receives data to and from the man machine subsystem MMS1 side via path A, and communication through path C is in a standby state. The linkboard SLNC2 transmits and receives data to and from the man machine subsystem MMS1 via path B, and communication through path D is in a standby state. In addition, the link board TLNC1 transmits and receives data to and from the main processor MP1 side via the path A, and the communication through the path B is in a standby state, and the link board TLNC2 is connected to the main processor MP1 through the path C. Send and receive data and communication over path D is in standby.

When the man machine subsystem (MMS1) in the active state has failed and the man machine subsystem (MMS2) is redundantly switched to communicate with the active state, the man machine subsystem (MMS2) is in the standby state. When the main processor MP1 in the active state has failed and the main processor MP2 is redundantly switched to the active state to communicate with the main processor MP2, the main processor MP2 disconnects the paths B and D in the standby state. Communicate via

However, in the conventional inter-processor communication system as described above, since the apparatus for testing the standby path is not provided, it is impossible to check whether the standby path is normal, so that the duplication transfer of the man machine subsystem and the main processor is performed. There is a problem in that smooth communication cannot be guaranteed.

The present invention has been made to solve the above problems, and provides a standby path test method and apparatus for inter-processor communication in the standby path test in a system in which the communication path used for inter-processor communication is duplicated There is a purpose.

1 illustrates a redundant path in conventional interprocessor communication.

Figure 2 illustrates a standby path test scheme in interprocessor communication in accordance with the present invention.

3 and 4 show a configuration for looping data in the linkboard shown in FIG.

Fig. 5 is a diagram showing the configuration of the looping control circuit shown in Figs. 3 and 4;

6 is an operation timing diagram of the looping control circuit.

Explanation of symbols on the main parts of the drawings

MMS1, 2: Man Machine Subsystem SLNC1, 2: Link Board

TLNC1, 2: link board MP1, 2: main processor

A feature of the present invention for achieving the above object is, in the inter-processor communication to communicate by connecting the communication group that duplicated the path between the redundant processor means and the redundant link board by an optical link, the link board is a processor Looping the data transfer path to the processor means side according to a clock applied from the means to return the transmission data from the processor means to the processor means side; And determining, by the processor means, whether the standby path is normal by checking whether the data transmitted by the processor means and the data looped back from the link board are the same.

In another aspect of the present invention, in the inter-processor communication in which a communication group that duplicates the path between the redundant processor means and the redundant link board is connected by optical link, the link board is a clock applied from the processor means. Looping control means for outputting a control signal when the frequency of the signal is changed, and looping means for looping back the data transmitted from the processor means to the processor means according to a control signal applied from the looping control means. It is.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The interprocessor communication system according to the present invention is shown in FIG. 2 as man machine subsystems MMS1 and 2, linkboards SLNC1 and 2, linkboards TLNC1 and 2 and main processor MP1 and 2, respectively. Although the operation of the communication path and the communication path for transmitting and receiving data is the same as the conventional interprocessor communication system, a description thereof will be omitted. The present invention is a path provided between the man machine subsystem (MMS1, 2) and the link board (SLNC1, 2), and the path provided between the link board (TLNC1, 2) and the main processor (MP1, 2) And a standby path between the man machine subsystems MMS1 and 2 and the linkboards SLNC1 and 2, and the linkboards TLNC1 and 2 and the main processor MP1 and 2, respectively. When testing the standby path between the loops, the linkboard SLNC1, 2 loops the data transfer path to the man machine subsystem MMS1, 2 according to the clock applied from the man machine subsystem MMS1, 2). (Looping) and sending the transmission data back to the man machine subsystem (MMS1, 2) side, so that the man machine subsystem (MMS1, 2) checks whether the data sent by it is looped back and the same data is returned. Test for normality, The link board TLNC1, 2 loops the data transfer path to the main processor MP1 and 2 according to the clock applied from the main processor MP1 and 2, and sends the transmission data back to the main processor MP1 and 2 side. The main processor (MP1, 2) tests the normality of the standby path by checking whether the data sent by it and the looped back data are the same.

In FIG. 2, it is assumed that the man machine subsystem MMS1 is active and the man machine subsystem MMS2 is in the standby state among the man machine subsystems MMS1 and 2, and the main processor (M1) among the main processors MP1 and 2 is shown in FIG. For example, assuming that MP1 is active and the main processor MP2 is in a standby state, the link board SLNC1 transmits and receives data to and from the machine subsystem MMS1 via path A and transmits path C. The communication via is in a standby state, the linkboard SLNC2 transmits and receives data with the man machine subsystem MMS1 side via path B, and the communication via the path D is in a standby state. In addition, the link board TLNC1 transmits and receives data to and from the main processor MP1 side via the path A, and the communication through the path B is in a standby state, and the link board TLNC2 is connected to the main processor MP1 through the path C. Send and receive data and communication via path D is in a standby state.

In this state, when the standby state machine subsystem (MMS2) wants to test the standby paths C and D, it links the 4.092 MHz clock that is different from the 8.192 MHz clock that the man machine subsystem (MMS2) normally outputs. When outputting to the board (SLNC1, 2) side, the link board (SLNC1, 2) receiving the corresponding 4.096 MHz clock loops the data passing through the paths C and D, and the man machine subsystem (MMS2) sends the path C by itself. In this case, it is determined whether the standby paths C and D are normal by checking whether the data transmitted through D and the looped data are identical. If the corresponding data is the same, the standby paths C and D are determined to be normal, If not the same, standby paths C and D are determined to be abnormal. In addition, when the main processor MP2 in the standby state wants to test the standby paths B and D, the link board (TLNC1, 2) has a 4.096 MHz clock different from the 8.192 MHz clock that the main processor MP2 normally outputs. Output to the loop, the linkboard (TLNC1, 2) receiving the corresponding 4.096 MHz clock loops the data transmitted through paths B and D, and the main processor (MP2) loops with the data transmitted through paths B and D by itself. If the data is the same, the standby paths B and D are judged to be normal. If the corresponding data is the same, the standby paths B and D are determined to be normal. It is determined to be abnormal. In addition, if necessary, the man machine subsystem MMS1 may test the path B, and the main processor MP1 may test the path C.

The configuration for each linkboard SLNC1, 2 to loop the data in the standby path is made as shown in FIG. That is, each of the link boards SLNC1 and 2 includes a multiplexer MUX and a looping control circuit RC. In the looping control circuit RC, a clock applied from the standby state machine subsystem MMS is 8.192. When it is changed from MHz to 4.096 MHz and applied, the predetermined control signal ALM is output to the control terminal S side of the multiplexer MUX. In addition, the multiplexer (MUX) has an input terminal A connected to a data transmission path of a man machine subsystem (MMS) in a standby state, an input terminal B connected to an adjacent link board (TLNC) data transmission path, and an output terminal. (C) is connected to the data receiving path of the man machine subsystem MMS in the standby state, and when the predetermined control signal ALM is input from the looping control circuit RC to the control input terminal S, the input terminal A, By selecting the input terminal A from B), the data transmitted from the standby man machine subsystem MMS is applied and looped back through the output terminal C to the standby man machine subsystem MMS.

Then, each link board TLNC1, 2 is configured to loop data of the standby path as shown in FIG. That is, each of the link boards TLNC1 and 2 includes a multiplexer MUX and a looping control circuit RC. The looping control circuit RC has a clock applied from the main processor MP in a standby state to 8.192 MHz. When the control signal is changed to 4.096 MHz, the control signal ALM is output to the control terminal S side of the multiplexer MUX. In addition, the multiplexer MUX has an input terminal A connected to the main processor MP side data transmission path in a standby state, an input terminal B connected to an adjacent link board SLNC side data transmission path, and an output terminal C. ) Is connected to the main processor MP side data receiving path in the standby state, and when a predetermined control signal ALM is input from the looping control circuit RC to the control input terminal S, the input terminal among the input terminals A and B is input. By selecting (A), the data transmitted and applied from the standby main processor MP is looped back through the output terminal C to the standby main processor MP side.

On the other hand, the looping control circuit RC for controlling the operation of the multiplexer MUX provided in each of the link boards SLNC1 and 2 and TLNC1 and 2 has a plurality of de- flip-flops DF1 as shown in FIG. DF4), a plurality of exclusive OR gates XO1 to XO10, a OR gate OG, and a plurality of inverters I1 and I2. The de-flop DF1 receives the output from its output stage Q to the data input terminal D through the inverter I1 and is used in the link boards SLNC1, 2 and TLNC1, 2 itself. A 16 MHz clock CLK1 (see Fig. 6 (1)) is applied to the clock input terminal to operate, and an 8 MHz clock CLK3 (Fig. 6) is provided to the clock terminal CLK side of the de-flip flop DF2 through the output terminal Q. (See (3)). The de-flip flop DF2 receives a clock CLK2 (see (2) in FIG. 6) applied from the man machine subsystem (MMS) or the main processor (MP) in standby state at 8.192 MHz or 4.098 MHz. The signals A to E received from the first to fifth output terminals Q1 to Q5, respectively, are input to the D1 and are individually input to the second to sixth data input terminals D2 to D6. The 8MHz clock CLK3 from the flop DF1 is inputted to the clock stage CLK to operate, and the signals A to F are provided through the first to sixth output terminals Q1 to Q6; (See (10)). In addition, the de-flip-flop DF3 receives a clock CLK2 (refer to (2) in FIG. 6) applied from the man machine subsystem MMS or the main processor MP in the standby state at 8.192 MHz or 4.098 MHz. Input to the data input terminal D1, and receive signals G to K separately from the first to fifth output terminals Q1 to Q5 thereof, respectively, to the second to sixth data input terminals D2 to D6; The inverted 8 MHz clock (/ CLK3; see FIG. 6 (4)) applied from the de-flop DF1 through the inverter I2 is input to the clock terminal CLK to operate the first to sixth output terminals. Signals G to L (see (11) to (16) in Fig. 6) are output through Q1 to Q6.

The exclusive OR gates XO1 to XO5 receive the signals A to F applied from the de-flip-flop DF2 to perform an exclusive OR operation, but exclusively perform two adjacent signals among the signals A to F. The OR is output to the OR gate (OG) and the exclusive OR gates XO6 to XO10 are subjected to an exclusive OR operation by receiving the signals G to L applied from the de-flip flop DF3. The two adjacent signals in L) are exclusively ORed and output to the OR gate OG side. That is, the exclusive OR gate XO1 exclusively ORs the signals A and B applied from the de flip-flop DF2 and outputs the result to the OR gate OG, and the exclusive OR gate XO2 is deflipped. The signals B and C applied from the flop DF2 are exclusively ORed and output to the OR gate OG side, and the exclusive OR gate XO3 is the signal C applied from the de flip-flop DF2. ) And (D) are exclusively ORed and output to the OR gate (OG) side, and the exclusive OR gate XO4 exclusively ORs the signals D and E applied from the de-flip-flop DF2. Output to the (OG) side, the exclusive OR gate XO5 performs exclusive OR on the signals E and F applied from the de-flip-flop DF2 and outputs to the OR gate OG side. (XO6) performs an exclusive OR on the signals (G) and (H) applied from the de flip-flop (DF3). It outputs to the sum gate OG side, and the exclusive OR gate XO7 performs exclusive OR on the signals H and I applied from the de-flip-flop DF3 and outputs to the OR gate OG side. The OR gate XO8 exclusively ORs the signals I and J applied from the de-flip flop DF3 and outputs the result to the OR gate OG. The exclusive OR gate XO9 is a de flip-flop DF3. The exclusive logic sum of the signals (J) and (K) applied from) is output to the OR gate (OG), and the exclusive OR gate (XO10) is the signal (K), (applied from the de-flip flop (DF3). L) is exclusively ORed and output to the OR gate OG side.

In addition, the OR gate OG performs an OR on the signals applied from the exclusive OR gates XO1 to XO10 and outputs the data to the data input terminal D of the de-flip flop DF4. The flip-flop DF4 receives a signal applied from the OR gate OG to the data input terminal D, and receives the 16 MHz clock CLK1 used by the link boards SLNC1 and 2 and the TLNC1 and 2 itself. It is applied to the clock input terminal and is operated, and outputs a control signal ALM (see (17) in FIG. 6) to the multiplexer MUX side through the output terminal Q to control the data looping operation in the multiplexer MUX.

The standby path test operation in the present invention configured as described above is performed as follows.

First, when the standby state machine subsystem MMS2 intends to test the standby paths C and D, the 8.192 MHz clock CLK2 normally output by the man machine subsystem MMS2 is the interval T1 of FIG. 6. When it is changed to 4.096 MHz and outputted to the link boards SLNC1 and 2, the looping control circuit RC of the link boards SLNC1 and 2 operates as described above, as shown in the section T2 of FIG. Outputs the high level control signal ALM to the multiplexer (MUX), loops the data transmitted through the paths C and D by the multiplexer (MUX), and sends it back to the standby state machine subsystem (MMS2). The man machine subsystem (MMS2) determines whether or not the standby paths C and D are normal by checking whether the data transmitted through the paths C and D and the looped data are identical by the same. Normal standby paths C and D If the data are not the same, the standby paths C and D are determined to be abnormal.

In addition, when the main processor MP2 in the standby state wants to test the standby paths B and D, the main processor MP2 normally outputs an 8.192 MHz clock CLK2 as shown in the section T1 of FIG. When the signal is changed to MHz and output to the link boards TLNC1 and 2, the looping control circuit RC of the link boards TLNC1 and 2 operates as described above to control the high level as in the section T2 of FIG. Outputs the signal ALM to the multiplexer MUX, loops the data transferred through the paths B and D by the multiplexer MUX, and sends the signal AM back to the standby main processor MP2 side. Determines whether the standby paths B and D are normal by checking whether the data transmitted through the paths B and D and the looped data are identical. If the corresponding data is the same, the standby paths B and D are normal. Judging, If the differences are not the same, the standby paths B and D are determined to be abnormal.

As described above, the present invention can test the standby path in advance in a system in which the communication path used for inter-processor communication is duplicated, so that smooth communication can be ensured when the man machine subsystem and the main processor are redundantly switched. do.

Claims (8)

In an interprocessor communication in which a communication group in which a duplicated path between a duplicated processor means and a duplicated link board is duplicated through an optical link is communicated, the link board is connected to the processor means according to a clock applied from the processor means. Looping a transmission path to return transmission data from said processor means to said processor means; And determining, by the processor unit, whether the standby path is normal by checking whether the data transmitted by the processor means and the data looped back from the link board are the same. Testing method. 2. The inter-processor communication of claim 1, wherein the linkboard loops a data transfer path to the processor means when a clock applied from the processor means is changed from a first frequency to a second frequency. How to test standby path. In an interprocessor communication in which a communication group in which a duplicated path between a duplicated processor means and a duplicated link board is duplicated through an optical link is communicated, the link board controls a control signal when a frequency of a clock applied from the processor means is changed. And looping control means for outputting a looping means, and looping means for looping back the data transmitted from the processor means to the processor means according to a control signal applied from the looping control means. Standby path test device in communication. 4. The method of claim 3, wherein the looping control means comprises: a signal generating means for generating a plurality of signals by sensing a clock applied from the processor means, and performing a logical operation on the plurality of signals applied from the signal generating means. And a logic operation means for outputting a control signal to said looping means side. The method of claim 4, wherein the signal generating means receives an output signal from its output terminal to a data input terminal through an inverter and operates by receiving a clock of a first frequency used in the link board itself to a clock input terminal. First flip-flop means for outputting a clock of a second frequency through an output terminal; A clock that varies from a third frequency applied by the processor means to a fourth frequency is input to the first data input terminal, and the first to fifth signals output from its first to fifth output terminals are second to fifth. Independently input to the sixth data input terminal, the clock of the second frequency applied from the first flip-flop means is operated to the clock terminal, and outputs the first to sixth signal through the first to sixth output terminal Second flip-flop means; A clock that varies from a third frequency applied by the processor means to a fourth frequency is input to the first data input terminal, and the seventh to eleventh signals output from the first to fifth output terminals thereof are second to fifth. Independently input to the sixth data input terminal, the clock of the inverted second frequency applied from the first flip-flop means through the inverter to the clock terminal to operate, the seventh to sixth through the first to sixth output terminal And a third flip-flop means for outputting a 12 signal. 5. The apparatus according to claim 4, wherein said logical operation means comprises: first exclusive logical sum means for receiving exclusive first OR sixth signals applied from said signal generating means; Second exclusive logical sum means for receiving the seventh to twelfth signals applied from the signal generating means and performing an exclusive OR; An AND operation means for ORing the signals applied from the first and second exclusive OR means; Receiving a signal applied from the logical sum means to the data input terminal, and operates by receiving a clock of the first frequency used in the link board itself to the clock input terminal, and outputs a control signal to the looping means side through the output terminal A standby path test apparatus in interprocessor communication, comprising: flip-flop means. 7. The apparatus of claim 6, wherein the first exclusive OR means comprises: a first exclusive OR gate for exclusive OR of the first and second signals and outputting the exclusive OR; A second exclusive OR gate for exclusive ORing the second and third signals and outputting the exclusive OR; A third exclusive OR gate for performing an exclusive OR on the third and fourth signals and outputting the exclusive OR; A fourth exclusive OR gate for performing exclusive OR on the fourth and fifth signals and outputting the fourth OR fifth signal to the OR unit; And a fifth exclusive AND gate for exclusively ORing the fifth and sixth signals to the OR unit. 7. The apparatus of claim 6, wherein the second exclusive OR means comprises: a first exclusive OR gate for exclusive OR of the seventh and eighth signals and outputting the seventh and eighth signals to the OR; A second exclusive OR gate for performing an exclusive OR on the eighth and ninth signals and outputting the exclusive OR; A third exclusive OR gate for performing an exclusive OR on the ninth and tenth signals and outputting the exclusive OR; A fourth exclusive OR gate for performing exclusive OR on the tenth and eleventh signals and outputting the exclusive OR to the logical sum means; And a fifth exclusive OR gate for exclusively ORing the eleventh and twelfth signals and outputting the exclusive OR to the logical sum means.