SU1410036A2 - Device for inspecting logical units - Google Patents

Abstract

The invention relates to automation and computing and can be used to monitor the health of logic blocks and digital circuits. The purpose of the invention is to increase the reliability of the control. The invention allows monitoring and localization of constant and non-constant faults, as in

Description

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Zonation, as well as in successive circuits, including short-circuit type faults, with | feedback loops with and with an odd number of inversions and short-circuiting occurrence in the short-wavelength sustainable generation. This is achieved by the fact that after completion of the switching of the logical elements of the tested node 3, the device provides for the analysis of the presence of

10036

In the case of its stable generation, in the case of its occurrence in inductive sensor 28, a signal appears that through differentiating node 21, the first 22 and second 23 amplifiers are fed to the inputs of the OR 2A element and starts the pulse shaper 29. The signal from the output of the former 29 through the memory element 26 turns on the indicator 27j fixing the presence of a fault in the circuit. 2 or „

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The invention relates to automation and computing and can be used to monitor the health of logic blocks and digital circuits and is additional to the main ZET. St. No. 1020829.

The purpose of the invention is to increase the reliability of the control. I Figure 1 presents a diagram of the proposed device; Fig. 2 illustrates an example of the implementation of a matching unit and an inductive sensor.

I The device contains a pulse generator 1, a counter 2, a tested node 3, a standard storage unit 4, a comparison element 5, a memory element 6, an indicator 7, an input fixation block 8, a control block 9 containing a switch 10, a trigger driver 11 switch. 12 In addition, the device b contains an AND 13 element, a switch 14, a switching registration unit 15, an AND-16 element, an indicator 17, a pulse shaper 18, an OR 19 element, a delay element 20, an electrical matching unit consisting of a differential node 21 first amplifier 22 and second amplifier 22, element OR 24, element 25, memory element 26, indicator 27 inductive sensor 28, second photo () worldviewer 29 pulses, transistors 30 and 31, resistor 32, capacitor 33, resistors 34 and 35.

The device operates according to the principle of comparing the input and output signals of two identical blocks — the checked node 3 and the block 4 storage stages.

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new The device has two modes of operation. The first corresponds to the control nodes, the second - the control chips installed on printed circuit boards.

The device works as follows (see figure 1).

Initially, all memory elements 6, blocks 8, 15 and element 26 are set to the zero state. The switch 10 starts the start-up shaper 11, opening the input latching blocks 8, which determine the outputs of the standard storage unit 4, corresponding to the unit inputs, switch switching registration units 15, corresponding to the inputs of the standard storage unit 4, set them to the zero state, turn off the registration units 15 switchings, corresponding to the outputs of the storage unit 4 of the standards, set them to a single state, and also, depending on the operation mode, they either start transmitting test signals from the counter 2 hours By means of elements 13 and 13 on the inputs of the tested node 3 and the standard storage unit 4, or in the second mode, the switches 14 are opened, which ensures the transmission of signals from the inputs of the tested node to the inputs of the standard storage unit 4. The switched-on switching registration units 15 through the NAND-16 element keep the memory elements 6 and 26 in their initial state. After all the inputs of the standard storage unit 4 are switched, i.e. Signals will be applied to all possible installation inputs. Check 1410036

of the node 3 and the standard storage unit 4, all switching registration units 15 are turned off, removing the prohibition on the inclusion of memory elements by signals from the output of the comparison elements 5. At the same time, the low-level signal from the output of the NAND 16 element turns on the indicator 17 and starts the pulse shaper 18. Comparison elements 5 in both modes compare signals on signals from blocks 3 and 4 and, if they do not match, output signals to the corresponding memory element 6, which in this case is set to the state corresponding to the indicator 7, the signal from the output of the driver 18 pulses through delay element 20 with time

is amplified by the differential stage and from resistors 34 and 35 is fed to amplifier 22, where it is amplified to a level sufficient to trigger an element OR 24. Thus, if a stable generation caused by a fault with a feedback short circuit occurred in the test node the output of the driver 29 by Wits high logic level signal. This signal is preserved even after completion of switching the logical elements of the storage unit of 15 standards, t, e, and after the delay of the time produced by the delay element 20 has expired. If in the test node the generation is not stable

after the switching of the switching delay, the required delay for the logic elements of blocks 3 and 4 on the switching points of the logical element of the forg shrovetel 29 output, and the following

the scanned node, sets the counter 2 to the initial state and, arriving at the input of the element 25, allows writing to the memory element 26 of the determination results in the test node of the generation. If a source of generation occurs anywhere in the test node (see

of course, and at the output of the element And 25, there will be a potential of a low logic level. TaKtM, 25, when it was received} w to the second input of the element I 25 from the input of the element 20 of the delay of the signal for recording the recording of the determination of the presence of generation on the information input of the element

2) in the inductive sensor 28, of the memory stick 26, a signal of the appropriate level will be received. In the event of a stable generation, a memory element 26 includes an indicator 27.

Claims (1)

Invention Formula The second is an antenna made in the form of a printed inductance, designed for the maximum switching frequency, logic elements and located with a minimum clearance from the tested node, a signal appears that has a capacitive and inductive component. The potential change will be transmitted through the capacitance formed by the printed conductors of the test node and the antenna to the node 21. The potential induced by the capacitive component enters in phase at both inputs of the node 21, which is, for example, a differential cascade made on transistors 30 and 31. The output of the cascade is a resistor 32, from which the potential through the capacitor 33 enters the input of the amplifier 23, where it is amplified to the level required for the operation of the element OR 24 The inductive signal component appears c due to the mutual induction of printed conductors of the test node and antenna. It is expressed in the appearance of a potential difference at the ends of the antenna at the time of a change in current in the generation center. This potential difference 35 Device for controlling logical nodes on the author. St. K-1020829, characterized in that, in order to increase the reliability of the control, an inductive sensor, an electrical matching unit, an element 1 SHI, a second pulse shaper, an element AND, a memory element, 45 indicator and a delay element, the output of the first pulse liner through the delay element is connected to the installation input of the counter and the first input of the AND element, the output of which is connected to the information input of the memory element, the control input of which is connected to the output of the NAND element, and the output - with the input of the indicator, the second input element And through the second 55 a pulse shaper is connected to the output of an OR element, the inputs of which are connected to the outputs of an inductive sensor through an electrical matching unit. is amplified by the differential stage and from resistors 34 and 35 is fed to amplifier 22, where it is amplified to a level sufficient to trigger an element OR 24. Thus, if a stable generation caused by a fault with a feedback short circuit occurred in the test node the output of the driver 29 by Wits high logic level signal. This signal is preserved even after the switching of the logical elements of the storage unit of the standards, t, e ", and after the delay of the time produced by the delay element 20 has passed. If the test node is stable generation is not voznnk and of course, and at the output of the element And 25, there will be a potential of a low logic level. TaKtM, 25, when it was received} w to the second input of the element I 25 from the input of the element 20 of the delay of the signal for recording the recording of the determination of the presence of generation on the information input of the element Invention Formula 35 Device for controlling logical nodes on the author. St. K-1020829, characterized in that, in order to increase the reliability of the control, an inductive sensor, an electrical matching unit, an element 1 SHI, a second pulse shaper, an element AND, a memory element, 45 indicator and a delay element, the output of the first pulse liner through the delay element is connected to the installation input of the counter and the first input of the AND element, the output of which is connected to the information input of the memory element, the control input of which is connected to the output of the NAND element, and the output - with the input of the indicator, the second input element And through the second 55 a pulse shaper is connected to the output of an OR element, the inputs of which are connected to the outputs of an inductive sensor through an electrical matching unit. fa $ .2