KR19990061009A - Via contact formation method of semiconductor device - Google Patents
Via contact formation method of semiconductor device Download PDFInfo
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- KR19990061009A KR19990061009A KR1019970081263A KR19970081263A KR19990061009A KR 19990061009 A KR19990061009 A KR 19990061009A KR 1019970081263 A KR1019970081263 A KR 1019970081263A KR 19970081263 A KR19970081263 A KR 19970081263A KR 19990061009 A KR19990061009 A KR 19990061009A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 반도체소자의 비아 콘택(via contact) 형성방법에 관한 것으로, 다층 금속배선을 형성하기 위하여 제1금속배선과 접속되는 비아 콘택을 형성하되, 전면에 금속층을 형성한 다음, 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함) 공정으로 평탄화시켜 형성한 후, 상기 CMP 공정으로 생성된 크랙 부분에 희생금속층을 형성하여 채우고, 열처리공정을 실시하여 오염 물질을 게터링(gettering)한 다음, 후속 공정으로 세정공정을 실시함으로써 상기 크랙 부분 이외의 부분에 증착된 희생금속층과 오염물질을 동시에 제거하여 비아 콘택의 파괴(failure) 및 제1금속배선의 단선을 방지하여 소자의 전기적 특성을 향상시키는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a via contact of a semiconductor device, wherein a via contact connected to a first metal wiring is formed to form a multilayer metal wiring, and a metal layer is formed on a front surface thereof, and then chemical mechanical polishing ( chemical mechanical polishing (hereinafter referred to as CMP) process, and then forming and filling a sacrificial metal layer on the crack portion generated by the CMP process, and then performing a heat treatment process to getter the contaminants, and then Technology to improve the electrical characteristics of the device by preventing the destruction of the via contact and disconnection of the first metal wiring by simultaneously removing the sacrificial metal layer and contaminants deposited on the portions other than the crack portion by performing the cleaning process in the process to be.
Description
본 발명은 반도체소자의 비아 콘택 형성방법에 관한 것으로서, 특히 제1금속배선과 접속되는 비아 콘택을 형성하고, CMP 공정으로 평탄화한 다음, 희생금속층을 형성하여 상기 CMP 공정으로 생성된 크랙을 보상하고, 열처리공정을 실시하여 오염물질을 게터링한 다음, 세정공정으로 상기 희생금속층 및 오염 물질을 제거하여 비아 콘택의 파괴와 제1금속배선의 단선을 방지하는 기술에 관한 것이다.The present invention relates to a method for forming a via contact of a semiconductor device. In particular, a via contact connected to a first metal wiring is formed, planarized by a CMP process, and then a sacrificial metal layer is formed to compensate for cracks generated by the CMP process. In addition, the present invention relates to a technique of performing a heat treatment process to getter contaminants, and then removing the sacrificial metal layer and the contaminants in a cleaning process to prevent breakage of via contacts and disconnection of the first metal wiring.
종래기술에 따른 반도체소자의 비아 콘택 형성방법에 대하여 살펴보기로 한다.A method of forming a via contact of a semiconductor device according to the prior art will be described.
먼저, 반도체소자를 형성하는 공지의 기술을 이용하여 반도체기판 상부에 소자들을 형성하고, 제1금속배선을 이용 연결한 후, 상기 제1금속층 상부에 층간절연막을 형성한다. 다음, 상기 층간절연막의 상부에 감광막을 도포한 후 노광 및 현상공정을 통하여 비아 콘택홀을 형성하기 위한 콘택 마스크를 형성한다.First, devices are formed on a semiconductor substrate by using a known technique of forming a semiconductor device, and connected by using a first metal wiring, and then an interlayer insulating film is formed on the first metal layer. Next, after the photosensitive film is coated on the interlayer insulating film, a contact mask for forming a via contact hole is formed through an exposure and development process.
그리고, 상기 콘택 마스크를 이용하여 상기 층간절연막을 식각하여 비아 콘택홀을 형성한다.The interlayer insulating layer is etched using the contact mask to form a via contact hole.
다음, 상기 비아 콘택홀을 매립하는 콘택 플러그를 형성하고, 상기 층간절연막이 노출될 때까지 CMP 공정을 실시한다.Next, a contact plug filling the via contact hole is formed, and a CMP process is performed until the interlayer insulating film is exposed.
그 다음, 상기 CMP 공정으로 발생한 오염물질을 제거하는 세정공정을 실시한다.Next, a cleaning process for removing contaminants generated by the CMP process is performed.
그리고, 상기 콘택 플러그와 접속되는 제2금속배선을 형성한다.Then, a second metal wiring connected to the contact plug is formed.
상기한 바와 같이 종래기술에 따른 반도체소자의 비아 콘택 형성방법은, 제1금속배선을 형성하고 실시하는 CMP 공정에서 사용하는 슬러리에 의해 표면이 오염되고, 상기 슬러리에 의해 비아 내의 산화막과 접착층 계면이 벌어지는 크랙(crack) 현상이 발생된다. 상기와 같은 오염물질은 소자의 특성을 열화시키기 때문에 후속 세정공정이 필수적이고, 일반적으로 습식식각 방법으로 세정공정을 실시하지만 상기 세정공정중 CMP 공정에서 발생한 크랙에 의하여 산화막과 접착층 사이의 계면으로 식각용액이 침투하여 하부의 금속배선의 단선을 유발하여 후속 열처리공정 등에서 소자의 신뢰성 및 특성을 저하시키는 문제점이 있다.As described above, in the method of forming a via contact of a semiconductor device according to the prior art, the surface is contaminated by a slurry used in the CMP process of forming and implementing the first metal wiring, and the oxide film and the adhesive layer interface in the via are separated by the slurry. Cracking phenomenon occurs. Since such contaminants deteriorate the characteristics of the device, a subsequent cleaning process is essential, and in general, the cleaning process is performed by a wet etching method, but etching is performed to the interface between the oxide film and the adhesive layer by cracks generated in the CMP process during the cleaning process. The solution penetrates and causes a disconnection of the lower metal wiring, thereby lowering the reliability and characteristics of the device in a subsequent heat treatment process.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 다층으로 금속배선을 형성하는 공정시 비아 콘택홀을 매립하는 콘택 플러그를 형성하고, CMP 공정을 실시한 다음, 상기 CMP 공정으로 발생한 크랙을 보상하기 위하여 희생금속층을 형성하고, 열처리공정을 실시한 다음, 세정공정을 실시함으로써 비아 콘택의 파괴 및 제1금속배선의 단선을 방지하여 반도체소자의 특성을 향상시키는 반도체소자의 비아 콘택 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art, to form a contact plug for filling the via contact hole in the process of forming a metal wiring in a multi-layer, to perform a CMP process, to compensate for the cracks generated by the CMP process In order to provide a method for forming a via contact of a semiconductor device, a sacrificial metal layer is formed, a heat treatment step is performed, and a cleaning step is performed to prevent breakage of the via contact and disconnection of the first metal wiring, thereby improving the characteristics of the semiconductor device. There is a purpose.
도 1 내지 도 6 은 본 발명에 따른 반도체소자의 비아 콘택 형성방법을 도시한 단면도.1 to 6 are cross-sectional views showing a via contact forming method of a semiconductor device according to the present invention.
도면의 주요부분에 대한 부호 설명Explanation of symbols for the main parts of the drawings
10 : 제1금속배선 11 : 제1절연막10: first metal wiring 11: first insulating film
12 : 평탄화막 13 : 제2절연막12 planarization film 13 second insulating film
15 : 제3절연막 17 : 제1Ti층15: third insulating film 17: first Ti layer
19 : 제1TiN층 21 : 텅스텐층19: first TiN layer 21: tungsten layer
23 : 희생금속층 25 : 제2Ti층23: sacrificial metal layer 25: the second Ti layer
27 : 제2금속배선 29 : 제3Ti층27: second metal wiring 29: third Ti layer
31 : 제2TiN층31: 2nd TiN layer
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 비아 콘택 형성방법은,In order to achieve the above object, a method of forming a via contact of a semiconductor device according to the present invention includes:
소정 구조의 반도체기판 상에 형성되어 있는 평탄화막 상에 제1금속배선을 형성하는 공정과,Forming a first metal wiring on the planarization film formed on the semiconductor substrate having a predetermined structure;
상기 제1금속배선의 비아 콘택으로 예정되는 부분을 노출시키는 비아 콘택홀을 구비하는 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a via contact hole exposing a portion of the first metal wiring to be a via contact;
상기 비아 콘택홀을 매우는 콘택 플러그를 형성하되, 상기 구조 전면에 금속층의 증착 및 CMP 공정에 의해 형성하는 공정과,Forming a contact plug to form the via contact hole, and forming a metal layer on the entire surface of the structure by deposition and a CMP process;
상기 구조 상부에 희생금속층을 형성하고, 열처리공정을 실시하는 공정과,Forming a sacrificial metal layer on the structure and performing a heat treatment process;
상기 희생금속층 및 열처리공정으로 게터링된 오염물질을 습식식각방법으로 제거하는 공정과,Removing the contaminants gettered by the sacrificial metal layer and the heat treatment process by a wet etching method;
상기 콘택 플러그를 통하여 제1금속배선과 접속되는 제2금속배선을 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a second metal wiring connected to the first metal wiring through the contact plug.
이하, 본 발명에 따른 반도체소자의 비아 콘택 형성방법에 관하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a via contact of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 6 은 본 발명에 따른 반도체소자의 비아 콘택 형성방법을 도시한 단면도이다.1 to 6 are cross-sectional views illustrating a method for forming a via contact of a semiconductor device according to the present invention.
먼저, 반도체소자를 형성하는 공지의 기술을 이용하여 반도체기판(도시안됨) 상부에 MOS 전계효과 트랜지스터, 비트라인 및 캐패시터 들과 같은 소자들을 형성한 다음, 상기 구조를 평탄화하는 평탄화막(12)을 형성하고, 제1금속배선(10)을 이용하여 상기 소자들과 연결한 후, 상기 제1금속배선(10) 상부에 제1절연막(11), 제2절연막(13) 및 제3절연막(15)을 순차적으로 형성하여 층간 절연 및 평탄화를 시킨다. 상기 제1금속배선(10)은 Al 을 사용한다.First, devices such as MOS field effect transistors, bit lines, and capacitors are formed on a semiconductor substrate (not shown) using a known technique for forming a semiconductor device, and then the planarization film 12 for planarizing the structure is formed. And a first insulating layer 11, a second insulating layer 13, and a third insulating layer 15 formed on the first metal wiring 10 after the first metal wiring 10 is connected to the elements. ) Are sequentially formed to provide interlayer insulation and planarization. The first metal wire 10 uses Al.
다음, 상기 제3절연막(15) 상부에 비아 콘택홀으로 예정된 부분을 노출시키는 감광막 패턴(도시안됨)을 형성하고, 상기 감광막 패턴을 콘택 마스크로 사용하여 상기 제3절연막(15), 제2절연막(13) 및 제1절연막(11)을 제거하여 상기 제1금속배선(10)을 노출시키는 비아 콘택홀을 형성한다. (도 1참조)Next, a photoresist pattern (not shown) is formed on the third insulating layer 15 to expose a predetermined portion as a via contact hole, and the third insulating layer 15 and the second insulating layer are formed using the photoresist pattern as a contact mask. (13) and the first insulating layer 11 are removed to form a via contact hole exposing the first metal wiring 10. (See Fig. 1)
그 다음, 상기 구조 상부에 제1Ti층(17)과 제1TiN층(19)의 적층구조로 형성된 접착층(glue layer)을 형성하고, 그 상부에 텅스텐막(21)을 형성하여 상기 비아 콘택홀을 매립하여 콘택 플러그를 형성한다. (도 2참조)Next, a glue layer formed of a stacked structure of the first Ti layer 17 and the first TiN layer 19 is formed on the structure, and a tungsten film 21 is formed on the structure to form the via contact hole. Landfill to form contact plugs. (See Fig. 2)
다음, 상기 텅스텐막(21), 제1TiN층(19) 및 제1Ti층(17)을 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함) 공정으로 상기 제3절연막(15)이 노출될때까지 연마하여 제거한다. (도 3참조)Next, the tungsten film 21, the first TiN layer 19, and the first Ti layer 17 are polished by chemical mechanical polishing (hereinafter referred to as CMP) until the third insulating film 15 is exposed. To remove it. (See Fig. 3)
그 다음, 상기 구조 상부에 Ti층으로 희생금속층(23)을 형성하여 상기 CMP 공정시 발생한 크랙 부분을 보상한 후, 급속열처리(rapid thermal process, 이하 RTP 라 함)공정을 실시하여 오염 물질을 게터링(gettering)한다. 상기 희생금속층(23)은 화학기상증착(chemical vapor deposition, 이하 CVD 라 함)방법 또는 물리기상증착(physical vapor deposition, 이하 PVD 라 함) 방법을 사용하여 형성한다. (도 4참조)Next, the sacrificial metal layer 23 is formed on the upper portion of the structure to compensate for the cracks generated during the CMP process, and then a rapid thermal process (hereinafter referred to as RTP) is performed to remove contaminants. Gettering The sacrificial metal layer 23 is formed using a chemical vapor deposition (hereinafter referred to as CVD) method or a physical vapor deposition (hereinafter referred to as PVD) method. (See Fig. 4)
그리고, 비.오.이.(buffered oxide etchant, 이하 BOE 라 함)용액을 이용한 습식식각공정으로 상기 크랙 부분에 형성된 희생금속층(23)을 제외한 희생금속층(23) 및 오염물질을 동시에 제거한다. (도 5참조)The sacrificial metal layer 23 and the contaminants are removed at the same time by a wet etching process using a buffered oxide etchant (hereinafter referred to as BOE) solution except for the sacrificial metal layer 23 formed on the crack portion. (See Fig. 5)
다음, 상기 구조 상부에 제2Ti층(25)을 형성하고, 그 상부에 제2금속배선(27)으로 Al을 형성한다.Next, a second Ti layer 25 is formed on the structure, and Al is formed on the second metal wiring 27 on the structure.
그 다음, 상기 제2금속배선(27) 상부에 제3Ti층(29) 및 제2TiN층(31)을 순차적으로 형성한다. (도 6참조)Next, a third Ti layer 29 and a second TiN layer 31 are sequentially formed on the second metal wiring 27. (See FIG. 6)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 비아 콘택 형성방법은, 다층 금속배선을 형성하기 위하여 제1금속배선과 접속되는 비아 콘택 플러그을 형성하되 비아 콘택홀을 금속층으로 매립한 다음, CMP 공정으로 평탄화를 시켜 형성한 후, 상기 CMP 공정으로 생성된 크랙 부분에 희생금속층을 형성하여 채우고, 열처리공정을 실시하여 오염 물질을 게터링한 다음, 후속 공정으로 세정공정을 실시함으로써 상기 크랙 부분 이외의 부분에 증착된 희생금속층과 오염물질을 동시에 제거하여 비아 콘택의 파괴 및 제1금속배선의 단선을 방지하여 소자의 전기적 특성을 향상시키는 이점이 있다.As described above, in the method for forming a via contact of a semiconductor device according to the present invention, a via contact plug connected to the first metal wiring is formed to form a multilayer metal wiring, and the via contact hole is filled with a metal layer, and then the CMP process is performed. After forming by flattening, the sacrificial metal layer is formed and filled in the crack portion generated by the CMP process, the heat treatment process is performed to getter the contaminants, and then the cleaning process is performed in a subsequent process to carry out a portion other than the crack portion. By simultaneously removing the sacrificial metal layer and contaminants deposited thereon, there is an advantage of improving the electrical characteristics of the device by preventing the breakage of the via contact and the disconnection of the first metal wiring.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019970081263A KR100268809B1 (en) | 1997-12-31 | 1997-12-31 | Manufacturing method for via contact of semiconductor device |
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| KR1019970081263A KR100268809B1 (en) | 1997-12-31 | 1997-12-31 | Manufacturing method for via contact of semiconductor device |
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| KR100268809B1 KR100268809B1 (en) | 2000-10-16 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100422905B1 (en) * | 2001-10-31 | 2004-03-16 | 아남반도체 주식회사 | Method for manufacturing semiconductor devices |
| KR100447970B1 (en) * | 2001-12-15 | 2004-09-10 | 주식회사 하이닉스반도체 | Method of making metal wiring in semiconductor device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102922415B (en) * | 2011-08-10 | 2015-05-13 | 无锡华润上华科技有限公司 | Chemical mechanical polishing method capable of prolonging service life of polishing pad |
| CN103435002A (en) * | 2013-08-05 | 2013-12-11 | 中航（重庆）微电子有限公司 | MEMS sacrificial layer etching method |
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1997
- 1997-12-31 KR KR1019970081263A patent/KR100268809B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100422905B1 (en) * | 2001-10-31 | 2004-03-16 | 아남반도체 주식회사 | Method for manufacturing semiconductor devices |
| KR100447970B1 (en) * | 2001-12-15 | 2004-09-10 | 주식회사 하이닉스반도체 | Method of making metal wiring in semiconductor device |
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