KR20050001537A - Method of forming metal wiring in flash memory device - Google Patents
Method of forming metal wiring in flash memory device Download PDFInfo
- Publication number
- KR20050001537A KR20050001537A KR1020030041723A KR20030041723A KR20050001537A KR 20050001537 A KR20050001537 A KR 20050001537A KR 1020030041723 A KR1020030041723 A KR 1020030041723A KR 20030041723 A KR20030041723 A KR 20030041723A KR 20050001537 A KR20050001537 A KR 20050001537A
- Authority
- KR
- South Korea
- Prior art keywords
- contact hole
- forming
- trenches
- metal wiring
- trench
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
Description
본 발명은 플래쉬 메모리 소자의 금속배선 형성방법에 관한 것으로, 특히 콘택 퍼스트 듀얼 다마신(contact first dual damascene) 방식을 적용하여 금속배선을 형성할 때 금속배선간을 절연시키는 트렌치용 산화막이 식각 손실에 의한 누화(cross talk) 현상을 방지할 수 있는 플래쉬 메모리 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal interconnection of a flash memory device. In particular, an oxide film for trenches insulated between metal interconnections when forming a metal interconnection by applying a contact first dual damascene method is used for etching loss. The present invention relates to a metal wiring forming method of a flash memory device capable of preventing cross talk.
최근 115 nm급 낸드 플래쉬(NAND flash)의 비트라인과 같은 금속배선 형성시 콘택홀을 먼저 형성한 후에 트렌치를 형성하는 콘택 퍼스트 듀얼 다마신 방식을 적용하고 있다.Recently, when forming a metal wiring such as a bit line of a 115 nm NAND flash, the contact first dual damascene method of forming a contact hole and then forming a trench is applied.
종래 플래쉬 메모리 소자의 금속배선 형성방법은 콘택 퍼스트 듀얼 다마신 방식에 의해 콘택홀 및 다수의 배선용 트렌치를 형성한 후, 콘택홀 및 다수의 트렌치에 금속배선용 도전성 물질을 증착하고, 화학적 기계적 연마 공정으로 금속배선을 형성한다. 그런데, 금속배선 공정을 완료할 때까지 수차례의 포토레지스트 패턴 제거 공정, 수차례의 세정 공정 등을 거치게 되고, 이러한 공정 동안에 금속배선간을 절연시키는 트렌치용 산화막은 식각 손실(etch loss)을 당하게 되어 금속배선 사이의 폭이 좁아지게 되며, 이로 인하여 누화(cross talk) 현상이 발생하게 된다. 이러한 누화 현상은 소자의 신뢰성을 저하시킬 뿐만 아니라 소자의 고집적화 실현도 어렵게 한다.In the conventional method of forming a metal wiring of a flash memory device, a contact hole and a plurality of wiring trenches are formed by a contact first dual damascene method, and then a conductive material for metal wiring is deposited in the contact hole and a plurality of trenches, and a chemical mechanical polishing process is performed. Form metal wiring. However, the photoresist pattern removal process and the cleaning process are performed several times until the metal wiring process is completed. During this process, the trench oxide film that insulates the metal wiring is subjected to etch loss. As a result, the width between the metal wires is narrowed, which causes cross talk. This crosstalk phenomenon not only lowers the reliability of the device but also makes it difficult to realize high integration of the device.
따라서, 본 발명은 금속 배선간을 절연시키는 트렌치용 산화막의 폭을 안정적으로 확보하여 인접된 금속배선간에 발생되는 누화현상을 방지하므로, 금속배선의 전기적 특성을 향상시키고, 소자의 고집적화를 실현시킬 수 있는 플래쉬 메모리 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Therefore, the present invention stably secures the width of the oxide oxide film that insulates the metal wires, thereby preventing crosstalk occurring between adjacent metal wires, thereby improving the electrical characteristics of the metal wires and achieving high integration of the device. It is an object of the present invention to provide a method for forming metal wiring of a flash memory device.
도 1a 내지 1e는 본 발명의 실시예에 따른 플래쉬 메모리 소자의 금속배선 형성방법을 설명하기 위한 소자의 단면도.1A to 1E are cross-sectional views of a device for explaining a method for forming metal wiring of a flash memory device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 반도체 기판 12: 질화막11: semiconductor substrate 12: nitride film
13: 층간 절연막 14: 트렌치 식각정지막13: interlayer insulating film 14: trench etch stop film
15: 트렌치용 산화막 16: 제 1 유기 버텀-반사방지막15: oxide film for trenches 16: first organic bottom antireflection film
17: 콘택홀 18: 제 2 유기 버텀-반사방지막17: contact hole 18: second organic bottom anti-reflection film
19: 트렌치 20: 콘택홀용 포토레지스트 패턴19: trench 20: photoresist pattern for contact hole
21: 트렌치용 포토레지스트 패턴 30: 금속배선21: photoresist pattern for trench 30: metal wiring
100: 식각 방지/보상 절연막 스페이서100: etch stop / compensation insulation spacer
이러한 목적을 달성하기 위한 본 발명의 실시예에 따른 플래쉬 메모리 소자의 금속배선 형성방법은 듀얼 다마신 방식으로 반도체 기판 상의 다층 구조의 절연막에 콘택홀 및 다수의 트렌치들을 형성하는 단계; 상기 콘택홀 및 상기 다수의 트렌치들의 측벽에 식각 방지/보상 절연막 스페이서를 형성하는 단계; 및 플러그 이온 주입 공정 및 금속배선 전 세정 공정을 실시한 후, 상기 콘택홀 및 상기 다수의 트렌치들을 도전성 물질로 채워 금속배선들을 형성하는 단계를 포함한다.Metal interconnection forming method of a flash memory device according to an embodiment of the present invention for achieving this object comprises the steps of forming a contact hole and a plurality of trenches in an insulating film of a multi-layer structure on a semiconductor substrate in a dual damascene method; Forming an etch stop / compensation insulating layer spacer on sidewalls of the contact hole and the plurality of trenches; And after performing the plug ion implantation process and the pre-metal wiring cleaning process, filling the contact hole and the plurality of trenches with a conductive material to form metal wirings.
상기에서, 상기 식각 방지/보상 절연막 스페이서는 스텝 커버리지 특성이 우수한 절연물질로 질화물 또는 산화물을 10 ~ 200 Å의 두께로 증착한 후, 스페이서 식각 공정을 실시하여 형성한다.The etching preventing / compensation insulating layer spacer may be formed by depositing a nitride or an oxide with a thickness of 10 to 200 GPa with an insulating material having excellent step coverage characteristics, and then performing a spacer etching process.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명함으로써, 본 발명을 상세하게 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예는 본발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art the scope of the invention It is provided for complete information.
도 1a 내지 1e는 본 발명의 실시예에 따른 플래쉬 메모리 소자의 금속배선 형성방법을 설명하기 위한 소자의 단면도이다.1A to 1E are cross-sectional views of devices for describing a method for forming metal wirings of a flash memory device according to an exemplary embodiment of the present invention.
도 1a를 참조하면, 단위 소자들이 형성된 반도체 기판(11) 상에 질화막(12), 층간 절연막(13), 트렌치 식각정지막(14) 및 트렌치용 산화막(15)을 순차적으로 형성한다. 트렌치용 산화막(15) 상에 제 1 유기 버텀-반사방지막(16)을 도포하고, 그 상부에 콘택홀용 포토레지스트 패턴(20)을 형성한다. 콘택홀용 포토레지스트 패턴(20)을 이용한 식각 공정으로 제 1 유기 버텀-반사방지막(16), 트렌치용 산화막(15), 트렌치 식각정지막(14), 층간 절연막(13) 및 질화막(12)을 순차적으로 식각하여 반도체 기판(11)이 저면을 이루는 콘택홀(17)을 형성한다.Referring to FIG. 1A, a nitride layer 12, an interlayer insulating layer 13, a trench etch stop layer 14, and a trench oxide layer 15 are sequentially formed on a semiconductor substrate 11 on which unit elements are formed. The first organic bottom anti-reflection film 16 is coated on the trench oxide film 15, and a contact hole photoresist pattern 20 is formed thereon. The first organic bottom anti-reflective film 16, the trench oxide film 15, the trench etch stop film 14, the interlayer insulating film 13, and the nitride film 12 are etched using the contact hole photoresist pattern 20. Etching is sequentially performed to form a contact hole 17 having a bottom surface of the semiconductor substrate 11.
도 1b를 참조하면, 콘택홀용 포토레지스트 패턴(20) 및 제 1 유기 버텀-반사방지막(16)을 제거하고, 제 1 세정 공정을 진행한다. 콘택홀(17)이 형성된 전체 구조상에 제 2 유기 버텀-반사방지막(18)을 도포한다. 제 2 유기 버텀-반사방지막(18)은 콘택홀(17) 내부에도 일정 두께로 채워지며, 트렌치용 산화막(15) 상에도 형성된다. 제 2 유기 버텀-반사방지막(18) 상에 트렌치용 포토레지스트 패턴(21)을 형성한다. 트렌치용 포토레지스트 패턴(21)을 이용한 식각 공정으로 제 2 유기 버텀-반사방지막(18) 및 트렌치용 산화막(15)을 식각하고, 계속해서 노출되는 트렌치 식각정지막(14)을 과도식각 공정으로 제거하여 다수의트렌치들(19)을 형성한다. 다수의 트렌치들(19) 사이의 패터닝된 트렌치용 산화막(15)의 제 1 폭(W1)은 디자인 룰에 따라 형성된 트렌치용 포토레지스트 패턴(21)의 폭에 의존되며, 이 폭(W1)은 적어도 소자 동작시 금속 배선과 이에 이웃된 금속 배선 사이의 누화(cross talk) 현상을 방지할 수 있는 폭이다.Referring to FIG. 1B, the contact hole photoresist pattern 20 and the first organic bottom anti-reflection film 16 are removed and a first cleaning process is performed. The second organic bottom anti-reflection film 18 is coated on the entire structure in which the contact hole 17 is formed. The second organic bottom anti-reflection film 18 is also filled in the contact hole 17 to a predetermined thickness, and is formed on the trench oxide film 15. A trench photoresist pattern 21 is formed on the second organic bottom anti-reflection film 18. The second organic bottom anti-reflective film 18 and the trench oxide film 15 are etched by the etching process using the trench photoresist pattern 21, and the subsequently exposed trench etch stop layer 14 is subjected to the transient etching process. To form a plurality of trenches 19. The first width W1 of the patterned trench oxide layer 15 between the plurality of trenches 19 depends on the width of the trench photoresist pattern 21 formed according to the design rule, and the width W1 is It is at least a width capable of preventing cross talk between the metal wiring and the adjacent metal wiring during the device operation.
도 1c를 참조하면, 트렌치용 포토레지스트 패턴(21) 및 제 2 유기 버텀-반사방지막(18)을 제거하고, 제 2 세정공정을 진행한다. 이로 인하여, 반도체 기판(11)의 일부가 노출된 콘택홀(17)과 다수의 트렌치(19)가 완성된다. 그런데, 트렌치용 포토레지스트 패턴(21) 및 제 2 유기 버텀-반사방지막(18)을 제거 공정과, 제 2 세정 공정을 거치면서 다수의 트렌치들(19) 사이의 패터닝된 트렌치용 산화막(15)은 식각 손실(etch loss)이 발생되어 제 1 폭(W1)보다 작은 제 2 폭(W2)으로 된다. 패터닝된 트렌치용 산화막(15)의 폭이 좁아진다는 것은 금속 배선간의 누화 현상을 일으킬 가능성이 높아짐을 의미한다.Referring to FIG. 1C, the trench photoresist pattern 21 and the second organic bottom anti-reflection film 18 are removed and a second cleaning process is performed. As a result, the contact hole 17 and the plurality of trenches 19 in which a part of the semiconductor substrate 11 is exposed are completed. However, the trench oxide film 15 patterned between the plurality of trenches 19 through the removal process of the trench photoresist pattern 21 and the second organic bottom anti-reflection film 18 and the second cleaning process. An etch loss is generated so that the second width W2 is smaller than the first width W1. The narrow width of the patterned trench oxide film 15 means that the possibility of crosstalk between metal wirings is increased.
도 1d를 참조하면, 전 공정의 식각 손실을 보상하면서 후 공정에서 발생될 식각 손실을 방지하기 위하여, 콘택홀(17) 및 다수의 트렌치들(19)을 포함한 전체 구조상에 스텝 커버리지(step coverage) 특성이 우수한 절연물질, 예를 들어 질화물 또는 산화물을 10 ~ 200 Å의 두께로 증착한 후, 스페이서 식각 공정을 실시하여 콘택홀(17) 및 다수의 트렌치(19)의 측벽에 식각 방지/보상 절연막 스페이서(100)를 형성하고, 제 3 세정 공정을 실시한다. 이후 플러그 이온 주입용 포토레지스트 패턴(도시 않음)을 형성하고, 플러그 이온 주입 공정으로 콘택홀(17)의 저면을 이루는 반도체 기판(11)에 플러그 이온을 주입하고, 플러그 이온 주입용포토레지스트 패턴(도시 않음)을 제거하고, 제 4 세정 공정을 실시하고, 금속배선 전 세정(pre-metal cleaning) 공정을 실시한다. 이와 같은 공정들을 진행하는 동안에 제 2 폭(W2)을 갖는 패터닝된 트렌치용 산화막(15)은 식각 손실로 부터 방지되고, 식각 방지/보상 절연막 스페이서(100)는 어느 정도 식각 손실을 입겠지만, 패터닝된 트렌치용 산화막(15)과 식각 방지/보상 절연막 스페이서(100)에 의한 제 3 폭(W3)은 최초 트렌치용 포토레지스트 패턴(21)에 의해 형성된 트렌치용 산화막(15)의 제 1 폭(W1)과 거의 유사하게 된다.Referring to FIG. 1D, step coverage on the overall structure including the contact hole 17 and the plurality of trenches 19 to compensate for the etch loss of the previous process while preventing the etch loss to be generated in the later process. An insulating material having excellent properties, such as nitride or oxide, is deposited to a thickness of 10 to 200 GPa, and then a spacer etching process is performed to etch prevention / compensation insulating films on the sidewalls of the contact holes 17 and the plurality of trenches 19. The spacer 100 is formed and a 3rd washing process is performed. Thereafter, a plug ion implantation photoresist pattern (not shown) is formed, and plug ions are implanted into the semiconductor substrate 11 forming the bottom surface of the contact hole 17 by a plug ion implantation process, and a plug ion implantation photoresist pattern ( Not shown), a fourth cleaning step is performed, and a pre-metal cleaning step is performed. During such processes, the patterned trench oxide film 15 having the second width W2 is prevented from etching loss, and the etching prevention / compensation insulating film spacer 100 may suffer from etching loss to some extent. The third width W3 by the trench trench 15 and the etching prevention / compensation insulating layer spacer 100 is the first width W1 of the trench oxide 15 formed by the trench photoresist pattern 21. Is almost similar to).
도 1e를 참조하면, 콘택홀(17) 및 다수의 트렌치들(19)을 포함한 전체 구조상에 배선용 도전성 물질을 증착한 후, 화학적 기계적 연마 공정을 통해 금속배선들(30)을 형성한다.Referring to FIG. 1E, after the conductive material for wiring is deposited on the entire structure including the contact hole 17 and the plurality of trenches 19, the metal wires 30 are formed through a chemical mechanical polishing process.
상술한 바와 같이, 본 발명은 콘택홀 및 트렌치의 측벽에 식각 방지/보상 절연막 스페이서를 형성하므로, 듀얼 다마신 공정시에 발생한 식각 손실을 보상하고 이후의 공정시에 발생될 식각 손실을 방지할 수 있어 인접된 금속배선간의 누화현상이 방지되어 금속배선의 전기적 특성을 향상시킬 수 있다.As described above, the present invention forms an etching prevention / compensation insulation spacer on the sidewalls of the contact hole and the trench, thereby compensating for the etching loss generated during the dual damascene process and preventing the etching loss to be generated during the subsequent process. Therefore, crosstalk between adjacent metal lines can be prevented, thereby improving the electrical characteristics of the metal lines.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030041723A KR20050001537A (en) | 2003-06-25 | 2003-06-25 | Method of forming metal wiring in flash memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030041723A KR20050001537A (en) | 2003-06-25 | 2003-06-25 | Method of forming metal wiring in flash memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20050001537A true KR20050001537A (en) | 2005-01-07 |
Family
ID=37217184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020030041723A KR20050001537A (en) | 2003-06-25 | 2003-06-25 | Method of forming metal wiring in flash memory device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20050001537A (en) |
-
2003
- 2003-06-25 KR KR1020030041723A patent/KR20050001537A/en not_active Application Discontinuation
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7078332B2 (en) | Method for manufacturing semiconductor device | |
| KR100471409B1 (en) | Method for fabrication of semiconductor device | |
| KR20050001537A (en) | Method of forming metal wiring in flash memory device | |
| KR100602132B1 (en) | Method for fabricating dual damascene pattern | |
| KR100784074B1 (en) | Method of manufacturing bit line in a semiconductor device | |
| KR20060019357A (en) | Manufacturing method of semiconductor device | |
| KR100875656B1 (en) | Semiconductor device and method for manufacturing the same | |
| KR100737701B1 (en) | Method of manufacturing wire in a semiconductor device | |
| KR100518084B1 (en) | Method of forming a dual damascene pattern in a semiconductor device | |
| KR100421278B1 (en) | Fabricating method for semiconductor device | |
| KR101055754B1 (en) | Metal wiring formation method of semiconductor memory device | |
| KR100792433B1 (en) | Method for manufacturing a semiconductor device | |
| KR100827483B1 (en) | Method for forming metal line of semiconductor device | |
| KR100641488B1 (en) | Method for manufacturing contact of the semiconductor device | |
| KR100268810B1 (en) | Manufacturing method of metal line of semiconductor device | |
| KR100728968B1 (en) | Method of manufacturing semiconductor device | |
| KR100770533B1 (en) | Semiconductor device and method for manufacturing the semiconductor device | |
| KR100571408B1 (en) | Dual damascene wiring manufacturing method of semiconductor device | |
| KR20060131129A (en) | Method for manufacturing a semiconductor device | |
| KR20030051040A (en) | Method of forming a barrier metal layer in a semiconductor device | |
| KR20030018746A (en) | Method for forming metal wiring of semiconductor device | |
| KR20050024853A (en) | Method of forming metal wiring in flash memory device | |
| KR20050042862A (en) | Method of forming metal wiring in flash memory device | |
| KR20000027820A (en) | Method for forming conductive plug of semiconductor devices | |
| KR20020032698A (en) | Method of forming a copper wiring in a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |