KR19990048480A - Capacitor Formation Method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor suitable for increasing the surface area of a storage electrode and increasing a capacitance thereof. Forming a first insulating layer, and sequentially forming a third insulating layer having the same etch selectivity as the second insulating layer having a different etching selectivity with respect to the first insulating layer on the first insulating layer, and Etching the insulating layer, the second insulating layer, and the first insulating layer to expose the impurity region to partially retain the second insulating layer between the first insulating layer and the third insulating layer; Forming a polysilicon layer such that a portion corresponding to the second insulating layer is etched together with the third insulating layer, and removing the third insulating layer using the polysilicon layer as a mask. It is characterized by forming a pole.

Accordingly, in the present invention, the polysilicon is deposited once to form the storage electrode of the capacitor, thereby reducing the number of etching processes, thereby simplifying the process.

Description

Capacitor Formation Method

The present invention relates to a method of forming a capacitor (capacitor), in particular the manufacturing process

The present invention relates to a method for forming a storage electrode of a capacitor of a simplified semiconductor device.

Capacitors have a constant capacitance even if the cell area is reduced due to the high integration of semiconductor devices.

Many studies have been carried out to increase the storage density to have a.

In order to increase the storage density, there is a method of stacking capacitors or forming a three-dimensional structure using a trench.

The laminated structure among the capacitors having the three-dimensional structure is a structure that is easy to manufacture and suitable for mass productivity, while increasing the storage capacity and being immune to the disturbance of charge information caused by alpha particles.

The stacked capacitors are classified into a double stacked structure, a finger structure, or a crown structure according to the shape of the storage electrode.

1A to 1E are general capacitor manufacturing process diagrams according to the prior art.

Referring to FIG. 1A, a field oxide layer 102 defining an active region and a field region of a device is formed on a semiconductor substrate 100.

The gate electrode 106 is formed on the active region of the device of the semiconductor substrate 100 with the gate oxide layer 104 interposed therebetween. A source / drain region is formed in the active regions on both sides of the gate electrode 106. A transistor is formed by forming the impurity diffusion region 103 to be used. In the above-described transistor, a cap insulation layer 108 is formed on the gate electrode 106, and sidewalls 110 are formed on the side surfaces of the cap insulation layer 108 and the gate electrode 106.

A second insulating layer in which silicon oxide is grown on the entire surface of the above-described structure by chemical vapor deposition (CVD) to form a first insulating layer 112, and a thin silicon nitride is grown on the upper surface thereof. The layers 114 are formed by sequentially laminating them. Silicon oxide is further grown on the second insulating layer 114 to form a third insulating layer 116.

After applying a photoresist (PR) on the third insulating layer 116, the photoresist is exposed and developed to expose portions of the impurity region 103 and one sidewall 110 of the gate electrode 106. Patterning is performed to form the first mask pattern 118.

Referring to FIG. 1B, the third insulating layer 116, the second insulating layer 114, and the first insulating layer 112 may be removed using a dry etching method using the first mask pattern 118 as a mask. A portion of the substrate 100 is exposed. After that, the first mask pattern 118 is removed.

The first polysilicon layer 120 is formed to cover the remaining third insulating layer 116, the impurity region 113 of the exposed semiconductor substrate 100, and the sidewall 108 of the gate electrode 106. The silicon oxide is grown on the upper portion thereof, and the fourth insulating layer 122 is sequentially stacked.

Next, after the photoresist is applied on the fourth insulating layer 122, the photoresist is exposed and developed to pattern the exposed portion corresponding to the impurity region 103 and the sidewall 108 of the gate electrode 106. The second mask pattern 126 is formed.

Referring to FIG. 1C, using the second mask pattern 126 as an etching mask, a portion of the first polysilicon layer 120 is exposed by removing the fourth insulating layer 122 by a dry etching method.

Thereafter, when the etching process is completed, the second mask pattern 126 is removed.

The second polysilicon layer 124 is stacked to cover the remaining fourth insulating layer 122 and the exposed first polysilicon layer 120.

Next, a photoresist (PR) 128 is coated on the second polysilicon layer 124, and then exposed and developed according to the above-described method to correspond to a part of the impurity region 103 and the gate electrode 106. Patterning to cover the to form a third mask pattern (128).

Referring to FIG. 1D, the second polysilicon layer 124, the remaining fourth insulating layer 122, and the first polysilicon layer 120 are removed by using the third mask pattern 128 as an etching mask. The third insulating layer 116 remaining in the portion is exposed.

The structure may be selectively etched to remove the fourth insulating layer 122 remaining between the remaining second polysilicon layer 124 and the first polysilicon layer 120 to form the storage electrode 130. The storage electrode 130 has an increased capacitance due to a curved surface area on the outside of the conventional crown structure.

Although not shown in the drawings, a thin silicon nitride is then grown on the storage electrode 130 to form a dielectric, and polycrystalline silicon is deposited thereon to form a plate electrode to complete the manufacture of the capacitor.

However, in the conventional capacitor manufacturing method, by etching the polysilicon layer twice to form the storage electrode, the etching process is performed several times. Also, during the photo process, the contact process due to misalignment and defocus is caused. A problem has occurred.

Accordingly, it is an object of the present invention to provide a method of forming a capacitor in which the storage electrode manufacturing process is simplified.

The present invention is intended to simplify the manufacturing process by reducing the etching process according to the deposition of the polysilicon layer for forming the storage electrode once.

In order to achieve the above object, the capacitor manufacturing method of the present invention comprises the steps of: forming a first insulating layer exposing an impurity region on a semiconductor substrate on which a transistor including a gate electrode and an impurity region is formed; Sequentially forming a third insulating layer having the same etch selectivity as the second insulating layer having a different etching selectivity with respect to the first insulating layer, and forming a third insulating layer, a second insulating layer and a first insulating layer in the impurity region. Partially etching the second insulating layer between the first insulating layer and the third insulating layer to cover the entire surface of the structure, wherein the portion corresponding to the second insulating layer is formed together with the third insulating layer. Forming a polysilicon layer to be etched, and removing the third insulating layer using the polysilicon layer as a mask to form a storage electrode.

1a to 1d is a manufacturing process diagram of a capacitor according to the prior art,

2A to 2E are diagrams illustrating a capacitor manufacturing process according to the present invention.

Explanation of symbols on the main parts of the drawings

100, 200. Semiconductor substrate 102, 202. Field oxide film

103, 203. Impurity regions

104, 204. Gate oxide films 106, 206. Gate electrodes

108, 208. Cap insulation films 110, 210. Sidewalls

120, 124, 227. Polysilicon layers 130, 230. Storage electrodes

232. Dielectrics 234. Plate Electrodes

112, 114, 116, 122, 212, 214, 216, 222, 226. Insulation layer

118, 126, 128, 218, 224, 228.mask pattern

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2a to 2e are capacitor manufacturing process diagrams according to the technique of the present invention.

Referring to FIG. 2A, a field oxide layer 202 defining an active region and a field region of a device is formed on a semiconductor substrate 200 in the same manner as described above. The gate electrode 206 is formed on the active region of the device of the semiconductor substrate 200, and a gate insulating layer 204 is interposed between the semiconductor substrate 200 and the gate electrode 206.

Transistors are formed by forming impurity diffusion regions 203 used as source / drain regions in the active regions on both sides of the gate electrode 206.

In the transistor, a cap insulating layer 208 using silicon nitride is formed on the gate electrode 206, and sidewalls 210 are formed on the side of the cap insulating layer 208 and the gate electrode 206.

Silicon oxide is deposited on the entire surface of the above-described structure by CVD to form a first insulating layer 212, and a thin layer of silicon nitride is deposited thereon to sequentially stack the second insulating layer 214. This second insulating layer 214 has an etch selectivity with respect to the first insulating layer 212 which is silicon oxide, and is used as an etch stop layer in a subsequent step.

Next, after the photoresist is applied to the second insulating layer 214, the photoresist is exposed and developed to pattern the first region to expose portions of the impurity region 203 and the sidewall 212 of the gate electrode 206. A mask pattern PR 218 is formed.

Referring to FIG. 2B, the first insulating layer 212 is partially exposed by removing the second insulating layer 214 using a dry etching method using the first mask pattern 218 as an etching mask.

Thereafter, the first mask pattern 218 is removed.

Silicon oxide is deposited to cover the remaining second insulating layer 214 and the exposed first insulating layer 212 to form a third insulating layer 216, and the HSG 222 is formed to a sufficient thickness thereon. do.

Referring to FIG. 2C, a fourth insulating layer 226 is formed on the HSG 222 using silicon oxide, which is formed on the third and fourth insulating layers 216 and 226. It has a high etching selectivity, which is useful in subsequent processes.

On the fourth insulating layer 226, as described above, the photoresist is coated, exposed, and developed to pattern the impurity region 203 and a portion corresponding to one side wall 212 of the gate electrode 206 to be exposed. As a result, a second mask pattern PR 224 is formed.

Using the second mask pattern 224 as an etching mask, the fourth insulating layer 226 is removed by a dry etching method, the HSG 222 is removed by a wet etching method, and the remaining third insulating layer is again removed. A portion of the sidewalls 210 of the impurity region 203 of the semiconductor substrate 200 and the gate electrode 206 is exposed by removing the 216 and the first insulating layer 212 by a dry etching method.

At this time, since the HSG 222 has high etching selectivity with respect to the fourth insulating layer 226 which is silicon oxide, the remaining third insulating layer 216 and the first insulating layer 212, As shown, it is pitted laterally.

Referring to FIG. 2D, the second mask pattern 224 is removed.

The first polysilicon layer 227 is formed to cover the entire surface of the structure, and the first polysilicon layer formed on the sidewall of the HSG 222 is covered by the photoresist on the upper portion of the structure through the process of applying, exposing, and developing the photoresist. The second mask pattern PR 228 is formed by patterning the 227 to remain.

Referring to FIG. 2E, the first polycrystalline silicon layer 227, the fourth insulating layer 226, and the HSG 222 are removed by using the three mask pattern 228 as an etching mask. Part of the Thereafter, the third mask pattern 228 is removed to form the storage electrode 230. The storage electrode 230 of the present invention has an increased capacitance due to an increase in the surface area of the bent portion inside. Thereafter, silicon nitride is thinly grown on the storage electrode 230 to form the dielectric 232, and polycrystalline silicon is deposited on the storage electrode 230 to form the plate electrode 234, thereby completing the manufacture of the capacitor.

As described above, in the capacitor manufacturing method of the present invention, by depositing polycrystalline silicon once to form a storage electrode of the capacitor, the number of etching processes is reduced, thereby simplifying the process.

Claims (1)

Forming a first insulating layer exposing the impurity region on a semiconductor substrate on which a transistor including an impurity region is formed; Sequentially forming a third insulating layer having the same etching selectivity as the second insulating layer having a different etching selectivity with respect to the first insulating layer on the first insulating layer; Etching the third insulating layer, the second insulating layer, and the first insulating layer to expose the impurity region to partially retain the second insulating layer between the first insulating layer and the third insulating layer. and, Forming a polysilicon layer covering the entire surface of the structure and etching the second insulating layer and the third insulating layer corresponding to the second insulating layer together; And removing the third insulating layer using the polysilicon layer as a mask to form a storage electrode.