KR19990002376A - Apparatus and method for generating data input control signal of address driver IC in PDP-TV. - Google Patents

Abstract

The present invention relates to signal processing for inputting and outputting digital image data in a plasma display panel television (PDP-TV) system including a composite image signal input unit 10, a digital image data processing unit 20, and a PDP driving unit 30. In particular, the digital image data processing unit 20 relates to signal processing for providing data to the PDP driving unit 30. In order to output data from the data interface unit 4 of the digital image data processing unit 20 to the address driver IC 6, only the reference signal and the main clock are interfaced with the timing controller unit 5 of the digital image data processing unit 20. The data interface unit 4 generates and uses a shift signal for shifting data to the address driver IC 6 of the PDP driver unit by using the reference signal and the clock. The present invention proposes a PDP driving method and apparatus capable of simplifying input / output patterns of data by configuring two ICs (6) and thereby reducing noise in a system.

Description

Apparatus and Method for Generating Data Input Control Signal of Address Driving IC in PDP-TV

The present invention relates to a signal processing for inputting and outputting digital image data in a plasma display panel television (PDP-TV) system including a composite image signal input unit, a digital image data processor, and a PDP driver. In particular, the digital image data processor The present invention relates to signal processing for providing a PDP driver.

In the image display method of a TV, a CRT, which is a general TV system, adopts a method in which an electron gun sequentially scans pixel by pixel, and a gray scale is composed of a simple driving circuit driven by an analog method, and the driving speed is several tens of nanoseconds. It is very fast as (ns), but it is very difficult to implement the driving of millions of pixels by one pixel when the number of pixels increases to millions such as HDTV. However, in the case of the PDP, which is a flat panel display, a matrix driving method using a strong nonlinearity characteristic of gas discharge is used instead of scanning by pixel. Nonlinearity is a characteristic of gas discharge. Since the gas discharge phenomenon is caused by ionization through the ionization process of the gas, the discharge occurs only when a voltage higher than the discharge voltage at which the ionization reaction can occur sufficiently is applied. Is a characteristic of gas discharge in which no discharge occurs. PDPs are generally driven by a series of pulses with a constant voltage, and gradation display is implemented by digital rather than analog. However, since gas discharge usually requires a relatively high voltage of several hundred volts, the video signal is amplified and driven. The reason why the PDP is suitable for the enlargement is that not only the process but also the characteristics useful for the enlargement of the gas discharge can be applied to the driving method.

The concept of driving technology of PDP is as follows. PDP is an active light emitting display device in which ultraviolet light generated by gas discharge excites a fluorescent film to implement an image. In other words, since the PDP uses ultraviolet light emitted by gas discharge as a light source corresponding to each pixel, the driving circuit simply functions to form or erase gas discharge for each pixel in order to implement a display image. The driving circuit includes an image signal and signal control unit for each pixel constituting an image, and a high speed high voltage switching control unit that can form or eliminate ultraviolet rays generated from each pixel. The driving operation of the PDP-TV system can be classified into three types: selection operation, holding operation and erasing operation.

The selection operation is a driving operation necessary for initial discharge formation. In the case of Pen + mixture of He + Xe and Ne + Xe commonly used in PDP, potential of 240V ~ 280V is applied. In the case of AC, the third electrode is introduced to reduce the high current caused by the sustain electrode in the surface discharge form and the parasitic capacitor caused by the dielectric, and adopts a driving method that separates the selection operation from the sustain operation.

The holding operation is a driving operation in which discharge is maintained by a holding pulse having a voltage lower than a selection pulse by using the storage function characteristic of gas discharge. In the case of AC type PDP, the memory function effect by wall charge and the self priming effect are used in case of DC type PDP. In the case of the memory type driving method which can separate the selection operation and the holding operation by using the memory function, in the case of high gradation display for realizing a high quality display device, the PDP can operate without deterioration of luminance even for a large display device. It provides a driving method.

In the case of AC-type PDP, the discharge is formed at a low voltage in the period of neutralizing the subordinate charge so that the wall charge is not sufficiently formed, or the wall charge does not reach the normal state due to the erase pulse having a short pulse width. Remove

PDP using gas discharge has a memory function. The memory function is a phenomenon in which the past state affects the present state. In the case of AC PDP, it has a unique memory function due to the wall charges formed in the dielectric. In the case of DC PDP, the charged particle effect is used. Although the PDP adopts the driving method using the row driving method, it would not be possible to apply the large display without the memory function. The memory function is essential for driving a large display element for displaying a high gradation image, and it can be seen that it has a very useful function in gradation display.

AC PDPs have a unique memory function because charged particles such as electrons and ions formed during gas discharge form wall charges in the dielectric covering the electrode. In other words, there is no wall charge in the dielectric when there is no discharge, and wall charge is accumulated in the dielectric when a discharge is formed. When the wall charge is present, the potential applied to the external electrode and the potential caused by the wall charge are added together, so that a discharge is formed at a low voltage. Thus, the operation of discharging at a low potential can be separated by the operation of discharging (addressing) without the help of wall charge and the help of the wall charge. In the case of the AC type PDP having the above characteristics, there is a memory function by wall charge, and various driving methods are used according to the method using such wall charge.

1 is a block diagram of the prior art for displaying input and output of digital data for PDP gradation processing. In general, in the PDP-TV system, a composite video signal input unit, a digital image data processing unit, and a PDP driving unit are included. Rearrange the data. The rearranged digital image data is selected using the main clock of the timing controller 30 to select the data and output the data to the data interface unit 10. In the data interface unit 10, a data stream type suitable for gradation processing is performed. The digital video data is output to the address driver IC unit 20 of the PDP driver. Conventionally, the digital data processing unit outputs data to the address driver IC 20 of the PDP driver by the data shift signal provided by the timing controller unit 30 of the digital image data processor. The method of controlling the data output was common. That is, one address driver IC 20 receives the data from the data interface unit 10 and receives 64 bits of data 16 times each of 4 bits. However, even when the two address driver ICs 20 are simplified as one set, 32 operations are required every 4 bits. Therefore, in order to send the digital image data from the data interface unit 10 to the address driver IC 20, a total of 64 excessive patterns are inputted to input and output the shift signals required by the data interface unit 20 and the timing controller unit 30. It is necessary.

As described above, the shift signal generation method for the data input and output of the prior art has a problem that the port necessary for the input and output of the signal is excessive, the structure of the entire system is complicated, and the resulting noise.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art in which the PDP-TV system requires an excessive pattern for input and output of a shift signal for controlling digital image data output from the data interface unit 10 to the address driver IC 20 in the above-described PDP-TV system. The invention has been invented to solve this problem. In order to output the data from the data interface unit 4 of the digital image data processing unit to the address driver IC 6, the timing controller unit 5 of the digital image data processing unit has a reference signal. Only the main clock is provided to the data interface unit 4, and the data interface unit 4 generates a shift signal for shifting data to the address driver IC 6 of the PDP driver unit using the reference signal and the main clock. Thus, the shift signal from the timing controller section 5 to the data interface section 4 is inputted and outputted. The present invention provides a PDP driving method and apparatus capable of reducing the overall system and reducing noise by simplifying data input / output patterns by reducing the number of ports and by configuring two address driving ICs 6 as a set. .

1 is a block diagram of a conventional data input control signal generating device

2 is an overall configuration diagram of a PDP-TV

3 is a detailed block diagram of a memory unit that is an essential part of FIG. 2;

4 is a block diagram of a data input control signal generating device of the present invention;

5 is a configuration diagram of an address driver IC of the present invention.

* Description of Signs on Main Parts of Drawings

1-AV part 2-ADC part

3-memory 4,10-data interface

5,30-Timing Controller 6,20-Address Drive IC

7-Hold / Scan Drive IC 8-High Voltage Drive Circuit

9-AC / DC switcher 40-Complex video signal processor

50-Digital Data Processing Unit 60-PDP Driver

70-data rearranger 80-address generator

90-control clock generator

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. 2 is for explaining the overall operation of the AC type PDP-TV system. The PDP-TV generally includes a composite video signal processing unit 40 including an AV unit 1 which analog-processes a composite video signal received through an antenna and provides it to the ADC unit, and digitally processes the input analog composite video signal. The ADC unit 2 for performing the operation, the memory unit 3 for rearranging the digital image data inputted from the composite video signal unit 40, and the rearranged digital image data, and are suitable for PDP gray level processing. Digital data comprising a data interface unit 4 for producing a stream, the memory unit 3, the data interface unit 4, and a timing controller unit 5 for generating and supplying a main clock for controlling the entire system. The address driver IC 6 which receives the data stream from the processor 50 and the data interface 4, and supplies data to the plasma panel for gradation processing. It consists of the PDP drive part 60 which consists of the four drive ICs 7. As shown in FIG.

The AV unit 1 receives the NTSC composite signal, separates the analog R, G, and B signals from the horizontal and vertical synchronization signals, and obtains an APL (Average Picture Level) corresponding to the average value of the luminance signal (Y). It supplies to (2). This APL is used to improve the brightness of PDP-TV systems. NTSC composite video signal is interlaced scanning method, and one frame is composed of two fields of Odd / Even, horizontal synchronous signal is about 15.73KHZ, and vertical synchronous signal is about 60Hz. The audio signal separated from the composite video signal is output through the audio amplifier directly to the speaker.

The ADC unit 2 receives analog R, G, and B signals as inputs, converts them into digital data, and outputs them to the memory unit 3. At this time, the digital data is converted into shapes for improving the brightness of the PDP-TV system. Video data. The ADC section 2 is divided into an amplifier section, a clock generation section, a sampling area setting section, and a data mapping section.

The amplifying section in the ADC section 2 amplifies the analog R, G, B and APL signals to a signal level suitable for quantization, and converts the horizontal and vertical synchronization signals into a constant phase and outputs them. The clock generator must use a clock that is synchronized with the input synchronization signal. To this end, the clock generator generates clocks using phase locked loops (PLLs). The PLL is oscillated by the LF (Loop Filter), which outputs the control voltage of PD (Phase Detector), VCXO (Voltage Controlled Crystal Oscillstor), which compares the phase of the input synchronous signal with the phase of the variable pulse output from the loop. A VCXO and a PC (Programmable Counter) for dividing the output of the VCXO and outputting a phase comparison pulse to output a clock synchronized with the input synchronous signal. If the clock synchronized to the input synchronization signal is not used, the vertical linearity of the displayed image is not guaranteed. In addition, the sampling area is set to a vertical position and a horizontal position. The vertical position section is a pulse for setting only the line with the image information among the input signals, and the horizontal position section is a pulse for setting only the time with the image information among the lines set to the vertical position. The vertical position section and the horizontal position section are the standards for sampling. At this time, a total of 480 lines are selected, each with 240 lines in the Odd / Even field. The horizontal position section should be such that there can be at least 853 sampling clocks per selected line. The data mapping unit of the ADC unit 2 maps the R, G, and B data output from the A / D converter into data corresponding to the brightness characteristics of the PDP. In other words, by arranging several vector tables in the ROM and selecting the optimal vector table according to the digitized APL data, the R, G, B, and R: It is provided to the memory unit 3 in the form of B data.

In the memory unit 3, for the PDP gradation processing, it is necessary to reconstruct the video data of one field into a plurality of subfields, and then rearrange from the most significant bit MSB to the least significant bit LSB. In addition, since the image data input by the interlaced scanning method is converted to the progressive scanning method and displayed, an area for storing one frame of image data is required.

4 is a block diagram of a memory unit that performs the above functions. That is, the memory unit 3 can be roughly divided into a data rearrangement unit 70 and an address generation unit 80. In addition, the memory unit 3 includes a control clock generator 90, two frame memories A, B, and a data selector. The data rearrangement unit 70 is composed of shift registers A, B, D-FF MUX. (D flip-flop and multiplexer), and three-state buffers A, B, and the ADC unit 2 in parallel (MSB to LSB). The provided image data is rearranged so as to store bits having the same weight in one address of the frame memory. While the first shift register loads eight samples of image data, in the second shift register, eight samples of image data previously loaded are the least significant bit (LSB, 8) from the most significant bit (MSB, 8 Bits). Bits) are output while sequentially shifting.

In order to continuously rearrange the video data provided by the ADC unit 2, two first and second shift registers are provided, and they alternately load and shift. The D-FF MUX selects the same weighted data (Recordered Data) output in the shift mode and supplies it to the tri-state buffer. In addition, two frame memories are provided for storing one piece of image data (853 x 3 (RGB) x 480 x 8 Bits x 10 Mbit), and they alternately perform write and read operations in units of frames. The video data can be stored and displayed continuously. Therefore, the tri-state buffers A and B serve to connect the rearranged image data provided from the D-FF MUX to the frame memory in the write mode.

Since the address generator 80 converts the image data input by the interlaced scanning method into a sequential scanning method and displays the addressing order and the read addressing order differently. That is, image data of one field stored in the memory is repeatedly read even line data after reading one line of Odd line data.

Further, in the PDP gradation process, one field is divided into several subfields, and image data corresponding to each subfield must be read in turn and provided to the data interface unit 4, so that the reading order is structurally very different from the writing order. Will have Therefore, a write address generator and a read address generator according to the designed memory map configuration are required, and the address selector serves to provide a corresponding address according to each operation mode (write and read mode) of the frame memories A and B.

The control clock generator 90 inputs the vertical and horizontal synchronization signals H and Vsync and the main clock to generate and supply the write / read address clock and all other logic control pulses required to drive the memory unit 3. . The data selector selects and outputs the image data output in the read mode from the frame memories A and B to the data interface unit 4.

The data interface unit 4 temporarily stores R, G and B data from the memory unit 3 and provides the data in the form of data required by the address driver IC 6. It is required to be arranged in accordance with the arrangement of the R, G, and B pixels output from the memory section 3 and supplied to the address driver IC 6, which is why the data interface section 4 is required. The display size is 853 × 3 (r, g, b) × 480, and the data interface unit 4 should temporarily store one line (853 × 3 = 2559 bits) of data. Since the output must be performed simultaneously, two lines of temporary storage (2559 x 2 = 5118 bits) are needed. That is, a total of 24 bits of data of 8 bits each of R, G, and B from the memory unit 3 are sequentially inputted to the first temporary storage area (107 times) (24 bits x 107 = 2598 bits), and at the same time intervals, the second temporary data is stored. The data of the previous one line of the storage area is output in the form of a data stream required by the address driver IC 6. Such an input / output operation alternately occurs in the first and second temporary storage areas. That is, after the first temporary storage area operates in the input mode and the second temporary storage area operates in the output mode, the reverse operation is then repeated.

When the data interface 4 outputs the temporarily stored video data to the address driver IC 6, the data interface unit 4 provides 1 bit of data and 48 bits of video data in a stream form to each driver IC. When data is input to the driver IC in turn (75 times) in this manner, when shifted in parallel, one line of image data (48 bits x 75 = 3600 bits) is loaded into the address driver IC 6. Since this process should be the same as the input mode operation time of other temporary storage areas, the input mode should be operated at twice the frequency of the output mode.

The high voltage drive circuit section 8 is required by the address, scan and sustain driver ICs by combining the DC high voltage supplied from the AC / DC converter section 9 according to the control pulses of various logic levels output from the timing controller section 5. Generate a control pulse so that the PDP can be driven. In addition, the data stream provided from the data interface unit 4 to the address driver IC 6 is also raised to an appropriate voltage level to enable selective writing on the panel.

As described above, the driving method for the PDP gradation process first divides one field (60 Hz) into several subfields (64 gradations: 6 subfields, 256 gradations: 8 subfields), and then divides the image data corresponding to each subfield. Through the address driving IC 6, writing is performed in units of lines. In the subfield to which MSB data is written, the number of discharge sustain pulses is reduced in order from the LSB subfield, and gradation processing is performed in the total discharge sustain period according to a combination thereof. In addition, the driving sequence of all subfields repeats operations of full screen writing and erasing, data writing, and discharge holding (screen display). This process is outlined as follows.

As the operation mode for erasing discharge, in case of AC PDP, the discharge is formed at low voltage in the period of neutralizing the subordinate charge so that the wall charge is not sufficiently formed or the erase charge pulse having short pulse width is applied to the normal state of the wall charge. To prevent the wall charges from being reached, i.e. to erase the wall charges remaining in the selected (discharged) pixels after sustaining the discharge of the previous subfield, the walls on all the pixels for a short period of time that are not visible. A full screen erasing process of initializing the PDP by writing charges and then erasing all the remaining wall charges by erasing all pixels;

In the case of Pen + mixture of He + Xe and Ne + Xe commonly used in PDP, potential of 240V ~ 280V is applied. In the case of AC, the third electrode is introduced to reduce the high current caused by the sustain electrode in the surface discharge form and the parasitic capacitor caused by the dielectric, and adopts a driving method that separates the selection operation from the sustain operation. In the practical application, a selective operation is performed in which a wall charge is selectively formed on a pixel to be discharged by writing the data in line units through the data writing electrode while shifting the scanning pulse sequentially from 1 to 480 to the line scan electrode. In addition, the data writing and scanning process, which is a driving operation required for initial discharge formation,

In the case of AC PDP, the memory driving method that can separate the selection operation and the holding operation by using the memory function effect by wall charge, and the PDP is large in the case of high gradation display to realize high quality display device. A driving method which can operate without deterioration of brightness also in the display element of is provided. In practice, a sustain pulse is alternately applied between the discharge sustain driver electrode and the line scan electrode to start and sustain the discharge of the pixel on which the wall charge is formed. At this time, since the unwritten pixel is affected by the written peripheral pixels, and there is a possibility of causing an error discharge, the discharge sustaining process is performed so that a small amount of erase is performed every time the sustain pulse is applied.

In the AC / DC converter 9, AC power (220V, 60Hz) is input, and the high voltage required to combine the electrode driving pulses shown in FIG. 8 and the DC voltage required by each part constituting the other PDP-TV system. Create and supply

Hereinafter, embodiments of the present invention will be described in detail. 4 is for explaining an embodiment of the present invention. As described above, the digital image data input from the ADC unit 2 is rearranged in the memory unit 3 and selectively sent to the data interface unit 4 in the interface unit, where the address driving IC unit corresponding to the PDP driver unit ( In the PDP-TV driving method for outputting data in the form of a data stream, the data interface unit 4 shifts the data stream to the address driving IC 6 so that one address driving IC 6 is 4 bits. By the 16th, 64bits of data is received and processed. Accordingly, the shift signal of the data interface unit 4 for the shift processing is configured to generate and provide 64 shift signals at the timing controller unit 5. Therefore, 128 patterns for inputting and outputting a shift signal between the timing controller unit 5 and the data interface unit 4 are required. In the present invention, in order to reduce the excessive shift signal input / output pattern, the two address driver ICs are grouped into one set to perform signal processing. By doing so, the input / output pattern of the shift signal is reduced to simplify the system configuration.

As described above, two address driver ICs are processed in one pair, thereby reducing the shift signal pattern by half. However, since the 64 input / output patterns are excessive, it can be said that problems of system configuration complexity and noise sensitivity are present. In order to solve the problem, as illustrated in FIG. 1, the shift controller 30 generates the shift signal in the related art and controls the shift signal in the data interface unit 10 according to the control of the shift signal. In the present invention, as shown in Fig. 4, the timing controller unit 30 uses only two reference signals for the normal main clock and the shift signal generation using the specific two ports. 10), and the data interface unit 10 generates 32 shift signals for outputting data to the address driver IC 20 using its logic based on the main clock and the reference signal. It is making up. Fig. 5 is an explanatory diagram for processing data input using one set of two address driver ICs as described above. The set of IC1 and IC2 described above will be described as an example. If data is continuously input by 4 bits, the corresponding clocks of IC1 and IC2 are inverted and inputted respectively so that the input data can be divided into IC1 and IC2 correctly. To be entered.

As described above, the present invention simplifies the data input / output system by processing two address driving ICs that receive a data stream from the data interface unit as a set, and conventionally uses a timing controller unit 30 to output a shift signal for sending a data stream. In the present invention, the timing controller unit 30 provides only the reference signal necessary for generating the normal main clock and the shift signal to the data interface unit 10 using the specific two ports. The data interface unit 10 generates 32 shift signals for outputting data to the address driver IC 20 using its logic based on the main clock and the reference signal, thereby generating 128 shift signal input / output patterns. By reducing the pattern into four, the effect of simplifying the configuration of the entire system High, and thereby there is an effect to increase the efficiency even for noise in the system.

Claims (4)

In a PDP-TV (Plasma Display Panel Television) system, the image data digitally processed by the analog image signal processor 40 is received and the data is converted into a data stream by the data interface unit 4. An apparatus for generating a shift signal for sending to (6), The shift signal generating apparatus includes a timing controller 30 for outputting a reference signal and a main clock necessary for generating a shift signal; An apparatus for generating a shift signal of a data stream in a PDP-TV, comprising an interface unit (10) for generating a data shift signal using the reference signal of the timing controller unit (30) and the main clock. The PDP-TV of claim 1, wherein the reference signal and the main clock for generating the data shift signal in the timing controller unit 30 and the data interface unit 10 each comprise two input / output ports. Shift signal generator of the data stream in the. 2. The apparatus of claim 1, wherein the address driving ICs (6) of the PDP driver (60) process data input / output in a pair. In the PDP-TV system, it is necessary to receive the image data digitally processed by the analog image signal processor 40 and send the data to the address driver IC 6 of the PDP driver 60 as a data stream from the data interface unit 4. In the method for generating a shift signal, Outputting a reference signal and a main clock necessary for generating the shift signal by using two specific ports of the timing controller unit 30; The data interface unit (10) is a method for generating a shift signal of a data stream in a PDP-TV system comprising the step of generating 32 data shift signals using the input reference signal and the main clock.