GB2326511A - Method and apparatus for driving the address electrodes of a flat plasma display panel. - Google Patents

Description

METHOD AND APPARATUS FOR DRIVING ADDRESS ELECTRODES IN A FLAT PANEL DISPLAY The present invention relates to a flat panel display apparatus and more particularly, relates to a method and an apparatus for driving address electrodes in a flat panel display apparatus which utilizes a red-green-blue strip-type plasma display panel.

Currently, as television sets (hereinafter, referred to as "TV") have become more widely used, consumers are demanding slim display apparatuses which have wide screens and which are easily installable. In view of consumers' needs, the existing cathode ray tube (referred to as "CRT") has started to reveal limitations thereof. Thus, the existing display equipment such as the CRT has come to be replaced by a socalled flat panel display (hereinafter, referred to as "FPD") apparatus that has a wide display area and that is slim as well. Further, recently, research projects therein are in progress enthusiastically at home and abroad.

This kind of the FPD device is largely divided into an emissive device and a nonemissive device. The emissive device is usually called an active emitting device and is a device which emits a light by itself. Representative examples of the emissive device are a field emission display (referred to as "FED") device, a vacuum fluorescent display (referred to as "VFD") type device, an electro-luminescence (referred to as "EL") type device, a plasma display panel (hereinafter, referred to as "PDP") and the like. The nonemissive device is called a passive light emitting device, and representative examples of the non-emissive device are a liquid crystal display (referred to as "LCD") device, an electro-chromic display (referred to as "ECD"), an electro-phoretic display (referred to as "EPID") and the like.

Currently, the LCD device occupies the main stream in products such as desk clocks, calculators, lap-tops and the like. However, when this device is adopted to television sets having the screen size of 21 inches and over, it also shows the limitations up to now due to problems in a manufacturing process of a panel and in obtaining an acceptable product. Further, it has the disadvantages of having a narrow visual field angle and of having a response rate which is subject to a temperature variation. Recently, the PDP is newly attracting public attention as the flat panel display of the next generation which is capable of solving the problems of the LCD device.

Because the PDP emits a light by itself in a principle which is similar to that of a fluorescent lamp, it has a uniform brightness and a high contrast although a screen area is as wide as the screen area of the CRT. In addition, the PDP has a visual field angle of 140 degrees and above, and is well-known as the best wide screen display device which has a screen size of 21 to 55 inches. The panel manufacturing process of the PDP is simplified as compared with that of the LCD device and thereby saves a manufacturing cost. However, because the manufacturing cost of the PDP is more than that of the CRT, manufacturers are carrying out searches to reduce the manufacturing cost.

The plasma display is largely classified into a direct current (referred to as "DC") type and an alternating current (referred to as "AC") type according to a structural difference of a discharge cell thereof and a form of a driving voltage based on the structural difference. The DC type is driven by a DC voltage, whereas the AC type is driven by a sinusoidal AC voltage or by a pulse voltage. The AC type includes such a structure that a dielectric layer covers an electrode to serve as a current regulation resistor, whereas the DC type includes such a structure that an electrode is exposed to a discharge room as it is and that a discharge current comes to flow during a supply of the discharge voltage. Because the AC type has the electrode which is covered with the dielectric, it is more durable than the DC type. The AC type has a further advantage in that a wall electric charge which is generated on a surface of the dielectric as a result of a polarization, causes the cell to have a memory function therein, and is more applicable in the field of display devices than the others.

A color PDP includes a structure of 3 terminals wherein a special electrode is installed in order to improve discharge characteristics thereof. Namely, the 3-terminal structure comprises 3 electrodes per unit cell for display which are an address electrode for entering data, a maintenance electrode for sequentially scanning a line and for maintaining a cell discharge, and a bus electrode for helping a discharge maintenance.

A number of the address electrode for entering data is determined in accordance to a horizontal resolution. For example, in the case where a number of samples per line is 853 for each of the red, green and blue colors, a total number of the samples comes to 2559. Therefore, a required number of the address electrodes is also 2559. In the case where an arrangement of the address electrode has a strip form, red, green and blue electrodes are arranged repeatedly.

As described above, because a circuit arrangement of an electrode driving section is restricted considering a space utilization when thousands the address electrodes are arranged on one side, an upper and lower electrode driving system is adapted wherein the section for driving 1280 electrodes, which are ordered in an odd-numbered sequence, are arranged at an upper end portion of a panel whereas the section for driving 1279 electrodes, which are ordered in an even-numbered sequence, are arranged at a lower end portion thereof (refer to U.S. Patent No. 4,695,838).

Meanwhile, in order to display a TV signal of a system of national television system committee (hereinafter, referred to as "NTSC") on the PDP, a data processing section converts an interlaced scanning system into a sequential scanning system, and also converts data into data of a subfield system for a PDP contrast processing. Further, the data processing section provides 1280 red-green-blue (hereinafter, referred to as "RGB") pixel data per line to the electrode driving section for driving the upper and lower address electrodes of the panel of the PDP in harmony with the arrangement of the address electrode.

Conventionally, a video data processing section of the PDP comprises a data rearranging section for rearranging digital RGB sample data into subfield data for a contrast processing, a frame memory section for converting one scanning system into the other, a data interfacing section, and a timing control section. In particular, the data interfacing section provides previously-latched 2559 pixel data to the upper and lower electrode driving sections in harmony with the arrangement of the upper and lower electrodes while latching 2559 pixel data corresponding to 1 line which is supplied from the memory section. The data interfacing section is configured with an application specific integrated circuit (referred to as "ASIC"), and includes 5118 data latches for storing the pixel data corresponding to 2 lines, a demultiplexer for a data input, and a multiplexer for a data output.

Therefore, because 12 bits of input data have to be loaded over 107 times in a memory region for the upper address electrode of the data interfacing section, input terminals have to be selectively connected to 12 1-bit-latches every time. Also, as 80 bits of data have to be outputted over 16 times, 80 1-bit-latches have to be selectively connected to output terminals every time. Namely, 1280 input line patterns are selectively connected to the 12 input terminals and 1280 output line patterns are selectively connected to the 80 output terminals.

As described above, in order to provisionally store in a relevant storage location the data which corresponds to one line and which is supplied from the memory section in twelve-bit units over 107 times, the data interfacing section receives 107 respective input selection control signals from the timing control section. Additionally, in order to output the stored data in eighty-bit units over sixteen times to the electrode driving section, the data interfacing section receives 16 output selection control signal from the timing control section.

As a result, the data interfacing section necessitates output pins of 2 by 80 through which data is provided to upper and lower address electrode driving sections. Therefore, in the case where the data interfacing section is configured with the ASIC, because circuits have to be designed considering a plurality of data output pins, much time and effort are required when designing a circuit. Also, because many bonding pads are disposed at the edge of an integrated circuit, the size of the integrated circuit increases.

Additionally, when the data interfacing section is installed on a printed circuit board, a wiring design of the printed circuit board becomes highly complicated. These problems cause the unit price of manufacturing the PDP to be raised.

It is an object of the present invention to at least partly overcome the difficulties of the prior art An embodiment of the present invention provides a method and an apparatus for driving address electrodes in a flat panel display equipment wherein a number of data output pins of a data interfacing section is sharply reduced to accomplish the simplification of connection lines and of an internal circuit design.

In order to achieve the above object, the present invention provides a method for driving L address electrodes with L units of relevant 1-bit pixel data via P (where P is a least integer which is greater than or equal to a quotient which is obtained by dividing L by M) units of driving integrated circuits having N numbers of input pins grouped into G groups and having M numbers of output pins, which comprises the steps of: inputting L units of 1-bit pixel data into the G groups completely in K units in sequence, where K=N-P/G; performing the inputting step repeatedly over QIG times; and driving relevant L electrodes simultaneously with L pixel data inputted over Q times.

In order to achieve the above objects, the present invention provides an apparatus for driving L address electrodes with L units of relevant 1 bit pixel data, which comprises: means for configuring the L address electrodes with P units of driving integrated circuits having N numbers of input pins and M numbers of output pins, where P is a least integer which is greater than or equal to a quotient which is obtained by dividing L by M; and means for grouping the P units of the driving integrated circuits into G groups, and for inputting L units of 1-bit pixel data into the respective groups in parallel and in circulation in K units over Q times, where G is a divisor of P excluding 1 and P, K=NP/GandQ=MG/N.

As a result, in the case where a group number of the driving integrated circuits of the address electrode driving sections increases, although a bit number which is entered at a time decreases, an operation speed increases in inverse proportion to a decreased bit number. Thus, a number of data line connections between the data interfacing section and the address electrode driving section decreases by forty, twenty, sixteen and eight lines, in the case of groups 2, 4, 5 and 10, respectively. Therefore, the line connections are adaptively selected between the data interfacing section and the address electrode driving section in accordance with the operation speed, so that when the data interfacing section is configured with a chip, a number of the out pins thereof can be adaptively designed.

The decrease in the number of the output pins of the data interfacing section described above can reduce a whole unit cost of manufacturing the PDP.

The above objects and other advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings, in which: FIG. 1 is a block diagram for showing a circuit configuration of a plasma display panel television set which is a preferred embodiment of a flat panel display apparatus according to the present invention; FIG. 2 is a circuit diagram for showing a circuit configuration of a preferred embodiment of a data interfacing section according to the present invention; FIG. 3 is a timing chart for showing a waveform of respective parts of the data interfacing section shown in FIG. 2; FIG. 4 is a circuit diagram for showing a circuit configuration of a preferred embodiment of an address electrode driving apparatus according to the present invention; FIG. 5 is a timing chart for showing a waveform of respective parts of the address electrode driving apparatus shown in FIG. 4; FIG. 6 is a circuit diagram for showing a circuit configuration of another preferred embodiment of an address electrode driving apparatus according to the present invention; FIG. 7 is a timing chart for showing a waveform of respective parts of the address electrode driving apparatus shown in FIG. 6; FIG. 8 is a circuit diagram for showing a circuit configuration of a further preferred embodiment of an address electrode driving apparatus according to the present invention; FIG. 9 is a timing chart for showing a waveform of respective parts of the address electrode driving apparatus shown in FIG. 8; FIG. 10 is a circuit diagram for showing a circuit configuration of a further preferred embodiment of an address electrode driving apparatus according to the present invention; and FIG. 11 is a timing chart for showing a waveform of respective parts of the address electrode driving apparatus shown in FIG. 10.

A description will be given below in detail with reference to accompanying drawings to a configuration and an operation of a method and an apparatus for driving address electrodes in a flat panel display according to embodiments of the present invention.

PIG. 1 is a block diagram for showing a circuit configuration of a plasma display panel television set which is a preferred embodiment of a flat panel display apparatus according to the present invention. A PDP-TV includes a video processing section for converting an NTSC composite video signal into a signal form which is adapted to the PDP-TV system, and a driving circuit section for displaying processed video data via a panel thereof.

Broadly speaking, a composite video signal which is received via an antenna, is analog-processed by an audio/video (referred to as "A/V") signal processing section 10, and an analog-processed signal is then digitized to a prescribed video signal by an analogto-digital converter (referred to as "ADC") 12. Afterwards, while passing through a data rearranging section 14a, memory section 14b and data interfacing section 14c of a data processing section 14, this video data is converted into a data stream which is adapted to a contrast-processing characteristics of the PDP, and a converted data stream is then provided to an address electrode driving section 20 and 22.

Under the control of a timing controller 16, a high-voltage generating section 18 provides a high-voltage control pulse which is required by an upper address electrode driving section 20, a lower address electrode driving section 22, a scan electrode driving section 24 and a maintenance electrode driving section 26, and a power supplying section 30 inputs an AC voltage (referred to as "ACV") to produce all of the DC voltages (referred to as "DCV's") which are required by a whole system.

A/V signal processing section 10 inputs the NTSC composite video signal to separate an analog RGB and a horizontal or vertical synchronizing signal H.V SYNC, and produces an average picture level (referred to as "APL") which corresponds to an average value of a luminance signal to and which is then provided to ADC 12.

The interlaced scanning system is adopted for the NTSC composite video signal whose one frame consists of two fields of respectively even- and odd-numbered sequences, and whose horizontal and vertical synchronizing signals have frequencies of 15.73 [KHz] and 60 [Hz], respectively. An audio signal which is separated from the composite video signal is directly provided to a speaker via an audio amplifier.

ADC 12'inputs the analog RGB signal to convert an inputted analog RGB signal into digital data, and provides converted digital data to data processing section 14. Here, the digital data is video data whose signal form is converted for a brightness improvement of the PDP-TV system. ADC 12 amplifies the analog RGB signal and the APL signal to have signal levels thereof which are adapted to a quantization, and converts the vertical and horizontal synchronizing signals to have prescribed phases thereof. Also, ADC 12 generates a clock by using a phase-locked loop (referred to as "PLL") in order to use a sampling clock as a clock which is synchronized with an input synchronizing signal.

The PLL compares a phase of a variable pulse from a loop with a phase of an input synchronizing signal, and provides a clock which is synchronized with the input synchronizing signal. In the case where the clock which is not synchronized with the input. synchronizing signal is used, a vertical linearity of a picture to be displayed is not ensured.

Also, ADC 12 sets vertical and horizontal positions of a sampling area. In a vertical position section, only lines which include the video signal among the input signals are set. In a horizontal position section, only time which includes the video signal among the lines which is set to the vertical position, is set. Both the vertical position section and the horizontal position section are a reference for a sampling. As illustrated in Table 1, a total of 480 lines is selected in the 240 lines of units for the vertical position section. The horizontal position section has to correspond to a time interval in which at least 853 sampling clocks can exists per line.

Table 1

items 1 frame remarks odd even a total line 1H-262.5H 262.5H-525H NTSC TV an an active line 22H-263H 284H-525H a selective line 23H-262H 285H-524H Also, ADC 12 maps the RGB data to data which'coincides with a brightness characteristic of the PDP and outputs a mapped RGB data. Namely, ADC 12 includes a read only memory (referred to as "ROM") which has a plurality of vector tables recorded therein, and then maps an optimal vector table read from the ROM 1 to 1 in accordance with a digitized APL data to provide an improved form of RGB data to data processing section 14.

In order to process the contrast of the PDP, data rearranging section 14a of data processing section 14 is required to reconfigure the video data into a plurality of subfields, and then to rearrange data bits from the most significant bit (referred to as "MSB") to the least significant bit (referred to as "LSB"). Data rearranging section 14a performs rearrangement so that the video data provided in parallel may be stored at a location specified by an address of a frame memory as bits having the same weight.

Here, in order to distinguish data for the upper address electrode from data for the lower address electrode, there is configured one word in which among respective 8 1-bit data with respect to rearranged red and blue, 4 1-bit data in an odd-numbered sequence are placed at an upper bit while 4 1-bit data in an even-numbered sequence are placed at a lower bit, and in which among 8 1-bit data with respect to a rearranged green, four one-bit data in an odd-numbered sequence are placed at a lower bit while 4 1-bit data in an even-numbered sequence are placed at an upper bit.

Because memory section 14b of data processing section 14 divides one field into eight subfields for the contrast processing of the PDP, and reads in series the video data corresponding to respective subfields in harmony with an arrangement order of the electrodes to provide the read video data to data interfacing section 14c, a read order is quite different from a write order structurally.

Data interfacing section 14c rearranges the RGB data from memory section 14b in harmony with an arrangement of an RGB pixel of a display section 28 and provides a rearranged RGB data to an address driving integrated circuit (referred to as "IC").

Namely, data interfacing section 14c provisionally stores the RGB data from memory section 14b and then respectively provides read RGB data to upper and lower address electrode driving sections 20 and 22 in a data form which is required by upper and lower address electrode driving sections 20 and 22. More detailed descriptions will be given later.

Timing controller 16 generates a clock signal and control pulses which are necessitated by respective sections in response to a synchronizing signal, and provides the generated clock signal and control pulses to respective sections.

High-voltage generating section 18 combines the DC high-voltages with each other in accordance with a control pulse having various logic levels from timing controller 16, and produces the high-voltage control pulse which is required by upper address electrode driving section 20, by lower address electrode driving section 22, by scan electrode driving section 24 and by maintenance electrode driving section 26, and which enables the PDP to be driven. Upper and lower address electrode driving sections 20 and 22 adequately heighten a voltage level of the data from data interfacing section 14c and a selective entry can be executed into display section 28.

Namely, a driving method for the contrast processing of the PDP according to the present invention, first, divides one field into a plurality of subfields, i.e., 256 contrast 8 subfields, and enters the video data corresponding to respective subfields in the line of unit into display section 28 via upper and lower address electrode driving sections 20 and 22. The method sets a number of a discharge maintenance pulses to a smaller one in an order starting from the subfield having MSB data entered therein to the subfield having LSB data entered therein, and comes to perform the contrast-processing on the basis of a total discharge maintenance period according to a combination therebetween.

Upper and lower address electrode driving sections 20 and 22 include 20 driving IC's which have both debit input pins and 64 bit output pins. More detailed descriptions will be given later.

The same data is displayed twice in even and odd fields and thereby eliminates a flickering which accompanies a non-interlacing scan. A driving order of the divided subfields is described as follows.

1) An entry and elimination of a whole screen: In order to eliminate a wall electric charge which remains at a selected pixel after a discharge maintenance of a previous subfield, the wall electric charge is entered into a whole pixel for a short time which is not enough to be visible, and the whole pixel is then eliminated to eliminate all of the remaining wall electric charges and an initialization is achieved.

2) The entry of data: While shifting a scan pulse in sequence at a scan electrode, a relevant data is entered in the line of unit via an address electrode, and thereby forming the wall electric charge at a pixel which is intended to be discharged.

3) A maintenance of a discharge: The discharge of a pixel having the wall electric charge which is formed therein while alternately applying the maintenance pulse between the maintenance electrode and the scan electrode is initiated and is then maintained. At this time, because there exists such a possibility that a peripheral pixel, which is entered, influences another pixel, which is not entered, to produce an erroneous discharge, an elimination of a narrow range is performed every time after applying the maintenance pulse, and a correct discharge is then performed.

FIG. 2 is a circuit diagram for showing a circuit configuration of a preferred embodiment of a data interfacing section according to the present invention.

A data interfacing section 14c includes upper and lower data interfacing sections 32 and 34, and an input/output control section 36. Respective data interfacing section 32 and 34 includes a pair of provisional storage sections 38 and 40.

Respective provisional storage sections 38 and 40 include storage areas 38a and 40a each for provisionally storing 1280 pixel data, input selecting means 38b and 40b for inputting twelve pixel data into storage areas 38a and 40a over 107 times in response to 107 units of input selection control signals INS1 to INS 107 which are sequentially generated, and output selecting means 38c and 40c for outputting the 1280 pixel data stored in storage areas 38a and 40a in 40 units over 32 times in response to 32 units of output selection control signals OTS1 to OTS32 which are sequentially generated.

Input/output control section 36 includes an operation mode control section 42, first and second control signal generating sections 44 and 46.

First control signal generating section 44 which is configured with a 107-shift register, inputs both a first clock signal CLK1 of 50 [MHz] shown in FIG. 3 and a first reference signal fl07 from timing controller 16, and shifts the first reference signal fl07 over 107 times in response to first clock signal CLK1 to generate 107 input selection control signals INS1 to INS 107 shown in FIG. 3.

Second control signal generating section 46 which is configured with a 32-shift register, inputs both a second clock signal CLK2 of 12.5 (MHz] shown in FIG. 3 and a second reference signal f32 from timing controller 16, and shifts the second reference signal f32 over 32 times in response to second clock signal CLK2 to generate 32 output selection control signals OTS1 to OTS32 shown in FIG. 3.

Operation mode control section 42 includes four AND gates G1 to G4 and two NOT gates G5 and G6. Operation mode control section 42 provides control signals from first and second control signal generating sections 44 and 46 to the pair of provisional storage sections 32 and 34 so that an input/output mode of data may proceed alternately at the pair of provisional storage sections 32 and 34 in response to an input/output mode control signal SLCT shown in FIG. 3.

Therefore, 107 units of input selection control signals INS 1 to INS 107 are provided to upper provisional storage sections 38 of upper and lower data interfacing sections 32 and 34 via AND gate G2 in a logic "high" section of the input/output mode control signal SLCT to store 1280 pixel data supplied from a memory, and at the same time, 32 output selection control signals OTS1 to OTS32 are provided to lower provisional storage section 40 of upper and lower data interfacing sections 32 and 34 via AND gate G4 to output the stored pixel data in forty-bit units over 32 times.

Both a storage operation and an output operation are performed in a logic "low" section of input/output mode control signal SLCT as described above.

Input/output mode control signal SLCT is a pulse signal which has 480-line scan frequency and which is supplied from timing controller 16 or a pulse signal which has 480-line scan frequency and which is supplied from memory section 14b.

Here, as compared with a case where input/output mode control signal SLCT is separately generated by timing controller 16 in harmony with a read timing of a memory, a case where input/output mode control signal SLCT is generated while inputting a read address clock of memory section 14b contributes more to the simplification of a logic configuration of timing controller 16.

FIG. 4 is a circuit diagram for showing a circuit configuration of a preferred embodiment of an address electrode driving apparatus according to the present invention.

Respective upper and lower address electrode driving sections 20 and 22 include 20 units of driving integrated circuits DIC1 to DIC20 each of which includes both 4-bit input pins and 64-bit output pins.

Ten units of driving integrated circuits DIC1, DIC3, DICS, DIC7, DIC9, DICli, DIC13, DIC15, DIC17 and DIC19 in an odd-numbered sequence are grouped into a first group and are input-enabled in response to a third clock signal CLK3 shown in FIG. 5.

Ten units of driving integrated circuits DIC2, DIC4, DIC6, DIC8, DIC10, DIC12, DIC14, DIC16, DIC18 and DIC20 in an even-numbered sequence are grouped into a second group and are inputenabled in response to a fourth clock signal CLK4 shown in FIG. 5.

Respective driving sections are loaded with data corresponding to one line in forty units over a total of 32 times alternately from the first group in an odd-numbered sequence of data interfacing section 14c and from the second group in an even-numbered sequence thereof, and then drives electrodes of one line simultaneously.

Respective address electrode driving sections 20 and 22 are loaded with the data in forty bits of units every time from data interfacing section 14c. Therefore, as compared with loading the data in 80 bits of units into respective address electrode driving sections 20 and 22, the above case can decrease a number of data lines by half. Additionally, a loading speed increases from 16 times to 32 times for the same loading speed.

FIG. 6 is a circuit diagram for showing a circuit configuration of another preferred embodiment of an address electrode driving apparatus according to the present invention.

FIG. 7 is a timing chart for showing a waveform of respective parts of the address electrode driving apparatus shown in FIG. 6.

As shown in FIG. 6, in embodiment 2 of the present invention, respective upper and lower address electrode driving sections 20 and 22 include 20 units of driving integrated circuits DIC1 to DIC20 each of which includes both input pins of 4 bits and output pins of 64 bits. In embodiment 2, driving integrated circuits are grouped into four groups. Namely, a first group includes DIC1, DIC5, DIC9, DIC13 and DIC17, and has a first clock signal CLK1 as an enable signal which is applied thereto. A second group includes DIC2, DIC6, DIC10, DIC14 and DIC18, and has a second clock signal CLK2 as an enable signal which is applied thereto. A third group includes DIC3, DIC7, Dip11, DIC15 and DIC19, and has a third clock signal CLK3 as an enable signal which is applied thereto. A fourth group includes DIC4, DIC8, DIC12, DIC16 and DIC20, and has a fourth clock signal CLK4 as an enable signal which is applied thereto.

First integrated circuits DIC1, DIC2, DIC3 and DIC4 of respective groups are commonly connected to first 4-bit lines of 20-bit lines. Second integrated circuits DICS, DIC6, DIC7 and DIC8 of respective groups are commonly connected to second 4-bit lines of 20-bit lines. Third integrated circuits DIC9, DIClO, DIC11 and DIC12 of respective groups are commonly connected to third 4-bit lines of 2ebit lines. Fourth integrated circuits DIC13, DIC14, DIC15 and DIC16 of respective groups are commonly connected to fourth 4-bit lines of 20-bit lines. Last integrated circuits DIC17, DIC18, DIC19 and DIC20 of respective groups are commonly connected to last 4-bit lines of 20-bit lines.

Consequently, in embodiment 2, respective driving sections are loaded with the data corresponding to one line in twenty units over a total of 64 times from data interfacing section 14c while sequentially circulating from the first group to the fourth group, and then drives the electrodes of one line simultaneously.

Because respective address electrode driving sections 20 and 22 are loaded with the data in twenty bits of units every time from data interfacing section 14c, as compared with loading the data in 80 bits of units into respective address electrode driving sections 20 and 22, this case can decrease a number of data lines by a quarter. Of course, a loading speed comes to increase from 16 times to 64 times for the same loading speed.

Also, an output of data interfacing section 14c has to be configured in harmony with these characteristics.

FIG. 8 is a circuit diagram for showing a circuit configuration of a further preferred embodiment of an address electrode driving apparatus according to the present invention. FIG. 9 is a timing chart for showing a waveform of respective parts of the address electrode driving apparatus shown in FIG. 8.

As shown in FIG. 8, in embodiment 3 of the present invention, respective upper and lower address electrode driving sections 20 and 22 include 20 units of driving integrated circuits DIC1 to DIC20 each of which includes both input pins of 4 bits and output pins of 64 bits. In embodiment 3, driving integrated circuits are grouped into five groups. Namely, a first group includes DIC1, DIC6, DIC11 and DIC16, and has a first clock signal CLK1 as an enable signal which is applied thereto. A second group includes DIC2, DIC7, DIC12 and DIC17, and has a second clock signal CLK2 as an enable signal which is applied thereto. A third group includes DIC3, DIC8, DIC13 and DIC18, and has a third clock signal CLK3 as an enable signal which is applied thereto. A fourth group includes DIC4, DIC9, DIC14 and DIC19, and has a fourth clock signal CLK4 as an enable signal which is applied thereto. A fifth group includes DICS, DIC10, DIC1S and DIC20, and has a fifth clock signal CLKS as an enable signal which is applied thereto.

First integrated circuits DIC1, DIC2, DIC3, DIC4 and DICS of respective groups are commonly connected to first 4-bit lines of 16-bit lines. Second integrated circuits DIC6, DIC7, DIC8, DIC9 and DIC10 of respective groups are commonly connected to second Sbit lines of 16-bit lines. Third integrated circuits DIC1 1, DIC12, DIC13, DIC14 and DIC1S of respective groups are commonly connected to third 4-bit lines of 16-bit lines. Last integrated circuits DIC16, DIC17, DIC18, DIC19 and DIC20 of respective groups are commonly connected to last Sbit lines of 16-bit lines.

Consequently, in embodiment 3, respective driving sections are loaded with the data corresponding to one line in sixteen units over a total of eighty times from data interfacing section 14c while sequentially circulating from the first group to the fifth group, and then drives the electrodes of one line simultaneously.

Because respective address electrode driving sections 20 and 22 are loaded with the data in sixteen bits of units every time from data interfacing section 14c, as compared with loading the data in 80 bits of units into respective address electrode driving sections 20 and 22, this case can decrease a number of data lines by one fifth. Of course, a loading speed comes to increase from sixteen times to eighty times for the same loading speed. Also, an output of data interfacing section 14c has to be configured in harmony with these characteristics.

FIG. 10 is a circuit diagram for showing a circuit configuration of a further preferred embodiment of an address electrode driving apparatus according to the present invention. FIG. 11 is a timing chart for showing a waveform of respective parts of the address electrode driving apparatus shown in FIG. 10.

As shown in FIG. 10, in embodiment 4 of the present invention, respective upper and lower address electrode driving sections 20 and 22 include 20 units of driving integrated circuits DIC1 to DIC20 each of which includes both input pins of 4 bits and output pins of 64 bits. In embodiment 4, driving integrated circuits are grouped into ten groups. Namely, a first group includes DIC1 and DIC11, and has a first clock signal CLK1 as an enable signal which is applied thereto. A second group includes DIC2 and DIC12, and has a second clock signal CLK2 as an enable signal which is applied thereto.

A third group includes DIC3 and DIC13, and has a third clock signal CH as an enable signal which is applied thereto. A fourth group includes DIC4 and DIC14, and has a fourth clock signal CLK4 which is applied as an enable signal thereto. A fifth group includes DIC5 and DIC15, and has a fifth clock signal CLK5 which is applied as an enable signal thereto. A sixth group includes DIC6 and DIC16, and has a sixth clock signal CLK6 which is applied as an enable signal thereto. A seventh group includes DIC7 and DIC17, and has a seventh clock signal CLK7 which is applied as an enable signal thereto. An eighth group includes DIC8 and DIC18, and has an eighth clock signal CLK8 which is applied as an enable signal thereto. A ninth group includes DIC9 and DIC19, and has a ninth clock signal CLK9 which is applied as an enable signal thereto. A tenth group includes DIC10 and DIC20, and has a tenth clock signal CLK10 which is applied as an enable signal thereto.

First integrated circuits DIC1, DIC2, DIC3, DIC4, DICS, DIC6, DIC7, DIC8, DIC9 and DIC10 of respective groups are commonly connected to first 4-bit lines of 8bit lines. Second integrated circuits DIC11, DIC12, DIC13, DIC14, DIC15, DIC16, DIC17, DIC18, DIC19 and DIC20 of respective groups are commonly connected to second 4-bit lines of 8-bit lines.

Consequently, in embodiment 4, respective driving sections are loaded with the data corresponding to one line in eight units over a total of 160 times from data interfacing section 14c while sequentially circulating from the first group to the tenth group, and then drives the electrodes of one line simultaneously.

Because respective address electrode driving sections 20 and 22 are loaded with the data in eight bits of units every time from data interfacing section 14c, as compared with loading the data in 80 bits of units into respective address electrode driving sections 20 and 22, this case can decrease a number of data lines by one-tenth. Of course, a loading speed comes to increase from 16 times to 160 times for the same loading speed.

Also, an output of data interfacing section 14c has to be configured in harmony with these characteristics.

While the present invention has been particularly shown and described with reference to particular embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be effected therein without departing from the scope of the invention as defined by the appended claims.

Claims (16)

What is claimed is:

1. A method for driving L address electrodes with L units of relevant l-bit pixel data via P (where P is a least integer which is greater than or equal to a quotient which is obtained by dividing L by M) units of driving integrated circuits having N numbers of input pins grouped into G groups and having M numbers of output pins, said method comprising the steps of: inputting L units of l-bit pixel data into said G groups completely in K units in sequence, where K=N-P/G; performing the inputting step repeatedly over Q/G times; and driving relevant L electrodes simultaneously with L pixel data inputted over Q times.

2. The method for driving address electrodes as claimed in claim 1, wherein said R driving integrated circuits of the respective groups include respective input pins respectively connected to relevant K-bit input lines and are simultaneously input-enabled in response to an input control signal of said respective groups, where R=P/G.

3. The method for driving address electrodes as claimed in claim 2, wherein said driving integrated circuits of the respective groups are arranged at a G interval therebetween.

4. The method for driving address electrodes as claimed in claim 2, wherein said G, K, L, M, N, P, Q and R are 2, 40, 1280, 64, 4, 32 and 10, respectively.

5. The method for driving address electrodes as claimed in claim 2, wherein said G, K, L, M, N, P, Q and R are 4, 20, 1280, 64, 4, 64 and 5, respectively.

6. The method for driving address electrodes as claimed in claim 2, wherein said G, K, L, M, N, P, Q and R are 5, 16, 1280, 64, 4, 80 and 4, respectively.

7. The method for driving address electrodes as claimed in claim 2, wherein said G, K, L, M, N, P, Q and R are 10, 8, 1280, 64, 4, 160 and 2, respectively.

8. An apparatus for driving L address electrodes with L units of relevant 1 bit pixel data, said apparatus comprising: means for configuring said L address electrodes with P units of driving integrated circuits having N numbers of input pins and M numbers of output pins, where P is a least integer which is greater than or equal to a quotient which is obtained by dividing L by M; and means for grouping the P units of said driving integrated circuits into G groups, and for inputting L units of 1-bit pixel data into said respective groups in parallel and in circulation in K units over Q times, where G is a divisor of P excluding 1 and P, K=NP/G and Q=MG/N.

9. The apparatus for driving address electrodes as claimed in claim 8, wherein said R driving integrated circuits of the respective groups include respective input pins respectively connected to relevant K-bit input lines and are simultaneously input-enabled in response to an input control signal of said respective groups, where R=P/G.

10. The apparatus for driving address electrodes as claimed in claim 9, wherein said driving integrated circuits of the respective groups are arranged at a G interval therebetween.

11. The apparatus for driving address electrodes as claimed in claim 8, wherein said G, K, L, M, N, P, Q and R are 2, 40, 1280, 64, 4, 32 and 10, respectively.

12. The apparatus for driving address electrodes as claimed in claim 8, wherein said G, K, L, M, N, P, Q and R are 4, 20, 1280, 64, 4, 64 and 5, respectively.

13. The apparatus for driving address electrodes as claimed in claim 8, wherein said G, K, L, M, N, P, Q and R are 5, 16, 1280, 64, 4, 80 and 4, respectively.

14. The apparatus for driving address electrodes as claimed in claim 8, wherein said G, K, L, M, N, P, Q and R are 10, 8, 1280, 64, 4, 160 and 2, respectively.

15. A method substantially as herein described with reference to or as illustrated in the accompanying drawings.

16. Apparatus constructed and arranged substantially as herein described with reference to or as shown in the accompanying drawings.