EP0078193A1 - Control circuit for an AC plasma panel - Google Patents

Control circuit for an AC plasma panel Download PDF

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Publication number
EP0078193A1
EP0078193A1 EP82401897A EP82401897A EP0078193A1 EP 0078193 A1 EP0078193 A1 EP 0078193A1 EP 82401897 A EP82401897 A EP 82401897A EP 82401897 A EP82401897 A EP 82401897A EP 0078193 A1 EP0078193 A1 EP 0078193A1
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EP
European Patent Office
Prior art keywords
voltage
integrated circuits
circuit
amplifiers
signals
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Application number
EP82401897A
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German (de)
French (fr)
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EP0078193B1 (en
Inventor
Louis Delgrange
Jacques Deschamps
Françoise Vialettes
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Thales SA
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Thomson CSF SA
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/292—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for reset discharge, priming discharge or erase discharge occurring in a phase other than addressing
    • G09G3/2927—Details of initialising
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/293—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for address discharge
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/294—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/297—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels using opposed discharge type panels

Definitions

  • the present invention relates to a control circuit for an alternating type plasma panel.
  • Plasma panels of the alternative type are well known in the prior art, in particular by French patent application No. 78.04893, published under No. 2,417,848, in the name of THOMSON-CSF and by the article published in the "THOMSON-CSF Technical Review", June 1978, volume 10, n ° 2, pages 249 to 275.
  • These panels include a large number of cells arranged in a matrix form. Each cell is formed by the gas space located at the intersection of two electrodes belonging to two networks of orthogonal electrodes and is subjected to control signals constituted by the difference of the voltages applied to the two electrodes between which it is located.
  • control signals mention may be made of the registration signals which cause the cells to ignite, the erasure signals which extinguish the cells and the maintenance signals which keep the cells in their initial state, namely the state off, i.e. the status on.
  • control circuits of alternating type plasma panels which allow the development of the control signals of the panels.
  • plasma panel control circuits comprising a multiplexing network which makes it possible to reduce the number of amplifiers used for the preparation of selective signals, that is to say write and erase signals, which, unlike maintenance signals, must only act on selected cells.
  • This multiplexing network can be achieved by associating with each electrode two diodes and a resistor.
  • the present invention relates to a control circuit for plasma panels of the alternative type which does not have the drawbacks that are encountered on known control circuits.
  • the present invention relates to a circuit for controlling an alternating type plasma panel in which each electrode network is controlled by integrated circuits associated with at least one amplifier.
  • the integrated circuits ensure the preparation of the recording and erasing signals, and the amplifiers ensure the preparation of the maintenance signals.
  • FIG. 1 is a diagram showing the organization of the control circuit according to the invention.
  • This plasma panel comprises two networks of orthogonal electrodes, the electrodes of which bear the references x l to x n and y l to y n .
  • the control circuit according to the invention consists of integrated circuits and amplifiers.
  • the electrodes x to x are controlled by integrated circuits which bear the reference X. These integrated circuits are associated with a single amplifier which bears the reference 2.
  • the integrated circuits X are supplied by DC voltages of values O Volt, 12 Volts and 100 Volts and by a low voltage sloping signal which generally increases from 0 to 12 Volts.
  • these integrated circuits X receive orders in low voltage logic which define the signal to be executed, its duration and the electrodes of the panel to be addressed.
  • electrodes y l to y are controlled by integrated circuits which bear the reference Y.
  • Two amplifiers 3 and 4 are associated with these integrated circuits.
  • the integrated circuits Y are supplied with direct voltages of values O Volt, 12 Volts, + 100 Volts and - 100 Volts.
  • Each integrated circuit X and Y generally makes it possible to control 32 electrodes of the panel.
  • a plasma panel comprising 256 electrodes at x and 256 electrodes at y will have its control circuit made up of 8 integrated circuits X and a single amplifier for controlling the network of electrodes at x, and 8 integrated circuits Y and of two amplifiers for controlling the array of electrodes in y.
  • Figures 2 and 3 are diagrams showing the structure of the integrated circuits X and Y used in the control circuit according to the invention.
  • Each integrated circuit X and Y has three parts: a logic circuit 5, a low voltage / high voltage interface circuit 6 and a network of diodes 8. We will study each of these parts.
  • a logic circuit 5 which receives orders in low voltage logic defining the signal to be executed, its duration and the electrodes of the panel to be addressed.
  • This logic circuit 5 is supplied by a direct voltage of 12 Volts.
  • This interface circuit comprises means symbolized by switches, 1 2 in FIG. 2 and 1 4 in FIG. 3. These means make it possible to carry each electrode of the panel at two different levels, for the integrated circuits X of FIG. 2 which are associated with a single amplifier 2, and at four different levels, for the integrated circuits Y of FIG. 3 which are associated with two amplifiers 3 and 4.
  • each switch 1 2 applies to the electrode at x of the panel to which it is connected, ie a voltage of O Volt, or a high voltage slope signal.
  • this interface circuit is supplied by DC voltages of O Volt, of + 100 Volts and by a low-voltage sloping signal which varies linearly generally between O and + 12 Volts.
  • This slope low voltage signal is amplified by an amplifier 7 which is part of the interface circuit 6 is enabling switches 1 2 applied to the panel electrodes is 0 Volt, a high slope signal voltage which varies linearly, generally, from 0 to 100 Volts.
  • each integrated circuit X with a low-voltage slope signal because this makes it possible to easily adapt the slope of the signal from the outside to the characteristics of the various plasma panels.
  • each switch I 4 applies to the electrode at y of the panel to which it is connected, ie a voltage of O Volt, either a voltage of approximately + 100 Volts, or a voltage of approximately - 100 Volts.
  • each switch 1 4 does not impose any voltage on the electrode at y of the panel to which it is connected and has a high impedance to the network of diodes 8 which follows it.
  • the switches 1 4 are placed in this last position which isolates them from the diode network 8 which follows them on the integrated circuit Y.
  • the interface circuit 6 of FIG. 3 receives supply voltages of O Volt, of substantially + 100 Volts and of substantially - 100 Volts.
  • each output of the interface circuit 6 is connected to two diodes D l and D 2 mounted head to tail.
  • Diode D has its cathode connected to an output of the interface circuit and its anode connected to ground.
  • Diode D 2 has its anode connected to an output of the interface circuit and its cathode connected to the output of amplifier 2.
  • each output of the interface circuit 6 is also connected to two diodes D 3 and D 4 mounted head to tail.
  • Diode D 3 has its cathode connected to an output of the interface circuit and its anode connected to the output of amplifier 3.
  • Diode D 4 has its anode connected to an output of the interface circuit and its cathode connected to the output of amplifier 4.
  • Figures 4a to e relate to the development of maintenance signals.
  • FIG. 4a the voltage of O Volt applied to the electrodes of the front face and which we have called V is shown.
  • FIG. 4b the voltage in square waves applied to the electrodes of the rear face and which has been called V y, is shown .
  • Figure 4c shows the voltage in V - V x y slots applied to each cell of the panel.
  • Maintenance signals do not change the condition of the cells. When a cell is switched off, its memory voltage remains zero when it receives the maintenance signal. When a cell is on, there is an inversion of the memory voltage V M each time the maintenance signal alternates.
  • FIG. 4d represents the discharge current i created by the maintenance signals in the lit cells.
  • This discharge current is in the form of pulses which change sign with each alternation of the maintenance signal.
  • FIG. 4e represents the pulses of light emitted by a cell which is in the on state and which receives the maintenance signal.
  • the control circuit which generates the maintenance signal must supply or accept, according to its direction, the discharge current which is a few tens of micro-amperes per cell lit and this for 0.1 to 0.2 microseconds.
  • Each integrated circuit X in FIG. 2 must maintain the electrodes at x to which it is connected to 0 Volt.
  • each electrode at x is connected to the amplifier 2 via the diode D 2 .
  • the amplifier maintains the voltage of 0 Volt on its output during the alternation of the maintenance signal where the control circuit must accept the discharge current I + .
  • the diode D 2 is forward biased and lets current 1 flow to the amplifier 2. Throughout the duration of the maintenance signal, the low voltage / high voltage interface circuit 6 supplies a voltage of 0 Volt.
  • the diode DIse is polarized in reverse and the current I + cannot therefore cross it.
  • each electrode is connected to the cathode of the diode D 1 whose anode is connected to ground.
  • the amplifier 2 has its equal output or greater than 0 Volt. The discharge current I - flows from the mass to the electrodes through the diodes D 1 and without passing through the diodes D 2 .
  • each integrated circuit Y of FIG. 3 must apply to the electrodes at which it is connected, square-wave voltages of + 100 Volts and - 100 Volts approximately.
  • each electrode at y is connected to the amplifier 4, via the diode D 4 .
  • the output of amplifier 4 is then substantially equal to - 100 Volts and amplifier 4 carries the electrodes to - 100 Volts.
  • the output of the amplifier 3 is also substantially - 100 Volts, so the diode D 3 is in reverse and the current I + cannot pass through it.
  • the low voltage / high voltage interface circuit 6 does not impose any voltage on the electrodes at y.
  • the switches 1 4 are in their fourth position.
  • the discharge current I - which goes from the integrated circuits Y to the electrodes therein is supplied, during one of the alternations of the maintenance signal, by the amplifier 3 via the diode D 3 .
  • the output of amplifier 3 is then substantially + 100 Volts and the amplifier. 3 brings the panel electrodes to + 100 Volts.
  • the output of the amplifier 4 is also substantially + 100 volts, the diode D 4 is reverse biased and the current I - cannot pass through it.
  • control circuit according to the invention allows the generation of the maintenance signals
  • FIGS. 5 and 6a to h After having explained how the control circuit according to the invention allows the generation of the maintenance signals, we will now explain how it allows the generation of the selective signals using FIGS. 5 and 6a to h.
  • FIG. 5 schematically represents four cells C 11 , C 12 ' C 21 and C 22 of a plasma panel. These cells are located at the intersections of two horizontal electrodes x 1 and x 2 , and two vertical electrodes y 1 and y 2 .
  • FIGS. 6a to d represent the voltages V x1 , V x2 , V y1 and V y2 to be applied to the electrodes x 1 , x 2 , y 1 and y 2 so as to maintain the cells C 11 , C 12 , and C 21 in their initial state, and to enter cell C 22 .
  • the voltage V x1 is a zero voltage
  • the voltage V x2 has a voltage ramp which increases from 0 to + 100 Volts stabilizes at 100 Volts then returns to 0.
  • the voltages V y1 and Vy 2 are formed by a series of two or three slots at + or - 100 Volts.
  • FIGS. 6e to h represent the voltages obtained at the terminals of cells C 11 , C 12 ′ C 21 and C 22 .
  • the memory voltage of these cells has been shown in broken lines.
  • the integrated circuit X of FIG. 2 is used.
  • the two positions of the switches I 2 make it possible to obtain a voltage of 0 Volt and a ramp of increasing voltage from 0 to 100 Volts, then stabilizing at 100 Volts if desired.
  • the voltage at the output of amplifier 2 is then fixed at + 100 Volts.
  • the diode D 2 is constantly in reverse and the amplifier 2 does not intervene.
  • the integrated circuit Y of FIG. 3 is used.
  • the switches 1 3 make it possible to obtain voltages of - 100 Volts, + 100 Volts and O Volt.
  • the voltage at the output of amplifier 3 is then fixed at - 100 Volts and the voltage at the output of amplifier 4 is then fixed at + 100 Volts.
  • the diodes D 3 and D 4 are constantly in reverse and amplifiers 3 and 4 do not intervene.
  • the diode networks 8 of the integrated circuits X, Y ensure the non-intervention of the amplifiers 2, 3 and 4 and during the preparation of the signals d 'maintenance, these diode networks ensure the circulation of the maintenance currents I + , I - between the amplifiers and the electrodes, without the other elements of the integrated circuits being used.
  • these amplifiers are generally produced in bipolar technology and have a low output resistance unlike integrated circuits which have a high output resistance.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Ce circuit de commande comporte, pour la commande de l'un des réseaux d'électrodes, des circuits intégrés (X) associés à un seul amplificateur (2) et, pour la commande de l'autre réseau d'électrodes, des circuits intégrés (Y) associés à deux amplificateurs (3, 4). Les circuits intégrés assurent l'élaboration des signaux d'inscription et d'effacement et les amplificateurs l'élaboration des signaux d'entretien.This control circuit comprises, for the control of one of the electrode networks, integrated circuits (X) associated with a single amplifier (2) and, for the control of the other electrode network, integrated circuits (Y) associated with two amplifiers (3, 4). The integrated circuits ensure the creation of the recording and erasing signals and the amplifiers the development of the maintenance signals.

Description

La présente invention concerne un circuit de commande d'un panneau à plasma de type alternatif.The present invention relates to a control circuit for an alternating type plasma panel.

Les panneaux à plasma de type alternatif sont bien connus de l'art antérieur, notamment par la demande de brevet français n° 78.04893, publiée sous le n° 2.417.848, au nom de THOMSON-CSF et par l'article paru dans la "Revue Technique THOMSON-CSF", juin 1978, volume 10, n° 2, pages 249 à 275.Plasma panels of the alternative type are well known in the prior art, in particular by French patent application No. 78.04893, published under No. 2,417,848, in the name of THOMSON-CSF and by the article published in the "THOMSON-CSF Technical Review", June 1978, volume 10, n ° 2, pages 249 to 275.

Ces panneaux comportent un grand nombre de cellules disposées sous forme matricielle. Chaque cellule est constituée par l'espace gazeux situé à l'intersection de deux électrodes appartenant à deux réseaux d'électrodes orthogonaux et se trouve soumise à des signaux de commande constitués par la différence des tensions appliquées aux deux électrodes entre lesquelles elle se trouve.These panels include a large number of cells arranged in a matrix form. Each cell is formed by the gas space located at the intersection of two electrodes belonging to two networks of orthogonal electrodes and is subjected to control signals constituted by the difference of the voltages applied to the two electrodes between which it is located.

Parmi les signaux de commande, on peut citer les signaux d'inscription qui provoquent l'allumage des cellules, les signaux d'effacement qui éteignent les cellules et les signaux d'entretien qui conservent les cellules dans leur état initial, soit l'état éteint, soit l'état allumé.Among the control signals, mention may be made of the registration signals which cause the cells to ignite, the erasure signals which extinguish the cells and the maintenance signals which keep the cells in their initial state, namely the state off, i.e. the status on.

On connait, dans l'art antérieur, des circuits de commande de panneaux à plasma de type alternatif qui permettent l'élaboration des signaux de commande des panneaux. On connait, notamment par l'article déjà cité, des circuits de commande de panneaux à plasma comportant un réseau de multiplexage qui permet de réduire le nombre d'amplificateurs servant à l'élaboration des signaux sélectifs, c'est-à-dire des signaux d'inscription et d'effacement, qui, au contraire des signaux d'entretien, ne doivent agir que sur des cellules sélectionnées.There are known, in the prior art, control circuits of alternating type plasma panels which allow the development of the control signals of the panels. There are known, in particular from the article already cited, plasma panel control circuits comprising a multiplexing network which makes it possible to reduce the number of amplifiers used for the preparation of selective signals, that is to say write and erase signals, which, unlike maintenance signals, must only act on selected cells.

Ce réseau de multiplexage peut être réalisé en associant à chaque électrode deux diodes et une résistance.This multiplexing network can be achieved by associating with each electrode two diodes and a resistor.

Les circuits de commande comportant un réseau de multiplexage présentent les inconvénients suivants :

  • - ils comportent un nombre important d'amplificateurs ou de transistors, de résistances et de condensateurs, ils sont donc encombrants et leur consommation est élevée ;
  • - il est difficile de commander simultanément plusieurs électrodes.
Control circuits comprising a multiplexing network have the following drawbacks:
  • - They include a large number of amplifiers or transistors, resistors and capacitors, so they are bulky and their consumption is high;
  • - it is difficult to control several electrodes simultaneously.

On connait aussi notamment par l'article publié par Texas Instruments, en novembre 1980, Bulletin SCA-204 et intitulé "A.C. Plasma Display", des circuits intégrés en technologie "BIDFET" qui permettent de commander des panneaux à plasma de type alternatif.We also know in particular from the article published by Texas Instruments, in November 1980, Bulletin SCA-204 and entitled "A.C. Plasma Display", integrated circuits in "BIDFET" technology which make it possible to control plasma panels of alternative type.

Ces circuits intégrés comprennent, dans un même boîtier :

  • - un circuit logique qui reçoit des ordres en logique basse tension qui définissent le signal à exécuter, sa-durée et les électrodes du panneau à adresser ;
  • - un circuit d'interface basse tension haute tension qui est commandé par le circuit logique et qui reçoit des tensions continues égales à 0 Volt et 100 Volts. Ce circuit comporte des moyens permettant de porter chaque électrode du panneau à deux niveaux différents 0 Volt et 100 Volts selon l'ordre appliqué au circuit logique.
These integrated circuits include, in a single package:
  • - a logic circuit which receives orders in low voltage logic which define the signal to be executed, its duration and the electrodes of the panel to be addressed;
  • - a low voltage high voltage interface circuit which is controlled by the logic circuit and which receives DC voltages equal to 0 Volts and 100 Volts. This circuit comprises means making it possible to bring each electrode of the panel to two different levels 0 Volt and 100 Volts according to the order applied to the logic circuit.

Ces circuit intégrés présentent l'avantage par rapport aux circuits de commande réalisés en composants discrets :

  • - d'être peu encombrants ;
  • - d'être faciles à adresser, car l'utilisateur donne ses ordres en logique basse tension et applique une tension continue de 100 Volts aux circuits intégrés, au lieu d'être obligé de manipuler des crénaux haute tension ;
  • - de permettre l'adressage simultané d'autant d'électrodes qu'on le veut.
These integrated circuits have the advantage over control circuits made of discrete components:
  • - to be compact;
  • - to be easy to address, because the user gives his orders in low voltage logic and applies a direct voltage of 100 Volts to the integrated circuits, instead of being forced to handle high voltage slots;
  • - allow the simultaneous addressing of as many electrodes as desired.

Par contre, ces circuits intégrés présentent des inconvénients importants :

  • - la technologie utilisée sur les circuits intégrés commercialisés jusqu'à présent limite l'amplitude des signaux de sortie à 100 Volts, alors que les signaux d'entretien sont des tensions en créneaux qui varient ordinairement entre - 100 Volts et + 100 Volts. Il faut alors faire flotter les alimentations des circuits intégrés reliés à l'un des réseaux d'électrodes sur des créneaux de 100 Volts d'amplitude ;
  • - les signaux de commande délivrés par ces circuits sont des créneaux de tensions. Il n'est plus possible d'obtenir des signaux d'effacement et d'inscription comportant une partie en pente comme cela est représenté notamment à la figure 3a et à la figure 4,de la demande de brevet précédemment citée. Or il est très intéressant d'utiliser des signaux d'effacement et d'inscription en pente, car cela permet de réaliser l'effacement et l'inscription sans avoir à effectuer des réglage délicats à cause de la dispersion des caractéristiques des cellules ;
  • - enfin, les amplificateurs de sortie de ces circuits intégrés ont une résistance de sortie R on beaucoup plus élevée (de l'ordre de 100 fois) que celle des amplificateurs en composants discrets. Cela provoque une nette diminution de la luminance des panneaux à plasma et peut même pour les grands panneaux provoquer une perte de l'information inscrite.
However, these integrated circuits have significant drawbacks:
  • - The technology used on the integrated circuits marketed until now limits the amplitude of the output signals to 100 Volts, while the maintenance signals are voltages in slots which ordinarily vary between - 100 Volts and + 100 Volts. It is necessary then float the power supplies of the integrated circuits connected to one of the electrode networks on slots of 100 Volts amplitude;
  • - the control signals delivered by these circuits are voltage slots. It is no longer possible to obtain erasure and registration signals comprising a sloping part as is shown in particular in FIG. 3a and in FIG. 4, of the previously cited patent application. However, it is very advantageous to use erasing and writing signals on a slope, since this makes it possible to carry out erasing and writing without having to make delicate adjustments because of the dispersion of the characteristics of the cells;
  • - Finally, the output amplifiers of these integrated circuits have an output resistance R on much higher (of the order of 100 times) than that of the amplifiers in discrete components. This causes a marked decrease in the luminance of the plasma panels and may even for large panels cause a loss of the information recorded.

La présente invention concerne un circuit de commande de panneaux à plasma de type alternatif qui ne présente pas les inconvénients que l'on rencontre sur les circuits de commande connus.The present invention relates to a control circuit for plasma panels of the alternative type which does not have the drawbacks that are encountered on known control circuits.

La présente invention concerne un circuit de commande d'un panneau à plasma de type alternatif dans lequel chaque réseau d'électrodes est commandé par des circuits intégrés associés à au moins un amplificateur. Selon l'invention, les circuits intégrés assurent l'élaboration des signaux d'inscription et d'effacement, et les amplificateurs assurent l'élaboration des signaux d'entretien.The present invention relates to a circuit for controlling an alternating type plasma panel in which each electrode network is controlled by integrated circuits associated with at least one amplifier. According to the invention, the integrated circuits ensure the preparation of the recording and erasing signals, and the amplifiers ensure the preparation of the maintenance signals.

Le circuit de commande, selon la présente invention, permet de cumuler les avantages des circuits intégrés et des amplificateurs en éléments discrets, en ce qui concerne :

  • - le faible encombrement ;
  • - la facilité d'adressage en logique basse tension, et l'adressage simultané de plusieurs électrodes.
The control circuit, according to the present invention, makes it possible to combine the advantages of integrated circuits and amplifiers in discrete elements, with regard to:
  • - the small footprint;
  • - the ease of addressing in low voltage logic, and the simultaneous addressing of several electrodes.

Le circuit de commande, selon la présente invention, présente, en outre, des avantages particuliers qui sont énumérés ci-dessous :

  • - la consommation du circuit selon l'invention est plus faible que celle d'un circuit de commande n'utilisant que des circuits intégrés, car dans le circuit selon l'invention, seuls les amplificateurs non intégrés sont actifs lors de l'élaboration des signaux d'entretien ;
  • - on utilise, selon l'invention, des circuits intégrés dont l'amplitude des signaux de sortie est de 200 Volts. Il n'est donc plus nécessaire de faire "flotter" les alimentations comme c'est le cas avec les circuits intégrés commercialisés dont l'amplitude des signaux de sortie ne dépasse pas 100 Volts ;
  • - on élabore avec le circuit selon l'invention des signaux d'effacement et d'inscription qui comportent une partie en pente ;
  • - il n'y a pas de perte de luminance, ni de perte d'information dans les panneaux à plasma utilisant le circuit de commande selon Mnvention, bien que la résistance de sortie des amplificateurs des .circuits intégrés utilisés soit élevée. En effet, seuls les amplificateurs non intégrés sont utilisés pour l'élaboration des signaux d'entretien ; ces amplificateurs sont généralement réalisés en technologie bipolaire et présentent une faible résistance de sortie R . A chaque alternance du signal d'entretien, il passe dans chaque cellule allumée un courant de décharge qui inverse la tension de mémoire de la cellule. Il faut que le circuit qui permet l'élaboration des signaux d'entretien puisse fournir ou accepter ce courant de décharge, qui est de quelques dizaines de micro-Ampères par cellule allumée, pendant 0,1 à 0,2 ps, sans que le signal d'entretien soit déformé. Il est donc nécessaire que le circuit qui permet l'élaboration des signaux d'entretien ait une faible résistance de sortie, c'est ce qui se passe dans le circuit de commande selon l'invention. Lors de l'élaboration des signaux d'inscription ou d'effacement, il n'y a pas ou presque de courant de décharge. Ces signaux peuvent donc être sans inconvénients élaborés par des circuits intégrés à résistance de sortie élevée.
The control circuit according to the present invention has, in addition, special benefits which are listed below:
  • the consumption of the circuit according to the invention is lower than that of a control circuit using only integrated circuits, because in the circuit according to the invention, only the non-integrated amplifiers are active during the development of the maintenance signals;
  • - Using the invention, integrated circuits whose amplitude of the output signals is 200 Volts. It is therefore no longer necessary to "float" the power supplies as is the case with commercial integrated circuits whose amplitude of the output signals does not exceed 100 Volts;
  • - Erasing and writing signals are developed with the circuit according to the invention which include a sloping part;
  • - There is no loss of luminance, nor loss of information in the plasma panels using the control circuit according to Mnvention, although the output resistance of the amplifiers of the integrated circuits used is high. In fact, only the non-integrated amplifiers are used for the preparation of the maintenance signals; these amplifiers are generally produced in bipolar technology and have a low output resistance R. Each time the maintenance signal alternates, a discharge current flows through each cell that reverses the memory voltage of the cell. It is necessary that the circuit which allows the development of the maintenance signals can supply or accept this discharge current, which is a few tens of micro-amperes per lit cell, for 0.1 to 0.2 ps, without the maintenance signal is distorted. It is therefore necessary that the circuit which allows the generation of the maintenance signals has a low output resistance, this is what happens in the control circuit according to the invention. During the generation of the recording or erasing signals, there is almost no discharge current. These signals can therefore be without drawbacks produced by integrated circuits with high output resistance.

D'autres objets, caractéristiques et résultats de l'invention ressortiront de la description suivante donnée à titre d'exemple non limitatif et illustrée par les figures annexées qui représentent :

  • - la figure 1, un schéma montrant l'organisation du circuit de commande selon l'invention ;
  • - les figures 2 et 3, des schémas montrant la structure des circuits intégrés utilisés dans le circuit de commande selon l'invention ;
  • - les figures 4a et b, les tensions permettant l'élaboration des signaux d'entretien, la figure 4c, la tension d'entretien, et les figures 4d et e, le courant de décharge dans les cellules et les impulsions de lumière émises par les cellules ;
  • - les figures 5 et 6 a à h, la représentation schématique de quelques cellules d'un panneau à plasma, des tensions élaborées par le circuit de commande selon l'invention et les signaux de commande reçus par les cellules.
Other objects, characteristics and results of the invention The following description will be given by way of nonlimiting example and illustrated by the appended figures which represent:
  • - Figure 1, a diagram showing the organization of the control circuit according to the invention;
  • - Figures 2 and 3, diagrams showing the structure of the integrated circuits used in the control circuit according to the invention;
  • - Figures 4a and b, the voltages allowing the development of the maintenance signals, Figure 4c, the maintenance voltage, and Figures 4d and e, the discharge current in the cells and the light pulses emitted by cells ;
  • - Figures 5 and 6 a to h, the schematic representation of some cells of a plasma panel, voltages developed by the control circuit according to the invention and the control signals received by the cells.

Sur les différentes figures, les mêmes repères désignent les mêmes éléments, mais, pour des raisons de clarté, les cotes et proportions des divers éléments ne sont pas respectées.In the different figures, the same references designate the same elements, but, for reasons of clarity, the dimensions and proportions of the various elements are not observed.

La figure 1 est un schéma montrant l'organisation du circuit de commande selon l'invention.FIG. 1 is a diagram showing the organization of the control circuit according to the invention.

Sur cette figure, on a représenté un panneau à plasma qui porte la référence 1. Ce panneau à plasma comporte deux réseaux d'électrodes orthogonaux, dont les électrodes portent les références xl à xn et ylà yn.In this figure, a plasma panel is shown which bears the reference 1. This plasma panel comprises two networks of orthogonal electrodes, the electrodes of which bear the references x l to x n and y l to y n .

Le circuit de commande selon l'invention est constitué de circuits intégrés et d'amplificateurs.The control circuit according to the invention consists of integrated circuits and amplifiers.

Les électrodes x à x sont commandées par des circuits intégrés qui portent la référence X. Ces circuits intégrés sont associés à un seul amplificateur qui porte la référence 2.The electrodes x to x are controlled by integrated circuits which bear the reference X. These integrated circuits are associated with a single amplifier which bears the reference 2.

Les circuits intégrés X sont alimentés par des tensions continues de valeurs O Volt, 12 Volts et 100 Volts et par un signal en pente basse tension qui croît généralement de 0 à 12 Volts.The integrated circuits X are supplied by DC voltages of values O Volt, 12 Volts and 100 Volts and by a low voltage sloping signal which generally increases from 0 to 12 Volts.

D'autres part, ces circuits intégrés X reçoivent des ordres en logique basse tension qui définissent le signal à exécuter, sa durée et les électrodes du panneau à adresser.On the other hand, these integrated circuits X receive orders in low voltage logic which define the signal to be executed, its duration and the electrodes of the panel to be addressed.

En ce qui concerne les électrodes yl à y , elles sont commandées par des circuits intégrés qui portent la référence Y.As regards the electrodes y l to y, they are controlled by integrated circuits which bear the reference Y.

Deux amplificateurs 3 et 4 sont associés à ces circuits intégrés.Two amplifiers 3 and 4 are associated with these integrated circuits.

Les circuits intégrés Y sont alimentés par des tensions continues de valeurs O Volt, 12 Volts, + 100 Volts et - 100 Volts.The integrated circuits Y are supplied with direct voltages of values O Volt, 12 Volts, + 100 Volts and - 100 Volts.

Ils reçoivent comme les circuits intégrés X des ordres en logique basse tension.Like the integrated circuits X, they receive orders in low voltage logic.

Chaque circuit intégré X et Y permet généralement de commander 32 électrodes du panneau.Each integrated circuit X and Y generally makes it possible to control 32 electrodes of the panel.

Un panneau à plasma comportant 256 électrodes en x et 256 électrodes en y, aura son circuit de commande constitué de 8 circuits intégrés X et d'un seul amplificateur pour la commande du réseau d'électrodes en x, et de 8 circuits intégrés Y et de deux amplificateurs pour la commande du réseau d'électrodes en y.A plasma panel comprising 256 electrodes at x and 256 electrodes at y will have its control circuit made up of 8 integrated circuits X and a single amplifier for controlling the network of electrodes at x, and 8 integrated circuits Y and of two amplifiers for controlling the array of electrodes in y.

Les figures 2 et 3 sont des schémas montrant la structure des circuits intégrés X et Y utilisés dans le circuit de commande selon l'invention.Figures 2 and 3 are diagrams showing the structure of the integrated circuits X and Y used in the control circuit according to the invention.

Chaque circuit intégrés X et Y comporte trois parties : un_ circuit logique 5, un circuit d'interface basse tension/haute tension 6 et un réseau de diodes 8. On va étudier chacune de ces parties.Each integrated circuit X and Y has three parts: a logic circuit 5, a low voltage / high voltage interface circuit 6 and a network of diodes 8. We will study each of these parts.

On trouve d'abord un circuit logique 5 qui reçoit des ordres en logique basse tension définissant le signal à exécuter, sa durée et les électrodes du panneau à adresser. Ce circuit logique 5 est alimenté par une tension continue de 12 Volts.First there is a logic circuit 5 which receives orders in low voltage logic defining the signal to be executed, its duration and the electrodes of the panel to be addressed. This logic circuit 5 is supplied by a direct voltage of 12 Volts.

On trouve ensuite un circuit d'interface basse tension/haute tension 6 qui est commandé par le circuit logique 5.There is then a low voltage / high voltage interface circuit 6 which is controlled by the logic circuit 5.

Ce circuit d'interface comporte des moyens symbolisés par des interrupteurs, 12 sur la figure 2 et 14 sur la figure 3. Ces moyens permettent de porter chaque électrode du panneau à deux niveaux différents, pour les circuits intégrés X de la figure 2 qui sont associés à un seul amplificateur 2, et à quatre niveaux différents, pour les circuits intégrés Y de la figure 3 qui sont associés à deux amplificateurs 3 et 4.This interface circuit comprises means symbolized by switches, 1 2 in FIG. 2 and 1 4 in FIG. 3. These means make it possible to carry each electrode of the panel at two different levels, for the integrated circuits X of FIG. 2 which are associated with a single amplifier 2, and at four different levels, for the integrated circuits Y of FIG. 3 which are associated with two amplifiers 3 and 4.

Selon l'ordre appliqué au circuit logique 5 de la figure 2, cet ordre étant transmis par une électrode de commande C, chaque interrupteur 12 applique à l'électrode en x du panneau à laquelle il est relié soit une tension de O Volt, soit un signal en pente haute tension.According to the order applied to the logic circuit 5 of FIG. 2, this order being transmitted by a control electrode C, each switch 1 2 applies to the electrode at x of the panel to which it is connected, ie a voltage of O Volt, or a high voltage slope signal.

Il faut préciser que ce circuit d'interface est alimenté par des tensions continues de O Volt, de + 100 Volts et par un signal en pente basse tension qui varie linéairement généralement entre O et + 12 Volts. Ce signal en pente basse tension est amplifié par un amplificateur 7 qui fait partie du circuit d'interface 6, c'est ce qui permet aux interrupteurs 12 d'appliquer aux électrodes du panneau soit du 0 Volt, soit un signal en pente haute tension qui varie linéairement, généralement, de O à 100 Volts.It should be specified that this interface circuit is supplied by DC voltages of O Volt, of + 100 Volts and by a low-voltage sloping signal which varies linearly generally between O and + 12 Volts. This slope low voltage signal is amplified by an amplifier 7 which is part of the interface circuit 6 is enabling switches 1 2 applied to the panel electrodes is 0 Volt, a high slope signal voltage which varies linearly, generally, from 0 to 100 Volts.

Il est intéressant d'alimenter chaque circuit intégré X par un signal en pente basse tension car cela permet d'adapter, aisément, de l'extérieur, la pente du signal aux caractéristiques des différents panneaux à plasma.It is advantageous to supply each integrated circuit X with a low-voltage slope signal because this makes it possible to easily adapt the slope of the signal from the outside to the characteristics of the various plasma panels.

De même, selon l'ordre appliqué au circuit logique 5 de la figure 3, cet ordre étant transmis par une électrode de commande C, chaque interrupteur I4 applique à l'électrode en y du panneau à laquelle il est relié soit une tension de O Volt, soit une tension de sensiblement + 100 Volts, soit une tension de sensiblement - 100 Volts. Il existe enfin une quatrième position de chaque interrupteur 14, dans laquelle chaque interrupteur 14 n'impose aucune tension à l'électrode en y du panneau à laquelle il est relié et présente une haute impédance au réseau de diodes 8 qui le suit. Pendant l'élaboration des signaux d'entretien, les interrupteurs 14 sont placés dans cette dernière position qui les isole du réseau de diodes 8 qui les suit sur le circuit intégré Y.Similarly, according to the order applied to the logic circuit 5 of FIG. 3, this order being transmitted by a control electrode C, each switch I 4 applies to the electrode at y of the panel to which it is connected, ie a voltage of O Volt, either a voltage of approximately + 100 Volts, or a voltage of approximately - 100 Volts. Finally, there is a fourth position of each switch 1 4 , in which each switch 1 4 does not impose any voltage on the electrode at y of the panel to which it is connected and has a high impedance to the network of diodes 8 which follows it. During the development of the maintenance signals, the switches 1 4 are placed in this last position which isolates them from the diode network 8 which follows them on the integrated circuit Y.

Le circuit d'interface 6 de la figure 3 reçoit des tensions d'alimentation de O Volt, de sensiblement + 100 Volts et de sensiblement - 100 Volts.The interface circuit 6 of FIG. 3 receives supply voltages of O Volt, of substantially + 100 Volts and of substantially - 100 Volts.

A la suite du circuit d'interface basse tension/haute tension 6, on trouve sur les circuits intégrés X et Y des figures 2 et 3, un réseau de diodes 8 qui assure la liaison entre, d'une part, les sorties du circuit d'interface basse tension/haute tension 6 et, d'autre part, les sorties des amplificateurs 2, 3 et 4 et les électrodes du panneau.Following the low voltage / high voltage interface circuit 6, on the integrated circuits X and Y of FIGS. 2 and 3, there is a network of diodes 8 which provides the connection between, on the one hand, the outputs of the low voltage / high voltage interface circuit 6 and, on the other hand , the outputs of amplifiers 2, 3 and 4 and the panel electrodes.

Sur la figure 2, on constate que chaque sortie du circuit d'interface 6 est reliée à deux diodes Dl et D2 montées tête-bêche.In Figure 2, we see that each output of the interface circuit 6 is connected to two diodes D l and D 2 mounted head to tail.

La diode D, a sa cathode reliée à une sortie du circuit d'interface et son anode reliée à la masse. La diode D2 a son anode reliée à une sortie du circuit d'interface et sa cathode reliée à la sortie de l'amplificateur 2.Diode D has its cathode connected to an output of the interface circuit and its anode connected to ground. Diode D 2 has its anode connected to an output of the interface circuit and its cathode connected to the output of amplifier 2.

Sur la figure 3 également, on constate que chaque sortie du circuit d'interface 6 est également reliée à deux diodes D3 et D4 montées tête-bêche.Also in FIG. 3, it can be seen that each output of the interface circuit 6 is also connected to two diodes D 3 and D 4 mounted head to tail.

La diode D3 a sa cathode reliée à une sortie du circuit d'interface et son anode reliée à la sortie de l'amplificateur 3. La diode D4 a son anode reliée à une sortie du circuit d'interface et sa cathode reliée à la sortie de l'amplificateur 4.Diode D 3 has its cathode connected to an output of the interface circuit and its anode connected to the output of amplifier 3. Diode D 4 has its anode connected to an output of the interface circuit and its cathode connected to the output of amplifier 4.

Après avoir décrit la structure du circuit de commande selon l'invention, on va maintenant expliquer son fonctionnement.After describing the structure of the control circuit according to the invention, we will now explain its operation.

On va notamment expliquer ce fonctionnement à l'aide des figures 4a à e.We will in particular explain this operation using FIGS. 4a to e.

Les figures 4a à e concernent l'élaboration des signaux d'entretien.Figures 4a to e relate to the development of maintenance signals.

On sait notamment réaliser les signaux d'entretien en maintenant les électrodes de la face avant du panneau à O Volt et en appliquant une tension en créneaux de + 100 Volts et -100 Volts environ aux électrodes de la face arrière du panneau.It is known in particular to carry out the maintenance signals by maintaining the electrodes of the front face of the panel at 0 Volt and by applying a voltage in slots of + 100 Volts and -100 Volts approximately to the electrodes of the rear face of the panel.

Sur la figure 4a, on a représenté la tension de O Volt appliquée aux électrodes de la face avant et que l'on a appelée V . Sur la figure 4b, on a représenté la tension en créneaux appliquée aux électrodes de la face arrière et que l'on a appelée Vy.In FIG. 4a, the voltage of O Volt applied to the electrodes of the front face and which we have called V is shown. In FIG. 4b, the voltage in square waves applied to the electrodes of the rear face and which has been called V y, is shown .

La figure 4c, représente la tension en créneaux V - V x y appliquée à chaque cellule du panneau.Figure 4c shows the voltage in V - V x y slots applied to each cell of the panel.

En trait discontinu, on a représenté sur la figure 4c la tension de mémoire VM aux bornes de chaque cellule.In broken lines, the voltage is shown in FIG. 4c. of memory V M at the terminals of each cell.

Les signaux d'entretien ne modifient pas l'état des cellules. Lorsqu'une cellule est éteinte, sa tension de mémoire reste nulle lorsqu'elle reçoit le signal d'entretien. Lorsqu'une cellule est allumée, il y a inversion de la tension de mémoire VM à chaque alternance du signal d'entretien.Maintenance signals do not change the condition of the cells. When a cell is switched off, its memory voltage remains zero when it receives the maintenance signal. When a cell is on, there is an inversion of the memory voltage V M each time the maintenance signal alternates.

La figure 4d représente le courant de décharge i créé par les signaux d'entretien dans les cellules allumées.FIG. 4d represents the discharge current i created by the maintenance signals in the lit cells.

Ce courant de décharge se présente sous la forme d'impulsions qui changent de signe à chaque alternance du signal d'entretien.This discharge current is in the form of pulses which change sign with each alternation of the maintenance signal.

La figure 4e représente les impulsions de lumière émises par une cellule se trouvant à l'état allumée et qui reçoit le signal d'entretien.FIG. 4e represents the pulses of light emitted by a cell which is in the on state and which receives the maintenance signal.

Le circuit de commande qui élabore le signal d'entretien doit fournir ou accepter, selon son sens, le courant de décharge qui est de quelques dizaines de micro-Ampères par cellule allumée et cela pendant 0,1 à 0,2 microsecondes.The control circuit which generates the maintenance signal must supply or accept, according to its direction, the discharge current which is a few tens of micro-amperes per cell lit and this for 0.1 to 0.2 microseconds.

Chaque circuit intégré X de la figure 2 doit maintenir les électrodes en x auquelles il est relié à 0 Volt.Each integrated circuit X in FIG. 2 must maintain the electrodes at x to which it is connected to 0 Volt.

Pour accepter le courant de décharge I+ qui va des électrodes x vers les circuits intégrés X, chaque électrode en x est reliée à l'amplificateur 2 par l'intermédiaire de la diode D2. L'amplificateur maintient la tension de 0 Volt sur sa sortie pendant l'alternance du signal d'entretien où le circuit de commande doit accepter le courant de décharge I+. La diode D2 est polarisée en direct et laisse passer le courant 1 vers l'amplificateur 2. Pendant toute la durée du signal d'entretien, le circuit d'interface basse tension/haute tension 6 fournit une tension de 0 Volt. La diode DIse trouve polarisée en inverse et le courant I+ ne peut donc la traverser.To accept the discharge current I + which goes from the electrodes x to the integrated circuits X, each electrode at x is connected to the amplifier 2 via the diode D 2 . The amplifier maintains the voltage of 0 Volt on its output during the alternation of the maintenance signal where the control circuit must accept the discharge current I + . The diode D 2 is forward biased and lets current 1 flow to the amplifier 2. Throughout the duration of the maintenance signal, the low voltage / high voltage interface circuit 6 supplies a voltage of 0 Volt. The diode DIse is polarized in reverse and the current I + cannot therefore cross it.

Pour fournir le courant de décharge I- qui va des circuits intégrés X vers les électrodes en x, chaque électrode est reliée à la cathode de la diode D1 dont l'anode est reliée à la masse. Pendant l'alternance du signal d'entretien où le circuit de commande doit fournir le courant de décharge I-, l'amplificateur 2 a sa sortie égale ou supérieure à 0 Volt. Le courant de décharge I- circule de la masse vers les électrodes à travers les diodes D1 et sans traverser les diodes D2.To supply the discharge current I - which goes from the integrated circuits X to the electrodes at x, each electrode is connected to the cathode of the diode D 1 whose anode is connected to ground. During the alternation of the maintenance signal where the control circuit must supply the discharge current I - , the amplifier 2 has its equal output or greater than 0 Volt. The discharge current I - flows from the mass to the electrodes through the diodes D 1 and without passing through the diodes D 2 .

Pour imposer la tension de 0 Volt sur les électrodes en x du panneau et fournir ou accepter les courants de décharge, on est conduit à utiliser un amplificateur. En effet, si on disposait deux diodes tête-bêche connectées à la masse à chaque sortie du circuit d'interface, on court-circuiterait tous les signaux de sortie du circuit d'interface.To impose the voltage of 0 Volt on the x electrodes of the panel and supply or accept the discharge currents, one is led to use an amplifier. Indeed, if we had two head-to-tail diodes connected to ground at each output of the interface circuit, we would short-circuit all the output signals of the interface circuit.

Pour l'élaboration des signaux d'entretien, chaque circuit intégré Y de la figure 3 doit appliquer aux électrodes en y auxquelles il est relié des tensions en créneaux de + 100 Volts et - 100 Volts environ.For the development of the maintenance signals, each integrated circuit Y of FIG. 3 must apply to the electrodes at which it is connected, square-wave voltages of + 100 Volts and - 100 Volts approximately.

Pour accepter le courant de décharge I+ qui va des électrodes en y vers les circuits intégrés Y pendant l'une des alternances du signal d'entretien, chaque électrode en y est reliée à l'amplificateur 4, par l'intermédiaire de la diode D4. La sortie de l'amplificateur 4 est, alors égale à sensiblement - 100 Volts et l'amplificateur 4 porte les électrodes à - 100 Volts.To accept the discharge current I + which goes from the electrodes at y to the integrated circuits Y during one of the alternations of the maintenance signal, each electrode at y is connected to the amplifier 4, via the diode D 4 . The output of amplifier 4 is then substantially equal to - 100 Volts and amplifier 4 carries the electrodes to - 100 Volts.

Pendant cette alternance du signal d'entretien, la sortie de l'amplificateur 3 est également de sensiblement - 100 Volts, ainsi la diode D3 est en inverse et le courant I+ ne peut la traverser. Pendant toute la durée du signal d'entretien, le circuit d'interface basse tension/haute tension 6 n'impose aucune tension aux électrodes en y. Les interrupteurs 14 sont dans leur quatrième position.During this alternation of the maintenance signal, the output of the amplifier 3 is also substantially - 100 Volts, so the diode D 3 is in reverse and the current I + cannot pass through it. During the entire duration of the maintenance signal, the low voltage / high voltage interface circuit 6 does not impose any voltage on the electrodes at y. The switches 1 4 are in their fourth position.

Le courant de décharge I- qui va des circuits intégrés Y vers les électrodes en y est fourni, pendant l'une des alternances du signal d'entretien, par l'amplificateur 3 par l'intermédiaire de la diode D3. La sortie de l'amplificateur 3 est alors de sensiblement + 100 Volts et l'amplificateur. 3 porte les électrodes du panneau à + 100 Volts.The discharge current I - which goes from the integrated circuits Y to the electrodes therein is supplied, during one of the alternations of the maintenance signal, by the amplifier 3 via the diode D 3 . The output of amplifier 3 is then substantially + 100 Volts and the amplifier. 3 brings the panel electrodes to + 100 Volts.

Pendant cette alternance du signal d'entretien, la sortie de l'amplificateur 4 est aussi de sensiblement + 100 Volts, la diode D4 se trouve polarisée en inverse et le courant I- ne peut la traverser.During this alternation of the maintenance signal, the output of the amplifier 4 is also substantially + 100 volts, the diode D 4 is reverse biased and the current I - cannot pass through it.

Après avoir expliqué comment le circuit de commande selon l'invention permet l'élaboration des signaux d'entretien, on va maintenant expliquer comment il permet l'élaboration des signaux sélectifs à l'aide des figures 5 et 6a à h.After having explained how the control circuit according to the invention allows the generation of the maintenance signals, we will now explain how it allows the generation of the selective signals using FIGS. 5 and 6a to h.

La figure 5 représente de façon schématique quatre cellules C11, C 12' C 21 et C22 d'un panneau à plasma. Ces cellules sont situées aux intersections de deux électrodes horizontales x1 et x2, et de deux électrodes verticales y1 et y2.FIG. 5 schematically represents four cells C 11 , C 12 ' C 21 and C 22 of a plasma panel. These cells are located at the intersections of two horizontal electrodes x 1 and x 2 , and two vertical electrodes y 1 and y 2 .

Les figures 6a à d représentent les tensions Vx1, Vx2, Vy1 et Vy2 à appliquer aux électrodes x1, x2, y1 et y2 de façon à entretenir les cellules C11, C12, et C21 dans leur état initial, et à inscrire la cellule C22.FIGS. 6a to d represent the voltages V x1 , V x2 , V y1 and V y2 to be applied to the electrodes x 1 , x 2 , y 1 and y 2 so as to maintain the cells C 11 , C 12 , and C 21 in their initial state, and to enter cell C 22 .

On remarque sur la figure 6a que la tension Vx1 est une tension nulle, on remarque sur la figure 6b que la tension Vx2 comporte une rampe de tension qui croît de 0 à + 100 Volts se stabilise à 100 Volts puis revient à 0.It is noted in FIG. 6a that the voltage V x1 is a zero voltage, it is noted in FIG. 6b that the voltage V x2 has a voltage ramp which increases from 0 to + 100 Volts stabilizes at 100 Volts then returns to 0.

Les tensions Vy1 et Vy2 sont constituées par une suite de deux ou trois créneaux à + ou - 100 Volts.The voltages V y1 and Vy 2 are formed by a series of two or three slots at + or - 100 Volts.

Les figures 6e à h représentent les tensions obtenues aux bornes des cellules C11, C12' C21 et C22. On a représenté en trait discontinu la tension de mémoire de ces cellules.FIGS. 6e to h represent the voltages obtained at the terminals of cells C 11 , C 12 ′ C 21 and C 22 . The memory voltage of these cells has been shown in broken lines.

Pour élaborer les tensions Vx1 et Vx2, on utilise le circuit intégré X de la figure 2. Les deux positions des interrupteurs I2 permettent d'obtenir une tension de 0 Volt et une rampe de tension croissant de 0 à 100 Volts, puis se stabilisant à 100 Volts si on le désire. La tension en sortie de l'amplificateur 2 est alors fixée à + 100 Volts. Lors de l'élaboration des signaux sélectifs, la diode D2 est constamment en inverse et l'amplificateur 2 n'intervient pas.To develop the voltages V x1 and V x2 , the integrated circuit X of FIG. 2 is used. The two positions of the switches I 2 make it possible to obtain a voltage of 0 Volt and a ramp of increasing voltage from 0 to 100 Volts, then stabilizing at 100 Volts if desired. The voltage at the output of amplifier 2 is then fixed at + 100 Volts. During the preparation of the selective signals, the diode D 2 is constantly in reverse and the amplifier 2 does not intervene.

Pour élaborer les tensions Vy1 et Vy2, on utilise le circuit intégré Y de la figure 3. Les interrupteurs 13 permettent d'obtenir des tensions de - 100 Volts, + 100 Volts et O Volt. La tension en sortie de l'amplificateur 3 est alors fixée à - 100 Volts et la tension en sortie de l'amplificateur 4 est alors fixée à + 100 Volts. Ainsi, lors de l'élaboration des signaux sélectifs, les diodes D3 et D4 sont constamment en inverse et les amplificateurs 3 et 4 n'interviennent pas.To develop the voltages V y1 and V y2 , the integrated circuit Y of FIG. 3 is used. The switches 1 3 make it possible to obtain voltages of - 100 Volts, + 100 Volts and O Volt. The voltage at the output of amplifier 3 is then fixed at - 100 Volts and the voltage at the output of amplifier 4 is then fixed at + 100 Volts. Thus, during the preparation of the selective signals, the diodes D 3 and D 4 are constantly in reverse and amplifiers 3 and 4 do not intervene.

On constate donc que lors de l'élaboration des signaux d'inscription et d'effacement les réseaux de diodes 8 des circuits intégrés X, Y assurent la non-intervention des amplificateurs 2, 3 et 4 et lors de l'élaboration des signaux d'entretien, ces réseaux de diodes assurent la circulation des courants d'entretien I+, I- entre les amplificateurs et les électrodes, sans que les autres éléments des circuits intégrés soient utilisés. Lors de l'élaboration des signaux d'entretien, seuls les amplificateurs non-intégrés sont utilisés. Or l'on sait que ces amplificateurs sont généralement réalisés en technologie bipolaire et présentent une faible résistance de sortie au contraire des circuits intégrés qui présentent une résistance de sortie élevée.It can therefore be seen that during the preparation of the recording and erasing signals the diode networks 8 of the integrated circuits X, Y ensure the non-intervention of the amplifiers 2, 3 and 4 and during the preparation of the signals d 'maintenance, these diode networks ensure the circulation of the maintenance currents I + , I - between the amplifiers and the electrodes, without the other elements of the integrated circuits being used. When developing maintenance signals, only non-integrated amplifiers are used. However, it is known that these amplifiers are generally produced in bipolar technology and have a low output resistance unlike integrated circuits which have a high output resistance.

Il n'y aura donc pas déformation des signaux d'entretien.There will therefore be no distortion of the maintenance signals.

Dans la description précédente on a donné les valeurs, égales à sensiblement + 100 Volts, - 100 volts et 0 Volt, des tensions qui sont couramment utilisées. Il est bien entendu que l'invention s'applique également aux cas où les tensions utilisées ont des valeurs différentes et où l'on prend pour les deux hautes tensions continues utilisées qui sont généralement égales à - 100 Volts et + 100 Volts des valeurs V et V 2 quelconques, avec V27>V1 et où l'on prend pour la haute tension continue intermédiaire entre les deux hautes tensions continues utilisées pour la commande du panneau une valeur V 0, avec V2> Y0>V1, alors que cette tension intermédiaire est généralement égale à 0 Volt. On peut remarquer qu'il est pratique d'avoir une tension intermédiaire V 0 égale à 0 Volt.In the preceding description, the values, substantially equal to + 100 volts, - 100 volts and 0 volts, of the voltages which are commonly used have been given. It is understood that the invention also applies to cases where the voltages used have different values and where we take for the two high DC voltages used which are generally equal to - 100 Volts and + 100 Volts values V and V 2 any, with V 27 > V 1 and where we take for the DC high intermediate voltage between the two DC high voltages used for the control of the panel a value V 0 , with V 2 > Y 0 > V 1 , while this intermediate voltage is generally equal to 0 Volt. We can notice that it is practical to have an intermediate voltage V 0 equal to 0 Volt.

Claims (11)

1. Circuit de commande d'un panneau à plasma de type alternatif, ce circuit assurant l'élaboration des signaux d'entretien, d'inscription et d'effacement du panneau, ces signaux étant appliqués entre deux électrodes appartenant à deux réseaux d'électrodes orthogonaux, caractérisé en ce que chaque réseau d'électrodes est commandé par des circuits intégrés (X, Y) associés à au moins un amplificateur (2, 3, 4), les circuits intégrés assurant l'élaboration des signaux d'inscription et d'effacement, et les amplificateurs assurant l'élaboration des signaux d'entretien.1. Control circuit of an alternative type plasma panel, this circuit ensuring the development of the maintenance, recording and erasing signals of the panel, these signals being applied between two electrodes belonging to two networks of orthogonal electrodes, characterized in that each electrode network is controlled by integrated circuits (X, Y) associated with at least one amplifier (2, 3, 4), the integrated circuits ensuring the generation of the recording signals and and the amplifiers ensuring the development of the maintenance signals. 2. Circuit selon la revendication 1, caractérisé en ce que chaque circuit intégré (X, Y) comporte un réseau de diodes (8), et en ce que, lors de l'élaboration des signaux d'inscription et d'effacement, ces réseaux de diodes assurent la non-intervention des amplificateurs (2, 3, 4), et lors de l'élaboration des signaux d'entretien, ces réseaux de diodes assurent la circulation des courants d'entretien (I+, I-) entre les amplificateurs et les électrodes sans que les autres éléments des circuits intégrés soient utilisés.2. Circuit according to claim 1, characterized in that each integrated circuit (X, Y) comprises an array of diodes (8), and in that, during the preparation of the recording and erasing signals, these diode networks ensure the non-intervention of amplifiers (2, 3, 4), and during the preparation of maintenance signals, these diode networks ensure the circulation of maintenance currents (I + , I - ) between amplifiers and electrodes without the other elements of integrated circuits being used. 3.Circuit selon l'une des revendications 1 ou 2, caractérisé en ce que l'un des réseaux d'électrodes est commandé par des circuits intégrés (X) associés à un seul amplificateur (2), et en ce que l'autre réseau d'électrodes est commandé par des circuits intégrés (Y) associés à deux amplificateurs (3, 4).3.Circuit according to one of claims 1 or 2, characterized in that one of the electrode networks is controlled by integrated circuits (X) associated with a single amplifier (2), and in that the other network of electrodes is controlled by integrated circuits (Y) associated with two amplifiers (3, 4). 4. Circuit selon l'une des revendications 1 à 3, caractérisé en ce que chaque circuit intégré comporte : - un circuit logique (5) recevant des ordres en logique basse tension définissant le signal à exécuter, sa durée et les électrodes du panneau à adresser ; - un circuit d'interface basse-tension/haute tension (6) qui est commandé par le circuit logique et qui comporte des moyens (I2, 14) permettant de porter chaque électrode du panneau à des niveaux différents ; - un réseau de diodes (8) assurant la liaison entre les sorties du circuit d'interface basse tension/haute tension d'une part, et, les sorties des amplificateurs et les électrodes du panneau, d'autre part. 4. Circuit according to one of claims 1 to 3, characterized in that each integrated circuit comprises: - a logic circuit (5) receiving orders in low voltage logic defining the signal to be executed, its duration and the electrodes of the panel to be addressed; - a low-voltage / high-voltage interface circuit (6) which is controlled by the logic circuit and which comprises means (I 2 , 1 4 ) making it possible to bring each electrode of the panel to different levels; - a network of diodes (8) ensuring the connection between the outputs of the low voltage / high voltage interface circuit on the one hand, and the outputs of the amplifiers and the panel electrodes on the other. 5. Circuit selon les revendications 3 et 4, caractérisé, en ce qui concerne les circuits intégrés (X) associés à un seul amplificateur (2), par le fait que : - le circuit d'interface (6) de ces circuits intégrés (X) est alimenté par un signal en pente basse tension, une haute tension continue (V 2) et une tension continue (Y0) intermédiaire entre les valeurs des deux hautes tensions continues (V et V2) utilisées pour la commande du panneau, et en ce que les moyens (I2) permettent d'appliquer aux électrodes reliées à ces circuits intégrés (X) soit la tension continue intermédiaire (V0), soit un signal en pente haute tension, selon l'ordre appliqué au circuit logique. 5. Circuit according to claims 3 and 4, characterized, with regard to the integrated circuits (X) associated with a single amplifier (2), in that: - the interface circuit (6) of these integrated circuits (X) is supplied by a low voltage sloping signal, a high direct voltage (V 2 ) and a direct voltage (Y 0 ) intermediate between the values of the two high voltages DC (V and V 2 ) used for the control of the panel, and in that the means (I 2 ) make it possible to apply to the electrodes connected to these integrated circuits (X) either the DC intermediate voltage (V 0 ), or a high voltage slope signal, in the order applied to the logic circuit. 6. Circuit selon les revendications 3 et 4 ou selon la revendication 5, caractérisé, en ce qui concerne les circuits intégrés (Y) associés à deux amplificateurs (3, 4), par le fait que : - le circuit d'interface (6) de ces circuits intégrés (Y) est aimenté par deux hautes tensions continues (V1, V2) et par une tension continue (V0) intermédiaire entre les valeurs des deux hautes tensions continues (V et V2) utilisées pour la commande du panneau, et en ce que les moyens (14) permettent d'appliquer aux electrodes reliées à ces circuits intégrés (Y) soit la tension continue intermédiaire (V0), soit l'une ou l'autre des deux hautes tensions continues (V1 et V2), ces moyens (I4) permettant également d'isoler le circuit d'interface (6) du réseau de diodes (8) qui le suit sur le circuit intégré (Y). 6. Circuit according to claims 3 and 4 or according to claim 5, characterized, with regard to the integrated circuits (Y) associated with two amplifiers (3, 4), in that: - the interface circuit (6) of these integrated circuits (Y) is magnetized by two high continuous voltages (V 1 , V 2 ) and by a direct voltage (V 0 ) intermediate between the values of the two high continuous voltages (V and V 2 ) used for the control of the panel, and in that the means (1 4 ) make it possible to apply to the electrodes connected to these integrated circuits (Y) either the intermediate DC voltage (V 0 ), or one or the other of the two high continuous voltages (V 1 and V 2 ), these means (I 4 ) also making it possible to isolate the interface circuit (6) from the diode network (8) which follows it on the integrated circuit ( Y). 7. Circuit selon l'une des revendications 3 à 6, caractérisé, en ce qui concerne les circuits intégrés (X) associés à un seul amplificateur (2), par le fait que : - cet amplificateur (2) a sa sortie fixée à la valeur de la tension continue intermédiaire (V0), lors de l'élaboration des signaux d'entretien, alors que les moyens (I2) du circuit d'interface basse tension/haute tension (6) fournissent également la tension continue intermédiaire (V0); - cet amplificateur (2) a sa sortie fixée à la valeur la plus élevée (V2) des deux hautes tensions continues utilisées, lors de l'élaboration des signaux sélectifs. 7. Circuit according to one of claims 3 to 6, characterized, with regard to the integrated circuits (X) associated with a single amplifier (2), in that: - This amplifier (2) has its output fixed at the value of the intermediate DC voltage (V 0 ), during the development of the maintenance signals, while the means (I 2 ) of the low voltage interface circuit / high voltage (6) also provide the intermediate DC voltage (V 0 ); - This amplifier (2) has its output fixed at the highest value (V 2 ) of the two high DC voltages used, during the preparation of the selective signals. 8. Circuit selon l'une des revendications 3 à 7, caractérisé, en ce qui concerne les circuits intégrés (Y) associés à deux amplificateurs (3, 4), par le fait que : - les amplificateurs (3, 4) ont leur sortie fixée à la valeur d'une des deux hautes tensions continues (V1, V2) utilisées, pendant chaque alternance du signal d'entretien, alors que les moyens (12) du circuit d'interface basse tension/haute tension (6) ne fournissent aucune tension et sont isolés du réseau de diodes (8) ; - l'un des amplificateurs (4) a sa sortie fixée a la valeur la plus élevée (V2) des deux hautes tensions continues utilisées lors de l'élaboration des signaux sélectifs, alors que l'autre amplificateur (3) a sa sortie fixée à l'autre valeur des deux hautes tensions continues utilisées (V 1). 8. Circuit according to one of claims 3 to 7, characterized, with regard to the integrated circuits (Y) associated with two amplifiers (3, 4), in that: - the amplifiers (3, 4) have their output fixed at the value of one of the two high continuous voltages (V 1 , V 2 ) used, during each alternation of the maintenance signal, while the means (1 2 ) of the low voltage / high voltage interface circuit (6) do not supply any voltage and are isolated from the diode network (8); - one of the amplifiers (4) at its output fixed at the higher value (V 2 ) of the two high DC voltages used during the preparation of the selective signals, while the other amplifier (3) at its output fixed at the other value of the two high continuous voltages used ( V 1 ). 9. Circuit selon l'une des revendications 3 à 8, caractérisé, en ce qui concerne les circuits intégrés (X) associés à un seul amplificateur (2), par le fait que : - le réseau de diodes (8) comporte deux diodes tête-bêche reliées, d'une part, à chaque sortie du circuit d'interface, et, d'autre part, l'une à la masse par son anode (D1) et l'autre à la sortie de l'amplificateur (2) par sa cathode (D 2). 9. Circuit according to one of claims 3 to 8, characterized, with regard to the integrated circuits (X) associated with a single amplifier (2), in that: - the diode network (8) comprises two head-to-tail diodes connected, on the one hand, to each output of the interface circuit, and, on the other hand, one to ground by its anode (D 1 ) and the other at the output of the amplifier (2) by its cathode (D 2 ). 10. Circuit selon l'une des revendications 3 à 9, caractérisé, en ce qui concerne les circuits intégrés (Y) associés à deux amplificateurs (3, 4), par le fait que : - le réseau de diodes (8) comporte deux diodes tête-bêche (D3, D4) reliées d'une part, à chaque sortie du circuit d'interface et d'autre part, à la sortie de l'un des amplificateurs. 10. Circuit according to one of claims 3 to 9, characterized, with regard to the integrated circuits (Y) associated with two amplifiers (3, 4), in that: - the diode network (8) comprises two head-to-tail diodes (D 3 , D 4 ) connected on the one hand, to each output of the interface circuit and on the other hand, to the output of one of the amplifiers . 11. Circuit selon l'une des revendication 5 à 10, caractérisé, en ce que les deux hautes tensions continues sont sensiblement égales à + 100 Volts (V 2) et - 100 Volts (V1) et en ce que la tension continue intermédiaire (V0) est sensiblement égale à 0 Volt.11. Circuit according to one of claims 5 to 10, characterized in that the two high DC voltages are substantially equal to + 100 volts (V 2 ) and - 100 volts (V 1 ) and in that the intermediate DC voltage (V 0 ) is substantially equal to 0 Volt.
EP82401897A 1981-10-23 1982-10-15 Control circuit for an ac plasma panel Expired EP0078193B1 (en)

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FR8119941A FR2515402B1 (en) 1981-10-23 1981-10-23
FR8119941 1981-10-23

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2547091A1 (en) * 1983-06-03 1984-12-07 Thomson Csf METHOD FOR CONTROLLING AN ALTERNATIVE TYPE PLASMA PANEL AND DEVICE FOR IMPLEMENTING IT
FR2552575A1 (en) * 1983-09-27 1985-03-29 Thomson Csf CONTROL CIRCUIT FOR AN ALTERNATIVE TYPE PLASMA PANEL
GB2326511A (en) * 1997-06-20 1998-12-23 Daewoo Electronics Co Ltd Method and apparatus for driving the address electrodes of a flat plasma display panel.

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2578671B1 (en) * 1985-03-05 1987-05-15 Thomson Csf CONTROL CIRCUIT FOR AN ALTERNATIVE PLASMA PANEL
EP1231590A3 (en) * 1991-12-20 2003-08-06 Fujitsu Limited Circuit for driving display panel
KR950003381B1 (en) * 1992-05-26 1995-04-12 삼성전관 주식회사 Lcd device and driving method of plasma address type
US5510748A (en) * 1994-01-18 1996-04-23 Vivid Semiconductor, Inc. Integrated circuit having different power supplies for increased output voltage range while retaining small device geometries
US5572211A (en) * 1994-01-18 1996-11-05 Vivid Semiconductor, Inc. Integrated circuit for driving liquid crystal display using multi-level D/A converter
US5465054A (en) * 1994-04-08 1995-11-07 Vivid Semiconductor, Inc. High voltage CMOS logic using low voltage CMOS process
US6078318A (en) * 1995-04-27 2000-06-20 Canon Kabushiki Kaisha Data transfer method, display driving circuit using the method, and image display apparatus
US5604449A (en) * 1996-01-29 1997-02-18 Vivid Semiconductor, Inc. Dual I/O logic for high voltage CMOS circuit using low voltage CMOS processes
FR2773907B1 (en) * 1998-01-20 2000-04-07 Thomson Tubes Electroniques BI-SUBSTRATE PLASMA PANEL WITH IMPROVED LIGHT OUTPUT

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3867646A (en) * 1973-10-05 1975-02-18 Electronic Arrays MOSFET circuitry for integrated chips interfacing with higher voltage devices
US3997813A (en) * 1975-11-10 1976-12-14 Burroughs Corporation MOS integrated circuit chip for display panels

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3821596A (en) * 1971-10-19 1974-06-28 Owens Illinois Inc Sustainer voltage generator
US3846646A (en) * 1972-12-08 1974-11-05 Owens Illinois Inc Control apparatus for supplying operating potentials
US4063131A (en) * 1976-01-16 1977-12-13 Owens-Illinois, Inc. Slow rise time write pulse for gas discharge device
JPS5567791A (en) * 1978-11-16 1980-05-22 Fujitsu Ltd Blanking system for display unit
JPS5683792A (en) * 1979-12-11 1981-07-08 Fujitsu Ltd Gas discharge panel
US4316123A (en) * 1980-01-08 1982-02-16 International Business Machines Corporation Staggered sustain voltage generator and technique
US4392084A (en) * 1981-03-13 1983-07-05 The United States Of America As Represented By The Secretary Of The Army Sustainer circuit for plasma display panels
US4370651A (en) * 1981-06-29 1983-01-25 International Business Machines Corporation Advanced plasma panel technology

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3867646A (en) * 1973-10-05 1975-02-18 Electronic Arrays MOSFET circuitry for integrated chips interfacing with higher voltage devices
US3997813A (en) * 1975-11-10 1976-12-14 Burroughs Corporation MOS integrated circuit chip for display panels

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SID INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, mai 1976, 1 ère édition, Lewis Winner, pages 58-59, New York (USA); *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2547091A1 (en) * 1983-06-03 1984-12-07 Thomson Csf METHOD FOR CONTROLLING AN ALTERNATIVE TYPE PLASMA PANEL AND DEVICE FOR IMPLEMENTING IT
EP0131479A1 (en) * 1983-06-03 1985-01-16 Thomson-Csf Method and device for controlling an A.C. plasma panel
US4636784A (en) * 1983-06-03 1987-01-13 Thomson-Csf Process for the control of an alternating current plasma panel and apparatus for performing the same
FR2552575A1 (en) * 1983-09-27 1985-03-29 Thomson Csf CONTROL CIRCUIT FOR AN ALTERNATIVE TYPE PLASMA PANEL
EP0150633A2 (en) * 1983-09-27 1985-08-07 Thomson-Csf Driver system for a A.C. plasma panel
EP0150633A3 (en) * 1983-09-27 1986-04-09 Thomson-Csf Driver system for a a.c. plasma panel
US4652796A (en) * 1983-09-27 1987-03-24 Thomson-Csf Control circuit for an alternate type plasma panel
GB2326511A (en) * 1997-06-20 1998-12-23 Daewoo Electronics Co Ltd Method and apparatus for driving the address electrodes of a flat plasma display panel.
GB2326511B (en) * 1997-06-20 2001-10-17 Daewoo Electronics Co Ltd Method and apparatus for driving address electrodes in a flat panel display

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FR2515402B1 (en) 1987-12-24
JPH0736101B2 (en) 1995-04-19
US4575721A (en) 1986-03-11
FR2515402A1 (en) 1983-04-29
EP0078193B1 (en) 1986-08-20
DE3272748D1 (en) 1986-09-25
JPS5880695A (en) 1983-05-14

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