EP1700290B1 - Image display screen and method of addressing said screen - Google Patents

Image display screen and method of addressing said screen Download PDF

Info

Publication number
EP1700290B1
EP1700290B1 EP04805623.8A EP04805623A EP1700290B1 EP 1700290 B1 EP1700290 B1 EP 1700290B1 EP 04805623 A EP04805623 A EP 04805623A EP 1700290 B1 EP1700290 B1 EP 1700290B1
Authority
EP
European Patent Office
Prior art keywords
addressing
voltage
emitter
electrode
selection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP04805623.8A
Other languages
German (de)
French (fr)
Other versions
EP1700290A1 (en
Inventor
Philippe Le Roy
Christophe Prat
Fabien Ammardji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
THOMSON LICENSING
Original Assignee
Thomson Licensing SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing SAS filed Critical Thomson Licensing SAS
Publication of EP1700290A1 publication Critical patent/EP1700290A1/en
Application granted granted Critical
Publication of EP1700290B1 publication Critical patent/EP1700290B1/en
Ceased legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the invention relates to an image display screen and a method of addressing this screen.
  • the invention relates to a display screen of the type based on active matrix organic electroluminescent materials etched on amorphous silicon (Si-a).
  • Thin film transistors in hydrogenated amorphous silicon have advantages over thin-film transistors made of polycrystalline silicon (p-Si) for the design of screens based on organic electroluminescent materials because they are more easy to manufacture and they exhibit luminance uniformity on samples of relatively large size.
  • p-Si polycrystalline silicon
  • the trigger threshold voltage of the amorphous silicon transistors drift over time during the prolonged application of a voltage between their gate and their source.
  • This derivation of the triggering threshold voltages results, on the one hand, in a process of marking the image on the screen and, on the other hand, changes in luminance of the screen over time.
  • a screen of the aforementioned type comprising addressing control means adapted to apply, during each image frame, the current modulator of each transmitter of this screen and using the same and unique addressing circuit of this transmitter, alternatively an addressing voltage representative of an image data and a polarity voltage inverse to the polarity of the addressing voltage.
  • this architecture and this control mode is likely to cause a decrease in luminance of the screen and a phenomenon of flickering on the screen, since the transmission time is reduced during each frame.
  • a screen of the aforementioned type comprising addressing control means adapted to apply, during each image frame, to the current modulator of each transmitter of this screen and using at least one of the plurality of addressing circuits of this transmitter, an addressing voltage representative of a datum of image always having the same polarization.
  • the object of the invention is to provide an alternating screen that has small variations in luminance over time.
  • the subject of the invention is an image display screen according to claim 1.
  • the invention also relates to a method of addressing a display screen according to claim 8.
  • the display screen according to the invention is an active matrix screen comprising light emitters distributed along lines and columns to form a network of emitters.
  • the transmitters of the display screen are organic light-emitting diodes known by the acronym OLED. They are each associated with a pixel when the screen is monochrome or a sub-pixel when the screen is full color. They emit a luminous intensity directly proportional to the current passing through them.
  • the figure 1 represents control means 2 of the transmission of the transmitters 4 of the network according to a first embodiment of the invention. For the sake of simplification, only the means for controlling the addressing of a single transmitter have been illustrated in this figure.
  • the control means 2 comprise a first addressing circuit 6 connected to a transmitter 4 of the network, addressing control means 8 of a transmitter column, selection control means 10 of a transmission line. transmitters, a control system 11 and a second addressing circuit 12 also connected to a transmitter 4.
  • the first addressing circuit 6 comprises a current modulator 14, a storage capacitor 16 and a selection switch 18.
  • the modulator 14 and the switch 18 are thin-film transistors in hydrogenated amorphous silicon. More precisely, they are n-type transistors. They comprise a drain, a gate and a source and are able to be traversed by a current flowing from their drain to their source, when a voltage greater than or equal to their trigger threshold voltage is applied between their gate and their source.
  • transistors 14 and 18 are able to be traversed by a current flowing from their source to their drain.
  • the drain of the modulator 14 is connected to the cathode of the transmitter 4.
  • the anode of the transmitter 4 is connected to a DC voltage generator V dd suitable for supplying power.
  • the source of the modulator 14 is connected to a ground electrode or to a negative voltage.
  • the gate of the modulator 14 is connected to the source of the switch 18 and to one terminal of the storage capacitor 16.
  • the other terminal of the capacitor 16 is connected to a ground electrode.
  • the gate of the switch 18 is connected to the selection control means 10 and its drain is connected to the addressing control means 8.
  • the addressing control means 8 of an emitter column comprise an emitter column addressing electrode 20 and an addressing control unit 22.
  • the electrode 20 is connected on the one hand to the emitter column.
  • control unit 22 and, on the other hand, the drain of the switch 18 of the first addressing circuits 6 of a column of transmitters.
  • the selection control means 10 comprises a first selection electrode 24 and a second selection electrode 26 for each transmitter line as well as a selection control unit 28.
  • first selection electrode 24 is connected to the control unit 28 and to the gate of the switch 18 of the first addressing circuits 6 of a line of transmitters.
  • the second electrode 26 is connected to the control unit 28 and the gate of the switch 38 of the second addressing circuit 12 of a transmitter line.
  • the control system 11 is connected to the addressing control unit 22 and to the selection control unit 28.
  • the second addressing circuit 12 comprises the same components as the first addressing circuit 6, namely a current modulator 34, a storage capacitor 36 and a selection switch 38. These components are connected to each other in the same manner as in the first addressing circuit 6 and will not be described in detail.
  • the current modulator 34 of the second addressing circuit 12 is connected to the cathode of the transmitter 4 at the node 32.
  • the drain of the switch 38 is connected to the same addressing electrode 20 as the switch 18 and its gate is connected to the second selection electrode 26.
  • the control system 11 is capable of transmitting digital image data and data relating to the bias voltage to the control unit 22 and a periodic selection signal to the control unit 28 at a predefined frequency.
  • the addressing control unit 22 is capable of transmitting an address voltage V D representative of an image data item to all the emitters of a column via the electrode 20.
  • the control unit of FIG. addressing 22 is also able to apply to the electrode 20 a voltage, called the bias voltage V p , of a polarization inverse to the polarization of the addressing voltage.
  • This voltage is a predetermined negative voltage of a predetermined duration.
  • the bias voltage V p is between -2 volts and -25 volts.
  • the term "reverse or negative bias voltage” is used to denote a potential difference V gs between the gate and source electrodes of the modulator which is less than 0 Volt: V gs ⁇ 0V.
  • the control unit 28 is able to apply a periodic selection voltage V S1 , V S2 to the gate of the switch 18 of the first addressing circuits 6 of a transmitter line or to the gate of the switch 38 of the second addressing circuit 12 of the same line of transmitters to allow the application of the addressing voltage V D or the bias voltage V p to the gate of the modulator 14 of the first addressing circuit 6 or to the gate of the modulator 34 second addressing circuit 12.
  • FIGS. 2A to 2F illustrate the method of addressing a display screen according to the first embodiment of the invention.
  • This method comprises a polarization programming step A of the modulator 34 of the second addressing circuit 12.
  • the selection control unit 28 transmits to the second electrode 26, a selection voltage V s2 , as illustrated on FIG. Figure 2B .
  • the selection switch 38 is unlocked by the application to its gate of this selection voltage V S2 .
  • the addressing control unit 22 applies to the addressing electrode 20 a bias voltage V p of negative polarity (V gs ⁇ 0).
  • V p bias voltage
  • the bias voltage V p is applied to the gate of the current modulator 34 and to a terminal of the storage capacitor 36.
  • the drain current I d2 which passed through the modulator 34 to supply the transmitter 4 during the previous frame, tends to now to 0 during this new frame as shown by the dashed curve of the figure 2E .
  • the storage capacity 36 having previously stored a voltage V D applied during the previous frame is biased to the bias voltage V p , as shown in FIG. 2D figure ; as indicated by the dashed curve of this figure, the storage capacity 36 maintains this bias voltage at the gate of the modulator 34 during a polarization phase of the second addressing circuit 12 and until the end of the next step
  • the steps B, C and D together constitute a polarization phase of the second addressing circuit 12.
  • the trip threshold voltage of modulator 34 drifted by the application of an address voltage during the previous frame is again derived during the polarization phase and during the entire duration of the new frame, by applying the bias voltage V p but in a direction opposite to its previous drift.
  • the bias voltage applied to the gate of the modulator 34 during the new frame makes it possible to reverse the drift of its trigger threshold voltage and to put it back to its initial value, that is to say to the value that it had before being derived by the application of an addressing voltage to its gate during the previous frame.
  • the selection control unit 28 During the addressing programming step B of the modulator 14 of the first addressing circuit 6, the selection control unit 28 generates a selection voltage V S1 and applies it to the first electrode 24.
  • the addressing control unit 22 transmits to the addressing electrode 20 an address voltage V Da representative of an image data item.
  • the selection switch 18, at the intersection of the addressing electrode 20 and the first selection electrode 24, is unblocked and transmits the addressing voltage V Da to the modulator 14 and to the storage capacity 16 of the first circuit 6. Since the addressing voltage V Da is greater than the trigger threshold voltage of the modulator 14, a drain current I d1 is established between the drain and the source of the modulator 14 and therefore passes through the transmitter 4 as shown in the figure 2F .
  • the capacitor 16 stores a potential representative of the addressing voltage V Da at the gate of the modulator 14 to maintain the luminance of the transmitter 4 during a time interval corresponding to the duration of an image frame. Thus, the transmitter 4 emits light during step C until the end of the image frame.
  • the selection control unit 28 transmits a selection voltage V S1 to the first electrode 24.
  • the addressing control unit 22 applies a bias voltage V p to the electrode 20.
  • the selection switch 18, at the intersection of the first electrode 24 and the addressing electrode 20, is unlocked and this time transmits the bias voltage V p to the modulator 14 and the storage capacitor 16.
  • the capacitance storage discharges and stores the charges transmitted by the bias voltage during a polarization phase E, F of the first addressing circuit 6, as shown in FIG. 2D figure .
  • the drain current I d1 of the previous frame ceases to pass through the modulator 14.
  • the trigger threshold voltage of the modulator 14 which has drifted and increased during the image frame will decrease during the new frame and especially at the course of step F.
  • the next image frame starts with an addressing programming step E of the modulator 34 of the second addressing circuit 12.
  • the selection control unit 28 applies to the electrode 26 a selection voltage V s2 .
  • the addressing control unit 22 applies, parallel to the electrode 20, an addressing voltage V Db .
  • the switch 38 of the second addressing circuit 12 is unlocked and the addressing voltage V Db , representative of an image data, is applied to the gate of the modulator 34 and to the terminal of the storage capacitor 36.
  • a drain current I d2 is generated between the drain and the source of the modulator 34. This current has an amplitude proportional to the value of the image data to be transmitted during this image frame. This current flows through the light emitter 4 during step F until the end of the image frame.
  • the transmitter 4 is supplied with current in turn by the first modulator 14 during an activation phase of the first addressing circuit, then by the second modulator 34 during a phase activating the second addressing circuit.
  • the trigger threshold voltages of the modulator 14 of the first addressing circuit and the modulator 34 of the second addressing circuit are increased and then decreased in turn at each image frame. Such a device therefore advantageously makes it possible to compensate for the trigger threshold voltage drift of the modulators of the panel.
  • An emitter 4 and the control means 40 of its transmission according to a second embodiment of the invention are represented on the figure 3 .
  • control means 40 comprise first addressing circuits 6 and second addressing circuits 12, each connected to a transmitter 4 of the network, addressing control means 42 of a column d transmitters, selection control means 44 of a transmitter line and a control system 56.
  • the first 6 and the second 12 addressing circuits comprise the same components, connected in the same way as the addressing circuits described in connection with the figure 1 . They are identified by the same references as on the figure 1 and will not be described below.
  • the addressing control means 42 comprise an addressing control unit 46, a first addressing electrode 48 and a second addressing electrode 50 for each column of transmitters.
  • the first addressing electrode 48 is connected to the control unit 46 and the drain of the switch 18 of all the first addressing circuits 6 of a column of transmitters.
  • the second addressing electrode 50 is connected to the control unit 46 and to the drain of the switch 38 of the set of second addressing circuits 12 of a column of transmitters.
  • the addressing unit 46 for addressing is able to send an address voltage V D1 on the first electrode 48 and concomitantly an address voltage V D2 on the second electrode 50.
  • the selection control means 44 comprise a selection control unit 54 and, for each row of transmitters, a single selection electrode 52.
  • the selection electrode 52 is connected to the control unit 54, to the gate of the switch 18 of the first addressing circuits 6 and to the gate of the switch 38 of the second addressing circuits 12 of a line of transmitters.
  • the control system 56 is connected to the control unit 54 as well as to the control unit 46. This control system 56 is able to transmit to the control unit 46 digital image data and data. relating to the bias voltage. It is also able to transmit to the control unit 54 a periodic selection signal.
  • This method comprises a step G of addressing addressing of the capacitor 16 and of the simultaneous polarization programming of the modulator 34.
  • the control unit 46 transmits an address voltage V Da representative of an image data item to the first electrode 48 and a bias voltage V p to the second electrode 50.
  • control unit 54 transmits a selection voltage V S to the selection electrode 52.
  • the switch 18 of the first addressing circuit and the switch 38 of the second programming circuit are unlocked so that firstly, the bias voltage V p is applied to the gate of the modulator 34 and the terminal of the capacitor 36 and, secondly, the addressing voltage V Da is applied to the gate of the modulator 14 and to a terminal storage capacity 16.
  • the storage capacitor 36 discharges and then charges at a negative potential equal to the bias voltage V p .
  • This voltage maintained at the gate of the modulator 34 by the storage capacitor 36 aims to progressively reduce the trigger threshold voltage of the modulator 34 in particular during the step H.
  • the drain current I d2 vanishes and remains zero during step H.
  • the capacitor 16 charges at the potential V Da and a drain current I d1 is established between the drain and the source of the modulator 14.
  • the transmitter 4 is supplied with the current I d1 during the step H until the end of the image frame.
  • the transmitter 4 is therefore supplied with current by the first addressing circuit 6; the steps G and H together form an activation phase of the first addressing circuit. Furthermore, during the steps G and H, the bias voltage is applied to the gate of the modulator 34 to compensate for the drift of its trigger threshold voltage. The steps G and H therefore also form a polarization phase of the second addressing circuit.
  • control unit 46 transmits a bias voltage V p to the first electrode 48 and an address voltage V Db representative of an image data at the second electrode 50.
  • the switches 18 and 38 are simultaneously open by applying the selection voltage V S to the electrode 52.
  • the bias voltage V p is transmitted to the gate of the modulator 14 and to the terminal of the capacitor 16.
  • the capacitor 16 is discharge and then charge negatively.
  • the drain current I d1 vanishes and remains zero during step J.
  • the bias voltage V p is applied to the gate of the modulator 14.
  • the steps I and J together form a polarization phase of the first addressing circuit 6.
  • the addressing voltage V Db is applied to the gate of the modulator 34 and to a terminal of the capacitor 36.
  • This voltage maintained at the gate of the modulator 34 by the capacitor 36, generates a drain current I d2 which feeds transmitter 4 during step J and up to the next step of programming new image data.
  • the transmitter 4 is supplied with current by the second addressing circuit 12; these steps together form an activation phase of the second addressing circuit.
  • the emitter 4 is thus supplied in turn by the modulated current, by the modulator 14, then by the modulator 34.
  • the first 6 and second 12 addressing circuits are alternately activated to power the transmitter 4.
  • the modulator 34 When the modulator 14 supplies the transmitter 4, the modulator 34 is polarized by applying a bias voltage corresponding to a high negative voltage to its gate so that the tripping threshold voltage of the modulator 34 derived during the previous phase returns to its initial value.
  • the modulator 14 when the modulator 34 supplies the transmitter 4, the modulator 14 is biased by this same negative bias voltage so that its trigger threshold voltage having previously drifted in one direction, drifts in an opposite direction.
  • the addressing method associated with each transmitter contributes to compensating for variations in the tripping threshold of the modulators of a display screen.
  • the polarization and activation phases are carried out simultaneously and have equal durations.
  • the control means are also able to control the modulators 14 and 34 so that the polarization and activation phases of the first and second circuits, although performed simultaneously, have different durations.
  • the bias voltage applied to one or the other of the modulators of a transmitter varies from one image frame to another, as a function of the addressing voltage applied to the this modulator during the previous frame; preferably, this bias voltage is equal but of opposite sign to said addressing voltage of the previous frame.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)

Description

L'invention concerne un écran d'affichage d'images et un procédé d'adressage de cet écran.The invention relates to an image display screen and a method of addressing this screen.

En particulier, l'invention est relative à un écran d'affichage du type à base de matériaux électroluminescents organiques à matrice active gravée sur du Silicium amorphe (Si-a).In particular, the invention relates to a display screen of the type based on active matrix organic electroluminescent materials etched on amorphous silicon (Si-a).

Les transistors en couches minces (Thin Film Transistor) en Silicium amorphe hydrogéné présentent des avantages par rapport aux transistors en couches minces en Silicium poly-cristallin (p-Si) pour la conception d'écrans à base de matériaux électroluminescents organiques car ils sont plus faciles à fabriquer et ils présentent une uniformité de luminance sur des échantillons de taille relativement importante.Thin film transistors in hydrogenated amorphous silicon have advantages over thin-film transistors made of polycrystalline silicon (p-Si) for the design of screens based on organic electroluminescent materials because they are more easy to manufacture and they exhibit luminance uniformity on samples of relatively large size.

Cependant, la tension de seuil de déclenchement des transistors en Silicium amorphe dérive au cours du temps lors de l'application prolongée d'une tension entre leur grille et leur source.However, the trigger threshold voltage of the amorphous silicon transistors drift over time during the prolonged application of a voltage between their gate and their source.

Cette dérivation des tensions de seuil de déclenchement se traduit par d'une part, un processus de marquage de l'image sur l'écran et d'autre part, des modifications de luminance de l'écran au cours du temps.This derivation of the triggering threshold voltages results, on the one hand, in a process of marking the image on the screen and, on the other hand, changes in luminance of the screen over time.

Il est connu notamment par le document US 2003/052614 , un écran du type précité comprenant des moyens de commande d'adressage propres à appliquer, au cours de chaque trame d'image, au modulateur de courant de chaque émetteur de cet écran et à l'aide du même et unique circuit d'adressage de cet émetteur, alternativement une tension d'adressage représentative d'une donnée d'image et une tension de polarité inverse à la polarité de la tension d'adressage.He is known in particular by the document US 2003/052614 a screen of the aforementioned type comprising addressing control means adapted to apply, during each image frame, the current modulator of each transmitter of this screen and using the same and unique addressing circuit of this transmitter, alternatively an addressing voltage representative of an image data and a polarity voltage inverse to the polarity of the addressing voltage.

Toutefois, cette architecture et ce mode de pilotage est susceptible d'entraîner une baisse de luminance de l'écran et un phénomène de papillotement sur l'écran, puisque la durée d'émission est réduite au cours de chaque trame.However, this architecture and this control mode is likely to cause a decrease in luminance of the screen and a phenomenon of flickering on the screen, since the transmission time is reduced during each frame.

Il est connu notamment par le document US 6 011 529 (voir notamment figure 9) et WO 2004/051617 , un écran du type précité comprenant des moyens de commande d'adressage propres à appliquer, au cours de chaque trame d'image, au modulateur de courant de chaque émetteur de cet écran et à l'aide d'au moins un parmi la pluralité de circuits d'adressage de cet émetteur, une tension d'adressage représentative d'une donnée d'image présentant toujours la même polarisation.He is known in particular by the document US 6,011,529 (see in particular Figure 9) and WO 2004/051617 , a screen of the aforementioned type comprising addressing control means adapted to apply, during each image frame, to the current modulator of each transmitter of this screen and using at least one of the plurality of addressing circuits of this transmitter, an addressing voltage representative of a datum of image always having the same polarization.

Il est connu notamment par le document EP 1111 574 A2 un écran de type précité comprenant des moyens de commande d'adressage propres à sélectionner alternativement un premier ou un second transistor pour fournir du courant aux émetteurs de l'écran. Ce document ne propose pas de modulation de l'amplitude de ce courant proportionnelle aux valeurs de données de trames d'images.He is known in particular by the document EP 1111 574 A2 a screen of the aforementioned type comprising addressing control means adapted alternately to select a first or a second transistor to supply current to the transmitters of the screen. This document does not propose modulation of the amplitude of this current proportional to the data values of picture frames.

Le but de l'invention est de proposer un écran alternatif qui présente de faibles variations de luminance au cours du temps.The object of the invention is to provide an alternating screen that has small variations in luminance over time.

A cet effet, l'invention a pour objet un écran d'affichage d'images selon la revendication 1.For this purpose, the subject of the invention is an image display screen according to claim 1.

L'invention a également pour objet un procédé d'adressage d'un écran d'affichage selon la revendication 8.The invention also relates to a method of addressing a display screen according to claim 8.

L'invention sera mieux comprise à la lecture de la description qui va suivre, donnée uniquement à titre d'exemple et faite en se référant aux dessins, sur lesquels :

  • la figure 1 est une vue schématique représentant un émetteur et des moyens de commande de l'émission de cet émetteur de l'écran selon un premier mode de réalisation de l'invention ;
  • les figures 2A à 2F sont des graphes représentant l'évolution au cours du temps de différents tensions et courants au cours du procédé d'adressage réalisé par le dispositif selon l'invention ; en particulier,
  • la figure 2A est un graphe représentant la tension de sélection appliquée à une première électrode de sélection ;
  • la figure 2B est un graphe représentant la tension appliquée à une seconde électrode de sélection ;
  • la figure 2C est un graphe représentant la tension appliquée à une électrode d'adressage ;
  • la figure 2D est un graphe représentant la tension appliquée aux bornes d'une première capacité de stockage et la tension appliquée aux bornes d'une seconde capacité de stockage ;
  • la figure 2E est un graphe représentant le courant de drain traversant un premier modulateur de courant et le courant de drain traversant un second modulateur de courant ;
  • la figure 2F est un graphe représentant le courant traversant un émetteur ;
  • la figure 3 est une vue schématique représentant un émetteur et des moyens de commande de l'émission de cet émetteur de l'écran selon un second mode de réalisation de l'invention ;
  • les figures 4A à 4F sont des graphes représentant l'évolution au cours du temps de différents tensions et courants au cours du procédé d'adressage réalisé par le dispositif selon le second mode de réalisation de l'invention ; en particulier,
  • la figure 4A est un graphe représentant la tension de sélection appliquée à une électrode de sélection ;
  • la figure 4B est un graphe représentant la tension appliquée à une première électrode d'adressage ;
  • la figure 4C est un graphe représentant la tension appliquée à une seconde électrode d'adressage ;
  • la figure 4D est un graphe représentant la tension aux bornes d'une première capacité de stockage et la tension aux bornes d'une seconde capacité de stockage ;
  • la figure 4E est un graphe représentant le courant de drain traversant un premier modulateur de courant et le courant de drain traversant un second modulateur de courant ; et
  • la figure 4F est un graphe représentant le courant traversant un émetteur.
The invention will be better understood on reading the description which follows, given solely by way of example and with reference to the drawings, in which:
  • the figure 1 is a schematic view showing a transmitter and control means of the transmission of this transmitter screen according to a first embodiment of the invention;
  • the Figures 2A to 2F are graphs representing the evolution over time of different voltages and currents during the addressing process carried out by the device according to the invention; in particular,
  • the Figure 2A is a graph representing the selection voltage applied to a first selection electrode;
  • the Figure 2B is a graph representing the voltage applied to a second selection electrode;
  • the Figure 2C is a graph representing the voltage applied to an addressing electrode;
  • the 2D figure is a graph representing the voltage applied across a first storage capacitor and the voltage applied across a second storage capacitor;
  • the figure 2E is a graph showing the drain current flowing through a first current modulator and the drain current flowing through a second current modulator;
  • the figure 2F is a graph representing the current flowing through a transmitter;
  • the figure 3 is a schematic view showing an emitter and means for controlling the transmission of this emitter of the screen according to a second embodiment of the invention;
  • the Figures 4A to 4F are graphs representing the evolution over time of different voltages and currents during the addressing method performed by the device according to the second embodiment of the invention; in particular,
  • the Figure 4A is a graph representing the selection voltage applied to a selection electrode;
  • the Figure 4B is a graph representing the voltage applied to a first addressing electrode;
  • the figure 4C is a graph representing the voltage applied to a second address electrode;
  • the figure 4D is a graph representing the voltage across a first storage capacity and the voltage across a second storage capacity;
  • the figure 4E is a graph showing the drain current flowing through a first current modulator and the drain current flowing through a second current modulator; and
  • the figure 4F is a graph representing the current flowing through a transmitter.

L'écran d'affichage selon l'invention est un écran à matrice active comportant des émetteurs de lumière répartis selon des lignes et des colonnes pour former un réseau d'émetteurs.The display screen according to the invention is an active matrix screen comprising light emitters distributed along lines and columns to form a network of emitters.

Les émetteurs de l'écran d'affichage sont des diodes électroluminescentes organiques connues sous l'acronyme OLED. Ils sont chacun associé à un pixel lorsque l'écran est monochrome ou à un sous pixel lorsque l'écran est polychrome. Ils émettent une intensité lumineuse directement proportionnelle au courant qui les traverse.The transmitters of the display screen are organic light-emitting diodes known by the acronym OLED. They are each associated with a pixel when the screen is monochrome or a sub-pixel when the screen is full color. They emit a luminous intensity directly proportional to the current passing through them.

La figure 1 représente des moyens de commande 2 de l'émission des émetteurs 4 du réseau selon un premier mode de réalisation de l'invention. Dans un souci de simplification, seuls les moyens de commande de l'adressage d'un unique émetteur ont été illustrés sur cette figure.The figure 1 represents control means 2 of the transmission of the transmitters 4 of the network according to a first embodiment of the invention. For the sake of simplification, only the means for controlling the addressing of a single transmitter have been illustrated in this figure.

Les moyens de commande 2 comprennent un premier circuit d'adressage 6 relié à un émetteur 4 du réseau, des moyens de commande d'adressage 8 d'une colonne d'émetteurs, des moyens de commande de sélection 10 d'une ligne d'émetteurs, un système de commande 11 et un second circuit d'adressage 12 relié également à un émetteur 4.The control means 2 comprise a first addressing circuit 6 connected to a transmitter 4 of the network, addressing control means 8 of a transmitter column, selection control means 10 of a transmission line. transmitters, a control system 11 and a second addressing circuit 12 also connected to a transmitter 4.

Le premier circuit d'adressage 6 comprend un modulateur de courant 14, une capacité de stockage 16 et un interrupteur de sélection 18.The first addressing circuit 6 comprises a current modulator 14, a storage capacitor 16 and a selection switch 18.

Le modulateur 14 et l'interrupteur 18 sont des transistors en couches minces en Silicium amorphe hydrogéné. Plus précisément, ce sont des transistors de type n. Ils comportent un drain, une grille et une source et sont aptes à être traversés par un courant circulant de leur drain vers leur source, lorsqu'une tension supérieure ou égale à leur tension de seuil de déclenchement est appliquée entre leur grille et leur source.The modulator 14 and the switch 18 are thin-film transistors in hydrogenated amorphous silicon. More precisely, they are n-type transistors. They comprise a drain, a gate and a source and are able to be traversed by a current flowing from their drain to their source, when a voltage greater than or equal to their trigger threshold voltage is applied between their gate and their source.

Alternativement, des transistors de type p peuvent également être utilisés. Dans ce cas, les transistors 14 et 18 sont aptes à être traversés par un courant circulant de leur source vers leur drain.Alternatively, p-type transistors may also be used. In this case, the transistors 14 and 18 are able to be traversed by a current flowing from their source to their drain.

Le drain du modulateur 14 est connecté à la cathode de l'émetteur 4. L'anode de l'émetteur 4 est connectée à un générateur de tension continue Vdd propre à l'alimenter en puissance. La source du modulateur 14 est raccordée à une électrode de masse ou à une tension négative. La grille du modulateur 14 est raccordée à la source de l'interrupteur 18 et à une borne de la capacité de stockage 16. L'autre borne de la capacité 16 est connectée à une électrode de masse. La grille de l'interrupteur 18 est branchée aux moyens de commande de sélection 10 et son drain est raccordé aux moyens de commande d'adressage 8.The drain of the modulator 14 is connected to the cathode of the transmitter 4. The anode of the transmitter 4 is connected to a DC voltage generator V dd suitable for supplying power. The source of the modulator 14 is connected to a ground electrode or to a negative voltage. The gate of the modulator 14 is connected to the source of the switch 18 and to one terminal of the storage capacitor 16. The other terminal of the capacitor 16 is connected to a ground electrode. The gate of the switch 18 is connected to the selection control means 10 and its drain is connected to the addressing control means 8.

Les moyens de commande d'adressage 8 d'une colonne d'émetteurs comprennent une électrode d'adressage 20 par colonne d'émetteurs et une unité de pilotage d'adressage 22. L'électrode 20 est branchée d'une part à l'unité de pilotage 22 et, d'autre part au drain de l'interrupteur 18 des premiers circuits d'adressage 6 d'une colonne d'émetteurs.The addressing control means 8 of an emitter column comprise an emitter column addressing electrode 20 and an addressing control unit 22. The electrode 20 is connected on the one hand to the emitter column. control unit 22 and, on the other hand, the drain of the switch 18 of the first addressing circuits 6 of a column of transmitters.

Les moyens de commande de sélection 10 comprennent une première électrode de sélection 24 et une seconde électrode de sélection 26 pour chaque ligne d'émetteurs ainsi qu'une unité de pilotage de sélection 28. La première électrode de sélection 24 est reliée à l'unité de pilotage 28 et à la grille de l'interrupteur 18 des premiers circuits d'adressage 6 d'une ligne d'émetteurs. La seconde électrode 26 est connectée à l'unité de pilotage 28 et à la grille de l'interrupteur 38 des seconds circuits d'adressage 12 d'une ligne d'émetteurs.The selection control means 10 comprises a first selection electrode 24 and a second selection electrode 26 for each transmitter line as well as a selection control unit 28. first selection electrode 24 is connected to the control unit 28 and to the gate of the switch 18 of the first addressing circuits 6 of a line of transmitters. The second electrode 26 is connected to the control unit 28 and the gate of the switch 38 of the second addressing circuit 12 of a transmitter line.

Le système de commande 11 est connecté à l'unité de pilotage d'adressage 22 et à l'unité de pilotage de sélection 28.The control system 11 is connected to the addressing control unit 22 and to the selection control unit 28.

Le second circuit d'adressage 12 comporte les mêmes composants que le premier circuit d'adressage 6 à savoir un modulateur de courant 34, une capacité de stockage 36 et un interrupteur de sélection 38. Ces composants sont connectés entre eux de la même manière que dans le premier circuit d'adressage 6 et ne seront pas décrits de manière détaillée.The second addressing circuit 12 comprises the same components as the first addressing circuit 6, namely a current modulator 34, a storage capacitor 36 and a selection switch 38. These components are connected to each other in the same manner as in the first addressing circuit 6 and will not be described in detail.

Spécifiquement, le modulateur de courant 34 du second circuit d'adressage 12 est raccordé à la cathode de l'émetteur 4 au noeud 32. Le drain de l'interrupteur 38 est raccordé à la même électrode d'adressage 20 que l'interrupteur 18 et sa grille est connectée à la seconde électrode de sélection 26.Specifically, the current modulator 34 of the second addressing circuit 12 is connected to the cathode of the transmitter 4 at the node 32. The drain of the switch 38 is connected to the same addressing electrode 20 as the switch 18 and its gate is connected to the second selection electrode 26.

Le système de commande 11 est apte à transmettre des données numériques d'image et des données relatives à la tension de polarisation à l'unité de pilotage 22 et un signal périodique de sélection à l'unité de pilotage 28 à une fréquence prédéfinie.The control system 11 is capable of transmitting digital image data and data relating to the bias voltage to the control unit 22 and a periodic selection signal to the control unit 28 at a predefined frequency.

L'unité de pilotage d'adressage 22 est apte à transmettre une tension d'adressage VD représentative d'une donnée d'image à l'ensemble des émetteurs d'une colonne via l'électrode 20. L'unité de pilotage d'adressage 22 est également apte à appliquer à l'électrode 20 une tension, dite tension de polarisation Vp, d'une polarisation inverse à la polarisation de la tension d'adressage. Cette tension est une tension négative prédéfinie d'une durée prédéterminée. Préférentiellement, la tension de polarisation Vp est comprise entre - 2 Volts et - 25 Volts. D'une manière générale, on appelle tension de polarisation inverse ou négative, une différence de potentiel Vgs entre les électrodes de grille et de source du modulateur qui est inférieure à 0 Volt : Vgs < 0V.The addressing control unit 22 is capable of transmitting an address voltage V D representative of an image data item to all the emitters of a column via the electrode 20. The control unit of FIG. addressing 22 is also able to apply to the electrode 20 a voltage, called the bias voltage V p , of a polarization inverse to the polarization of the addressing voltage. This voltage is a predetermined negative voltage of a predetermined duration. Preferably, the bias voltage V p is between -2 volts and -25 volts. In general, the term "reverse or negative bias voltage" is used to denote a potential difference V gs between the gate and source electrodes of the modulator which is less than 0 Volt: V gs <0V.

L'unité de pilotage 28 est apte à appliquer une tension de sélection périodique VS1, VS2 à la grille de l'interrupteur 18 des premiers circuits d'adressage 6 d'une ligne d'émetteurs ou à la grille de l'interrupteur 38 des seconds circuits d'adressage 12 de la même ligne d'émetteurs pour autoriser l'application de la tension d'adressage VD ou de la tension de polarisation Vp à la grille du modulateur 14 du premier circuit d'adressage 6 ou à la grille du modulateur 34 second circuit d'adressage 12.The control unit 28 is able to apply a periodic selection voltage V S1 , V S2 to the gate of the switch 18 of the first addressing circuits 6 of a transmitter line or to the gate of the switch 38 of the second addressing circuit 12 of the same line of transmitters to allow the application of the addressing voltage V D or the bias voltage V p to the gate of the modulator 14 of the first addressing circuit 6 or to the gate of the modulator 34 second addressing circuit 12.

Les figures 2A à 2F illustrent le procédé d'adressage d'un écran d'affichage selon le premier mode de réalisation de l'invention.The Figures 2A to 2F illustrate the method of addressing a display screen according to the first embodiment of the invention.

Ce procédé comprend une étape de programmation de polarisation A du modulateur 34 du second circuit d'adressage 12. L'unité de pilotage de sélection 28 transmet à la seconde électrode 26, une tension de sélection Vs2, tel qu'illustré sur la figure 2B. L'interrupteur de sélection 38 est débloqué par l'application à sa grille de cette tension de sélection VS2.This method comprises a polarization programming step A of the modulator 34 of the second addressing circuit 12. The selection control unit 28 transmits to the second electrode 26, a selection voltage V s2 , as illustrated on FIG. Figure 2B . The selection switch 38 is unlocked by the application to its gate of this selection voltage V S2 .

Simultanément, l'unité de pilotage d'adressage 22 applique à l'électrode d'adressage 20 une tension de polarisation Vp d'une polarité négative (Vgs < 0). La tension de polarisation Vp est appliquée à la grille du modulateur de courant 34 et à une borne de la capacité de stockage 36. Le courant de drain Id2 qui traversait le modulateur 34 pour alimenter l'émetteur 4 durant la trame précédente, tend maintenant vers 0 lors de cette nouvelle trame ainsi que le montre la courbe en pointillés de la figure 2E.Simultaneously, the addressing control unit 22 applies to the addressing electrode 20 a bias voltage V p of negative polarity (V gs <0). The bias voltage V p is applied to the gate of the current modulator 34 and to a terminal of the storage capacitor 36. The drain current I d2 which passed through the modulator 34 to supply the transmitter 4 during the previous frame, tends to now to 0 during this new frame as shown by the dashed curve of the figure 2E .

Parallèlement, la capacité de stockage 36 ayant préalablement stockée une tension VD appliquée lors de la trame précédente, se polarise à la tension de polarisation Vp, tel qu'illustré sur la figure 2D ; comme l'indique la courbe en pointillés de cette figure, la capacité de stockage 36 maintient cette tension de polarisation à la grille du modulateur 34 pendant une phase de polarisation du second circuit d'adressage 12 et jusqu'à la fin de la prochaine étape de programmation du modulateur 34. Les étapes B, C et D constituent ensemble une phase de polarisation du second circuit d'adressage 12.Meanwhile, the storage capacity 36 having previously stored a voltage V D applied during the previous frame, is biased to the bias voltage V p , as shown in FIG. 2D figure ; as indicated by the dashed curve of this figure, the storage capacity 36 maintains this bias voltage at the gate of the modulator 34 during a polarization phase of the second addressing circuit 12 and until the end of the next step The steps B, C and D together constitute a polarization phase of the second addressing circuit 12.

La tension de seuil de déclenchement du modulateur 34 ayant subi une dérive par l'application d'une tension d'adressage au cours de la trame d'image précédente, est à nouveau dérivée pendant la phase de polarisation et durant toute la durée de la nouvelle trame, par l'application de la tension de polarisation Vp mais dans un sens opposé à sa dérive précédente.The trip threshold voltage of modulator 34 drifted by the application of an address voltage during the previous frame is again derived during the polarization phase and during the entire duration of the new frame, by applying the bias voltage V p but in a direction opposite to its previous drift.

La tension de polarisation appliquée à la grille du modulateur 34 pendant la nouvelle trame permet d'inverser la dérive de sa tension de seuil de déclenchement et de replacer celle-ci à sa valeur initiale, c'est-à-dire à la valeur qu'elle avait avant d'avoir été dérivée par l'application d'une tension d'adressage à sa grille lors de la trame précédente.The bias voltage applied to the gate of the modulator 34 during the new frame makes it possible to reverse the drift of its trigger threshold voltage and to put it back to its initial value, that is to say to the value that it had before being derived by the application of an addressing voltage to its gate during the previous frame.

Au cours de l'étape B de programmation d'adressage du modulateur 14 du premier circuit d'adressage 6, l'unité de pilotage de sélection 28 génère une tension de sélection VS1 et l'applique à la première électrode 24.During the addressing programming step B of the modulator 14 of the first addressing circuit 6, the selection control unit 28 generates a selection voltage V S1 and applies it to the first electrode 24.

En même temps, l'unité de pilotage d'adressage 22 transmet à l'électrode d'adressage 20 une tension d'adressage VDa représentative d'une donnée d'image. L'interrupteur de sélection 18, au croisement de l'électrode d'adressage 20 et de la première électrode de sélection 24, est débloqué et transmet la tension d'adressage VDa au modulateur 14 et à la capacité de stockage 16 du premier circuit d'adressage 6. Comme la tension d'adressage VDa est supérieure à la tension de seuil de déclenchement du modulateur 14, un courant de drain Id1 s'établit entre le drain et la source du modulateur 14 et traverse donc l'émetteur 4 comme illustré à la figure 2F. La capacité 16 stocke un potentiel représentatif de la tension d'adressage VDa à la grille du modulateur 14 pour maintenir la luminance de l'émetteur 4 pendant un intervalle de temps correspondant à la durée d'une trame d'image. Ainsi, l'émetteur 4 émet de la lumière pendant l'étape C jusqu'à la fin de la trame d'image.At the same time, the addressing control unit 22 transmits to the addressing electrode 20 an address voltage V Da representative of an image data item. The selection switch 18, at the intersection of the addressing electrode 20 and the first selection electrode 24, is unblocked and transmits the addressing voltage V Da to the modulator 14 and to the storage capacity 16 of the first circuit 6. Since the addressing voltage V Da is greater than the trigger threshold voltage of the modulator 14, a drain current I d1 is established between the drain and the source of the modulator 14 and therefore passes through the transmitter 4 as shown in the figure 2F . The capacitor 16 stores a potential representative of the addressing voltage V Da at the gate of the modulator 14 to maintain the luminance of the transmitter 4 during a time interval corresponding to the duration of an image frame. Thus, the transmitter 4 emits light during step C until the end of the image frame.

Pendant les étapes B, C et D, on voit donc que l'émetteur 4 est alimenté en courant par le premier circuit d'adressage 6. Les étapes B, C et D forment donc ensemble une phase d'activation du premier circuit d'adressage 6.During the steps B, C and D, it is thus seen that the transmitter 4 is supplied with current by the first addressing circuit 6. The steps B, C and D thus together form an activation phase of the first circuit of FIG. addressing 6.

Pendant une étape de programmation de polarisation D du modulateur 14 du premier circuit d'adressage 6, l'unité de pilotage 28 de sélection transmet à la première électrode 24 une tension de sélection VS1. Conjointement à l'application d'une tension de sélection, l'unité de pilotage 22 d'adressage applique à l'électrode 20 une tension de polarisation Vp.During a polarization programming step D of the modulator 14 of the first addressing circuit 6, the selection control unit 28 transmits a selection voltage V S1 to the first electrode 24. In conjunction with the application of a selection voltage, the addressing control unit 22 applies a bias voltage V p to the electrode 20.

L'interrupteur de sélection 18, au croisement de la première électrode 24 et de l'électrode d'adressage 20, est débloqué et transmet cette fois la tension de polarisation Vp au modulateur 14 et à la capacité de stockage 16. La capacité de stockage se décharge et stocke les charges transmises par la tension de polarisation pendant une phase de polarisation E, F du premier circuit d'adressage 6, tel qu'illustré sur la figure 2D. Le courant de drain Id1 de la trame précédente cesse de traverser le modulateur 14. La tension de seuil du déclenchement du modulateur 14 qui a dérivé et augmenté au cours de la trame d'image va diminuer au cours de la nouvelle trame et notamment au cours de l'étape F.The selection switch 18, at the intersection of the first electrode 24 and the addressing electrode 20, is unlocked and this time transmits the bias voltage V p to the modulator 14 and the storage capacitor 16. The capacitance storage discharges and stores the charges transmitted by the bias voltage during a polarization phase E, F of the first addressing circuit 6, as shown in FIG. 2D figure . The drain current I d1 of the previous frame ceases to pass through the modulator 14. The trigger threshold voltage of the modulator 14 which has drifted and increased during the image frame will decrease during the new frame and especially at the course of step F.

La trame d'image suivante démarre par une étape de programmation d'adressage E du modulateur 34 du second circuit d'adressage 12. Pendant cette étape, l'unité de pilotage 28 de sélection applique à l'électrode 26 une tension de sélection Vs2. L'unité de pilotage d'adressage 22 applique parallèlement à l'électrode 20 une tension d'adressage VDb.The next image frame starts with an addressing programming step E of the modulator 34 of the second addressing circuit 12. During this step, the selection control unit 28 applies to the electrode 26 a selection voltage V s2 . The addressing control unit 22 applies, parallel to the electrode 20, an addressing voltage V Db .

L'interrupteur 38 du second circuit d'adressage 12 est débloqué et la tension d'adressage VDb, représentative d'une donnée d'image, est appliquée à la grille du modulateur 34 et à la borne de la capacité de stockage 36. Un courant de drain Id2 est généré entre le drain et la source du modulateur 34. Ce courant a une amplitude proportionnelle à la valeur de la donnée d'image à émettre pendant cette trame d'image. Ce courant traverse l'émetteur de lumière 4 pendant l'étape F jusqu'à la fin de la trame d'image.The switch 38 of the second addressing circuit 12 is unlocked and the addressing voltage V Db , representative of an image data, is applied to the gate of the modulator 34 and to the terminal of the storage capacitor 36. A drain current I d2 is generated between the drain and the source of the modulator 34. This current has an amplitude proportional to the value of the image data to be transmitted during this image frame. This current flows through the light emitter 4 during step F until the end of the image frame.

Pendant les étapes E et F, on voit donc que l'émetteur 4 est alimenté en courant par le second circuit d'adressage 12. Les étapes E et F forment donc ensemble une phase d'activation du second circuit d'adressage 12.During the steps E and F, it is thus seen that the transmitter 4 is supplied with current by the second addressing circuit 12. The steps E and F together form an activation phase of the second addressing circuit 12.

En conséquence, le système de commande 11 et les unités de pilotage 22 et 28 commandent l'adressage des tensions de sélection, d'adressage et de polarisation de sorte que :

  • une tension d'adressage de polarité positive, est appliquée à la grille du modulateur 14 du premier circuit d'adressage 6 pour alimenter l'émetteur 4 et consécutivement, une tension de polarisation de polarité négative est appliquée à la grille du modulateur 34 du second circuit d'adressage 12 pour compenser la dérivation de sa tension de seuil de déclenchement ;
  • puis inversement, une tension d'adressage de polarité positive, est appliquée à la grille du modulateur 34 du second circuit d'adressage 12 pour alimenter l'émetteur 4 et consécutivement, une tension de polarisation de polarité négative est appliquée à la grille du modulateur 14 du premier circuit d'adressage 6 pour compenser la dérivation de sa tension de seuil de déclenchement.
Consequently, the control system 11 and the control units 22 and 28 control the addressing of the selection, addressing and polarization voltages so that:
  • a positive polarity addressing voltage is applied to the gate of the modulator 14 of the first addressing circuit 6 to power the transmitter 4 and then, a bias voltage of negative polarity is applied to the gate of the modulator 34 of the second circuit addressing 12 to compensate for the derivation of its trigger threshold voltage;
  • then conversely, a positive polarity addressing voltage is applied to the gate of the modulator 34 of the second addressing circuit 12 to power the transmitter 4 and then, a bias voltage of negative polarity is applied to the gate of the modulator 14 of the first addressing circuit 6 to compensate for the derivation of its trigger threshold voltage.

D'une trame d'image à l'autre, l'émetteur 4 est alimenté en courant tour à tour par le premier modulateur 14 pendant une phase d'activation du premier circuit d'adressage, puis par le second modulateur 34 pendant une phase d'activation du second circuit d'adressage.From one image frame to another, the transmitter 4 is supplied with current in turn by the first modulator 14 during an activation phase of the first addressing circuit, then by the second modulator 34 during a phase activating the second addressing circuit.

Les tensions de seuil de déclenchement du modulateur 14 du premier circuit d'adressage et du modulateur 34 du second circuit d'adressage sont augmentées puis diminuées tour à tour à chaque trame d'image. Un tel dispositif permet donc avantageusement de compenser la dérive de tension de seuil de déclenchement des modulateurs du panneau.The trigger threshold voltages of the modulator 14 of the first addressing circuit and the modulator 34 of the second addressing circuit are increased and then decreased in turn at each image frame. Such a device therefore advantageously makes it possible to compensate for the trigger threshold voltage drift of the modulators of the panel.

Un émetteur 4 et les moyens de commande 40 de son émission selon un second mode de réalisation de l'invention, sont représentés sur la figure 3.An emitter 4 and the control means 40 of its transmission according to a second embodiment of the invention are represented on the figure 3 .

Dans ce mode de réalisation, les moyens de commande 40 comprennent des premiers circuits d'adressage 6 et des seconds circuits d'adressage 12, reliés chacun à une émetteur 4 du réseau, des moyens de commande d'adressage 42 d'une colonne d'émetteurs, des moyens de commande de sélection 44 d'une ligne d'émetteurs et un système de commande 56.In this embodiment, the control means 40 comprise first addressing circuits 6 and second addressing circuits 12, each connected to a transmitter 4 of the network, addressing control means 42 of a column d transmitters, selection control means 44 of a transmitter line and a control system 56.

Les premiers 6 et les seconds 12 circuits d'adressage comprennent les mêmes composants, reliés de la même façon que les circuits d'adressage décrits en relation avec la figure 1. Ils sont identifiés par les mêmes références que sur la figure 1 et ne seront plus décrits ci-après.The first 6 and the second 12 addressing circuits comprise the same components, connected in the same way as the addressing circuits described in connection with the figure 1 . They are identified by the same references as on the figure 1 and will not be described below.

Les moyens de commande 42 d'adressage comprennent une unité de pilotage d'adressage 46, une première électrode 48 d'adressage et une seconde électrode 50 d'adressage pour chaque colonne d'émetteurs. La première électrode 48 d'adressage est reliée à l'unité de pilotage 46 et au drain de l'interrupteur 18 de l'ensemble des premiers circuits d'adressage 6 d'une colonne d'émetteurs. La seconde électrode 50 d'adressage est reliée à l'unité de pilotage 46 et au drain de l'interrupteur 38 de l'ensemble des seconds circuits d'adressage 12 d'une colonne d'émetteurs.The addressing control means 42 comprise an addressing control unit 46, a first addressing electrode 48 and a second addressing electrode 50 for each column of transmitters. The first addressing electrode 48 is connected to the control unit 46 and the drain of the switch 18 of all the first addressing circuits 6 of a column of transmitters. The second addressing electrode 50 is connected to the control unit 46 and to the drain of the switch 38 of the set of second addressing circuits 12 of a column of transmitters.

L'unité de pilotage 46 d'adressage est apte à envoyer une tension d'adressage VD1 sur la première électrode 48 et de manière concomitante une tension d'adressage VD2 sur la seconde électrode 50.The addressing unit 46 for addressing is able to send an address voltage V D1 on the first electrode 48 and concomitantly an address voltage V D2 on the second electrode 50.

Les moyens de commande 44 de sélection comprennent une unité de pilotage 54 de sélection et pour chaque ligne d'émetteurs une unique électrode 52 de sélection. L'électrode 52 de sélection est connectée à l'unité de pilotage 54, à la grille de l'interrupteur 18 des premiers circuits d'adressage 6 et à la grille de l'interrupteur 38 des seconds circuits d'adressage 12 d'une ligne d'émetteurs.The selection control means 44 comprise a selection control unit 54 and, for each row of transmitters, a single selection electrode 52. The selection electrode 52 is connected to the control unit 54, to the gate of the switch 18 of the first addressing circuits 6 and to the gate of the switch 38 of the second addressing circuits 12 of a line of transmitters.

Le système de commande 56 est connecté à l'unité de pilotage 54 ainsi qu'à l'unité de pilotage 46. Ce système de commande 56 est apte à transmettre à l'unité de pilotage 46 des données numériques d'images et des données relatives à la tension de polarisation. Il est également apte à transmettre à l'unité de pilotage 54 un signal périodique de sélection.The control system 56 is connected to the control unit 54 as well as to the control unit 46. This control system 56 is able to transmit to the control unit 46 digital image data and data. relating to the bias voltage. It is also able to transmit to the control unit 54 a periodic selection signal.

Le procédé d'adressage d'un écran d'affichage selon le second mode de réalisation de l'invention est illustré sur les figures 4A à 4F.The method of addressing a display screen according to the second embodiment of the invention is illustrated on the Figures 4A to 4F .

Ce procédé comprend une étape G de programmation d'adressage de la capacité 16 et de programmation de polarisation simultanée du modulateur 34. L'unité de pilotage 46 transmet une tension d'adressage VDa représentative d'une donnée d'image à la première électrode 48 et une tension de polarisation Vp à la seconde électrode 50.This method comprises a step G of addressing addressing of the capacitor 16 and of the simultaneous polarization programming of the modulator 34. The control unit 46 transmits an address voltage V Da representative of an image data item to the first electrode 48 and a bias voltage V p to the second electrode 50.

Parallèlement, l'unité de pilotage 54 transmet une tension de sélection VS sur l'électrode de sélection 52. L'interrupteur 18 du premier circuit d'adressage et l'interrupteur 38 du second circuit de programmation sont débloqués de sorte que d'une part, la tension de polarisation Vp est appliquée à la grille du modulateur 34 et à la borne de la capacité 36 et d'autre part, la tension d'adressage VDa est appliquée à la grille du modulateur 14 et à une borne de la capacité de stockage 16.In parallel, the control unit 54 transmits a selection voltage V S to the selection electrode 52. The switch 18 of the first addressing circuit and the switch 38 of the second programming circuit are unlocked so that firstly, the bias voltage V p is applied to the gate of the modulator 34 and the terminal of the capacitor 36 and, secondly, the addressing voltage V Da is applied to the gate of the modulator 14 and to a terminal storage capacity 16.

La capacité de stockage 36 se décharge puis se charge à un potentiel négatif égal à la tension de polarisation Vp. Cette tension maintenue à la grille du modulateur 34 par la capacité de stockage 36, vise à diminuer progressivement la tension de seuil de déclenchement du modulateur 34 notamment au cours de l'étape H. Comme l'indique la courbe en pointillés de la figure 4E, le courant de drain Id2 s'annule et reste nul pendant l'étape H.The storage capacitor 36 discharges and then charges at a negative potential equal to the bias voltage V p . This voltage maintained at the gate of the modulator 34 by the storage capacitor 36, aims to progressively reduce the trigger threshold voltage of the modulator 34 in particular during the step H. As indicated by the dashed curve of the figure 4E , the drain current I d2 vanishes and remains zero during step H.

La capacité 16 se charge au potentiel VDa et un courant de drain Id1 s'établit entre le drain et la source du modulateur 14. L'émetteur 4 est alimenté par le courant Id1 pendant l'étape H jusqu'à la fin de la trame d'image.The capacitor 16 charges at the potential V Da and a drain current I d1 is established between the drain and the source of the modulator 14. The transmitter 4 is supplied with the current I d1 during the step H until the end of the image frame.

Pendant les étapes G et H, l'émetteur 4 est donc alimenté en courant par le premier circuit d'adressage 6; les étapes G et H forment donc ensemble une phase d'activation du premier circuit d'adressage. Par ailleurs, pendant les étapes G et H, la tension de polarisation est appliquée à la grille du modulateur 34 pour compenser la dérive de sa tension de seuil de déclenchement. Les étapes G et H forment donc également une phase de polarisation du second circuit d'adressage.During the steps G and H, the transmitter 4 is therefore supplied with current by the first addressing circuit 6; the steps G and H together form an activation phase of the first addressing circuit. Furthermore, during the steps G and H, the bias voltage is applied to the gate of the modulator 34 to compensate for the drift of its trigger threshold voltage. The steps G and H therefore also form a polarization phase of the second addressing circuit.

Pendant une étape I de programmation d'adressage de la capacité de stockage 36 et de programmation de polarisation simultanée du modulateur 14, l'unité de pilotage 46 transmet une tension de polarisation Vp à la première électrode 48 et une tension d'adressage VDb représentative d'une donnée d'image à la seconde électrode 50.During a step I of addressing programming of the storage capacity 36 and of the simultaneous polarization programming of the modulator 14, the control unit 46 transmits a bias voltage V p to the first electrode 48 and an address voltage V Db representative of an image data at the second electrode 50.

Les interrupteurs 18 et 38 sont simultanément ouverts par application de la tension de sélection VS à l'électrode 52. La tension de polarisation Vp est transmise à la grille du modulateur 14 et à la borne de la capacité 16. La capacité 16 se décharge puis se charge négativement. Comme l'indique la courbe en trait plein de la figure 4E, le courant de drain Id1 s'annule et reste nul pendant l'étape J.The switches 18 and 38 are simultaneously open by applying the selection voltage V S to the electrode 52. The bias voltage V p is transmitted to the gate of the modulator 14 and to the terminal of the capacitor 16. The capacitor 16 is discharge and then charge negatively. As indicated by the solid line curve of the figure 4E , the drain current I d1 vanishes and remains zero during step J.

Pendant les étapes I et J, la tension de polarisation Vp est appliquée à la grille du modulateur 14. Les étapes I et J, forment donc ensemble une phase de polarisation du premier circuit d'adressage 6.During the steps I and J, the bias voltage V p is applied to the gate of the modulator 14. The steps I and J together form a polarization phase of the first addressing circuit 6.

Conjointement, la tension d'adressage VDb est appliquée à la grille du modulateur 34 et à une borne de la capacité 36. Cette tension, maintenue à la grille du modulateur 34 par la capacité 36, génère un courant de drain Id2 qui alimente l'émetteur 4 pendant l'étape J et jusqu'à la prochaine étape de programmation d'une nouvelle donnée d'image.At the same time, the addressing voltage V Db is applied to the gate of the modulator 34 and to a terminal of the capacitor 36. This voltage, maintained at the gate of the modulator 34 by the capacitor 36, generates a drain current I d2 which feeds transmitter 4 during step J and up to the next step of programming new image data.

Pendant les étapes I et J, l'émetteur 4 est alimenté en courant par le second circuit d'adressage 12 ; ces étapes forment donc ensemble une phase d'activation du second circuit d'adressage.During the steps I and J, the transmitter 4 is supplied with current by the second addressing circuit 12; these steps together form an activation phase of the second addressing circuit.

En conséquence, le système de commande 56 et les unités de pilotage 46 et 54 commandent l'adressage des tensions de sélection, d'adressage et de polarisation de sorte que :

  • une tension d'adressage de polarité positive, est appliquée à la grille du modulateur 14 du premier circuit d'adressage 6 pour alimenter l'émetteur 4 et simultanément, une tension de polarisation de polarité négative est appliquée à la grille du modulateur 34 du second circuit d'adressage 12 pour compenser la dérive de sa tension de seuil de déclenchement ;
  • puis inversement, une tension d'adressage de polarité positive est appliquée à la grille du modulateur 34 du second circuit d'adressage 12 pour alimenter l'émetteur 4 et simultanément, une tension de polarisation de polarité négative est appliquée à la grille du modulateur 14 du premier circuit d'adressage 6 pour compenser la dérive de sa tension de seuil de déclenchement.
Consequently, the control system 56 and the control units 46 and 54 control the addressing of the selection, addressing and polarization voltages so that:
  • a positive polarity addressing voltage is applied to the gate of the modulator 14 of the first addressing circuit 6 to power the transmitter 4 and simultaneously, a bias voltage of negative polarity is applied to the gate of the modulator 34 of the second addressing circuit 12 to compensate for the drift of its trigger threshold voltage;
  • then conversely, a positive polarity addressing voltage is applied to the gate of the modulator 34 of the second addressing circuit 12 to power the transmitter 4 and simultaneously, a bias voltage of negative polarity is applied to the gate of the modulator 14 of the first addressing circuit 6 to compensate for the drift of its trigger threshold voltage.

L'émetteur 4 est ainsi alimenté tour à tour par le courant modulé, par le modulateur 14, puis par le modulateur 34.The emitter 4 is thus supplied in turn by the modulated current, by the modulator 14, then by the modulator 34.

Les premier 6 et second 12 circuits d'adressage sont alternativement activés pour alimenter en courant l'émetteur 4.The first 6 and second 12 addressing circuits are alternately activated to power the transmitter 4.

Quand le modulateur 14 alimente l'émetteur 4, le modulateur 34 est polarisé par application à sa grille d'une tension de polarisation correspondant à une tension négative élevée pour que la tension de seuil de déclenchement du modulateur 34 dérivée au cours de la phase précédente retrouve sa valeur initiale.When the modulator 14 supplies the transmitter 4, the modulator 34 is polarized by applying a bias voltage corresponding to a high negative voltage to its gate so that the tripping threshold voltage of the modulator 34 derived during the previous phase returns to its initial value.

Inversement, quand le modulateur 34 alimente l'émetteur 4, le modulateur 14 est polarisé par cette même tension de polarisation négative pour que sa tension de seuil de déclenchement ayant au préalable dérivé dans un sens, dérive dans un sens opposé. Ainsi, l'implantation de deux circuits d'adressage associé à chaque émetteur contribue à compenser les variations de seuil de déclenchement des modulateurs d'un écran d'affichage.Conversely, when the modulator 34 supplies the transmitter 4, the modulator 14 is biased by this same negative bias voltage so that its trigger threshold voltage having previously drifted in one direction, drifts in an opposite direction. Thus, the establishment of two circuits The addressing method associated with each transmitter contributes to compensating for variations in the tripping threshold of the modulators of a display screen.

Dans les modes de réalisation décrits, les phases de polarisation et d'activation sont réalisées simultanément et ont des durées égales. En variante, les moyens de commandes sont également aptes à commander les modulateurs 14 et 34 pour que les phases de polarisation et d'activation des premier et second circuits, bien que réalisées simultanément, aient des durées différentes.In the embodiments described, the polarization and activation phases are carried out simultaneously and have equal durations. Alternatively, the control means are also able to control the modulators 14 and 34 so that the polarization and activation phases of the first and second circuits, although performed simultaneously, have different durations.

Selon un mode de réalisation préférentiel, la tension de polarisation appliquée à l'un ou à l'autre des modulateurs d'un émetteur varie d'une trame d'image à l'autre, en fonction de la tension d'adressage appliquée à ce modulateur lors de la trame précédente ; de préférence, cette tension de polarisation est égale mais de signe opposé à ladite tension d'adressage de la trame précédente.According to a preferred embodiment, the bias voltage applied to one or the other of the modulators of a transmitter varies from one image frame to another, as a function of the addressing voltage applied to the this modulator during the previous frame; preferably, this bias voltage is equal but of opposite sign to said addressing voltage of the previous frame.

Claims (9)

  1. Image display screen comprising:
    - light emitters (4) distributed along emitter lines and emitter columns to form an emitter network,
    - means for controlling (2, 6, 8, 10, 12; 40, 42, 44) the emission of the emitters of the network comprising:
    a) for each emitter (4), a first addressing circuit (6) for controlling current passing through said emitter (4), said circuit (6) comprising:
    - a first transistor (14) for modulating current of said emitter (4), having a gate electrode, a source electrode and a drain electrode;
    - a first storage capacity (16) capable of storing a voltage between the gate electrode of source of said first transistor (14),
    b) for each emitter (4), at least one second addressing circuit (12) of said emitter, said first (6) and second (12) addressing circuits being mounted parallel to the same emitter (4), said second circuit (12) comprising:
    - a second transistor (34) for modulating current of said emitter (4), having a gate electrode, a source electrode and a drain electrode;
    - a second storage capacity (36) capable of storing a voltage between the gate electrode of source of said second transistor (34);
    c) means for controlling addressing (8, 11, 20, 22; 42, 46, 48, 50, 56):
    c1) which are adapted to selectively activate the first (6) or the second (12) addressing circuits such that, from one frame to the other of said images, each emitter (4) is supplied turn to turn by the first transistor (14) during an activation phase (B, C; G, H) of the first addressing circuit, then by the second transistor (34) during an activation phase (E, F; I, J) of the second addressing circuit,
    c2) which are capable of applying to the terminals of said first storage capacity (16) and between the gate electrode and the source electrode of said first transistor (14) first an addressing voltage (VD; DD1, VD2) representative of an item of data of one of the image frames to start said activation phase (B, C; G, H) of the first addressing circuit (6) and supplying the emitter (4) into a current, having, during said frame, an amplitude proportional to the value of said item of data, and then a polarisation voltage (Vp) to start a polarisation phase (D, F; I, J) of the first addressing circuit (6), and
    c3) which are capable of applying to the terminals of said second storage capacity (36) and between the gate electrode and the source electrode of said second transistor (34) first an addressing voltage (VD, DD1, VD2) representative of an item of data of the other image frame to start said activation phase (E, F; I, J) of the second addressing circuit (12) and supplying the emitter (4) with a current, having, during said frame, an amplitude proportional to the value of said item of data, then the polarisation voltage (Vp) to start a polarisation phase (A, C; G, H) of the second addressing circuit (12); where said polarisation voltage has a polarity inverse to the polarity of said addressing voltage, where the activation phase (B, C; G, H) of the first addressing circuit (6) is carried out at the same time as the polarisation phase (A, C; G, H) of the second addressing circuit (12), and where the activation phase (E, F; I, J) of the second addressing circuit (12) is carried out at the same time as the polarisation phase (D, F; I, J) of the first addressing circuit (6).
  2. Display screen according to claim 1, characterised in that the transistors (14, 34) for modulating current are thin-layer transistors made of hydrogenated amorphous silicon.
  3. Display screen according to claim 1 or 2, characterised in that the control means comprise means for controlling selection (10, 11, 24, 26, 28; 44, 52, 54, 56) comprising:
    - for each first addressing circuit (6) of an emitter, a first selection switch (18) capable of transmitting said addressing voltage (VD; VD1, VD2) or said polarisation voltage at the terminals of said first storage capacity (16) and between the gate electrode and the source electrode of said first current modulator (14), according to a selection voltage (VS1, VS2; VS) to select said emitter (4);
    - for each second addressing circuit (12) of the same emitter, a second selection switch (38) capable of transmitting said addressing voltage (VD; VD1, VD2) or said polarisation voltage at the terminals of said second storage capacity (36) and between the gate electrode and the source electrode of said second current modulator (34), according to said selection voltage (VS1, VS2; VS) to select said emitter (4); and
    - means for controlling (11, 24, 26, 28; 52, 54, 56) of the first (18) and second (38) selection switches.
  4. Display screen according to claim 3, characterised in that the control means (11, 24, 26, 28) further comprise:
    - for each line of emitters, first (24) and second (26) selection electrodes connected respectively to the first (18) and second (38) selection switches for the control thereof; and
    - a unit for controlling (28) selection, capable of transmitting alternatively, first said selection voltage (VS1) to said first selection electrode (24), then said selection voltage (VS2) to said second selection electrode (26).
  5. Display screen according to claim 4, characterised in that the addressing control means (8, 20, 22) comprise:
    - an addressing electrode (20) for each emitter column, the first (18) and the second (38) selection switches being connected to said addressing electrode (20); and
    - an addressing control unit (22) capable of sending alternatively said addressing voltage (VD) and said polarisation voltage (Vp) on said addressing electrode (20).
  6. Display screen according to claim 3, characterised in that the control means (52, 54, 56) further comprise:
    - a selection electrode (52) for each emitter line, the first (18) and second (38) selection switches being connected to said selection electrode (52) for the control thereof; and
    - a selection control unit (54) capable of sending said selection voltage (VS) concurrently to the first (18) and second (38) selection switches.
  7. Display screen according to claim 6, characterised in that the addressing control means (42, 46, 48, 50) comprise:
    - for each emitter column, first (48) and second (50) addressing electrodes connected respectively to the first (18), and second (38) selection switches; and
    - an addressing control unit (46) capable of sending concurrently on the first addressing electrode (48) and on the second addressing electrode (50), said addressing voltage (VD1) or said polarisation voltage (Vp) .
  8. Method for addressing an image display screen comprising light emitters (4), a first (6) and a second (12) addressing circuits that can be activated selectively, the first addressing circuit (6) comprising a first transistor (14) for modulating current connected to an emitter (4) and having a gate electrode, a source electrode and a drain electrode, a first (16) storage capacity capable of storing a voltage between the gate electrode and the source electrode of the first transistor (14), said second addressing circuit (12) comprise a second transistor (34) for modulating current connected to said emitter (4) and having a gate electrode, a source electrode and a drain electrode, a second (36) storage capacity capable of storing a voltage between the gate electrode and the source electrode of the second transistor (34),
    said method comprising, from one frame to the other of said images and for controlling each emitter (4) :
    - an activation phase (B, C; G, H) of the first addressing circuit (6) to supply the emitter (4) with a current having, during one of the frames, an amplitude proportional to the value of an item of data of this frame alternating turn by turn with an activation phase (E, F; I, J) of the second addressing circuit (12) to supply the emitter (4) with a current having, during the other frame, an amplitude proportional to the value of an item of data of this frame;
    - a polarisation phase (D, F; I, J) of the first addressing circuit (6) and a polarisation phase (A, C; G, H) of the second addressing circuit (12);
    - to start (B; G) said activation phase of the first addressing circuit (6), the application at the terminals of said first storage capacity (16) and between the gate electrode and the source electrode of said first transistor (14) of an addressing voltage (VD, DD1, VD2) representative of the item of data of a frame,
    - to start (E, I) said activation phase of the second addressing circuit (12), the application at the terminals of said second storage capacity (36) and between the gate electrode and the source electrode of said second transistor (34) of an addressing voltage (VD, DD1, VD2) representative of the item of data of the other frame,
    - to start (D; I) said polarisation phase of the first addressing circuit (6), the application at the terminals of said first storage capacity (16) and between the gate electrode and the source electrode of said first transistor (14) of a polarisation voltage (Vp) of polarity, inverse to the polarity of said addressing voltage,
    - to start (A; G) said polarisation phase of the second addressing circuit (12), the application at the terminals of said second storage capacity (36) and between the gate electrode and the source electrode of said second transistor (34) of a polarisation voltage (Vp) of polarity inverse to the polarity of said addressing voltage,
    where the activation phase (B, C; G, H) of the first addressing circuit (6) is carried out at the same time as the polarisation phase (A, C; G, H) of the second addressing circuit (12) and where the activation phase (E, F; I, J) of the second addressing circuit (12) is carried out at the same time as the polarisation phase (D, F; I, J) of the first addressing circuit (6).
  9. Addressing method according to claim 1, characterised in that the polarisation voltage (Vp) applied to either one of the transistors (14, 34) for modulating current of an emitter varies from one image frame to the other, according to the addressing voltage applied to this modulator during the preceding frame.
EP04805623.8A 2003-12-31 2004-12-02 Image display screen and method of addressing said screen Ceased EP1700290B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0315629 2003-12-31
PCT/FR2004/003104 WO2005073948A1 (en) 2003-12-31 2004-12-02 Image display screen and method of addressing said screen

Publications (2)

Publication Number Publication Date
EP1700290A1 EP1700290A1 (en) 2006-09-13
EP1700290B1 true EP1700290B1 (en) 2019-01-16

Family

ID=34814552

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04805623.8A Ceased EP1700290B1 (en) 2003-12-31 2004-12-02 Image display screen and method of addressing said screen

Country Status (5)

Country Link
EP (1) EP1700290B1 (en)
JP (1) JP5074769B2 (en)
KR (1) KR101205912B1 (en)
CN (1) CN100456346C (en)
WO (1) WO2005073948A1 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101066414B1 (en) * 2004-05-19 2011-09-21 재단법인서울대학교산학협력재단 Driving element and driving method of organic light emitting device, and display panel and display device having the same
JP5121118B2 (en) * 2004-12-08 2013-01-16 株式会社ジャパンディスプレイイースト Display device
KR101142996B1 (en) 2004-12-31 2012-05-08 재단법인서울대학교산학협력재단 Display device and driving method thereof
FR2895131A1 (en) 2005-12-20 2007-06-22 Thomson Licensing Sas DISPLAY PANEL AND CONTROL METHOD WITH TRANSIENT CAPACITIVE COUPLING
FR2895130A1 (en) 2005-12-20 2007-06-22 Thomson Licensing Sas METHOD FOR CONTROLLING A CAPACITIVE COUPLING DISPLAY PANEL
FR2900492B1 (en) * 2006-04-28 2008-10-31 Thales Sa ORGANIC ELECTROLUMINESCENT SCREEN
EP1863005B1 (en) * 2006-06-01 2010-08-04 Thomson Licensing Video display device and operating method therefore
EP1863001A1 (en) 2006-06-01 2007-12-05 Thomson Licensing Video display device and operating method therefore
US9116593B2 (en) 2007-07-06 2015-08-25 Qualcomm Incorporated Single-axis window manager
JP5178492B2 (en) * 2007-12-27 2013-04-10 株式会社半導体エネルギー研究所 Display device and electronic apparatus including the display device
KR100939211B1 (en) 2008-02-22 2010-01-28 엘지디스플레이 주식회사 Organic Light Emitting Diode Display And Driving Method Thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001034231A (en) * 1999-07-22 2001-02-09 Seiko Epson Corp El display device
EP1111574A2 (en) * 1999-12-24 2001-06-27 Sel Semiconductor Energy Laboratory Co., Ltd. Electroluminescent display device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5714968A (en) * 1994-08-09 1998-02-03 Nec Corporation Current-dependent light-emitting element drive circuit for use in active matrix display device
JP2689916B2 (en) * 1994-08-09 1997-12-10 日本電気株式会社 Active matrix type current control type light emitting element drive circuit
JP3308880B2 (en) * 1997-11-07 2002-07-29 キヤノン株式会社 Liquid crystal display and projection type liquid crystal display
US20020030647A1 (en) * 2000-06-06 2002-03-14 Michael Hack Uniform active matrix oled displays
JP3877049B2 (en) * 2000-06-27 2007-02-07 株式会社日立製作所 Image display apparatus and driving method thereof
KR100370095B1 (en) * 2001-01-05 2003-02-05 엘지전자 주식회사 Drive Circuit of Active Matrix Formula for Display Device
TW518528B (en) * 2001-01-08 2003-01-21 Chi Mei Optoelectronics Corp Driving method of active matrix electro-luminescent display
US6858989B2 (en) * 2001-09-20 2005-02-22 Emagin Corporation Method and system for stabilizing thin film transistors in AMOLED displays
KR100489272B1 (en) * 2002-07-08 2005-05-17 엘지.필립스 엘시디 주식회사 Organic electroluminescence device and method for driving the same
TWI254898B (en) * 2003-10-02 2006-05-11 Pioneer Corp Display apparatus with active matrix display panel and method for driving same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001034231A (en) * 1999-07-22 2001-02-09 Seiko Epson Corp El display device
EP1111574A2 (en) * 1999-12-24 2001-06-27 Sel Semiconductor Energy Laboratory Co., Ltd. Electroluminescent display device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HACK M ET AL: "Drain-Bias Dependence of Threshold Voltage Stability of Amorphous Silicon TFTs", IEEE ELECTRON DEVICE LETTERS, IEEE SERVICE CENTER, NEW YORK, NY, US, vol. 25, no. 4, 1 April 2004 (2004-04-01), pages 188 - 190, XP011109652, ISSN: 0741-3106, DOI: 10.1109/LED.2004.825154 *
KIM J H ET AL: "THRESHOLD VOLTAGE SHIFT OF AMORPHOUS SILICON THIN FILM TRANSISTORS WITH ATMOSPHERIC PRESSURE CHEMICAL VAPOR DEPOSITION SILICON DIOXIDE", APPLIED PHYSICS LETTERS, A I P PUBLISHING LLC, US, vol. 64, no. 18, 2 May 1994 (1994-05-02), pages 2362/2363, XP000440965, ISSN: 0003-6951, DOI: 10.1063/1.111615 *

Also Published As

Publication number Publication date
EP1700290A1 (en) 2006-09-13
CN1902675A (en) 2007-01-24
JP5074769B2 (en) 2012-11-14
WO2005073948A1 (en) 2005-08-11
JP2007519949A (en) 2007-07-19
KR20060135670A (en) 2006-12-29
KR101205912B1 (en) 2012-11-28
CN100456346C (en) 2009-01-28

Similar Documents

Publication Publication Date Title
EP1644913B1 (en) Display device and control circuit for a light modulator
EP2013863B1 (en) Organic electroluminescent display
EP1851747B1 (en) Pixel addressing circuit and method of controlling such circuit
EP1700290B1 (en) Image display screen and method of addressing said screen
FR2884639A1 (en) ACTIVE MATRIX IMAGE DISPLAY PANEL, THE TRANSMITTERS OF WHICH ARE POWERED BY POWER-DRIVEN POWER CURRENT GENERATORS
WO2005086130A1 (en) Device for improving pixel addressing
FR2816095A1 (en) DRIVING METHOD AND DRIVING CIRCUIT OF A PLASMA DISPLAY PANEL
EP2277164B1 (en) Improved display device based on pixels with variable chromatic coordinates
EP1964093A1 (en) Method of driving a display panel with depolarization
EP1964095B1 (en) Display panel and control method using transient capacitive coupling
EP1964094B1 (en) Method for controlling a display panel by capacitive coupling
EP1771838B1 (en) Image display device and display device control method
EP1864275B1 (en) Image display device and method of controlling same
EP1697920B1 (en) Device for displaying images on an oled active matrix
EP1697919B1 (en) Image display screen
EP1697997B1 (en) Image display screen and method for controlling said screen
FR2843225A1 (en) Active matrix image display device with compensation for trigger thresholds, uses measurement of current drawn by pixel driver to determine its threshold voltage and generates correction to command voltage to match threshold voltage
MXPA06007404A (en) Image display screen and method of addressing said screen

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20060419

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB

DAX Request for extension of the european patent (deleted)
RBV Designated contracting states (corrected)

Designated state(s): DE FR GB

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: THOMSON LICENSING

17Q First examination report despatched

Effective date: 20100730

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

INTG Intention to grant announced

Effective date: 20180808

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602004053648

Country of ref document: DE

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602004053648

Country of ref document: DE

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20191017

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 602004053648

Country of ref document: DE

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20191202

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20200701

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20191231

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20191202