KR20060135670A - Image display screen and method of addressing said screen - Google Patents

Abstract

The invention relates to a display screen comprising: light emitters (4) which are distributed in rows and columns of emitters; and a first addressing circuit (6, 14, 16, 18) which is associated with each emitter of the network, said circuit (6) comprising a first current modulator (14) which can power the emitter (4) and a first storage capacity (16) which can store a potential at the grid electrode of the first current modulator (14). The inventive screen comprises at least one second emitter addressing circuit (12, 34, 36, 38), said first and second addressing circuits being associated with the same emitter. In addition, the second circuit comprises a second current modulator (34) for the emitter and a second storage capacity (36) which can store a potential at the grid electrode of the second current modulator. The invention also relates to a method of addressing the screen.

Description

Image display screen and how to address this screen {IMAGE DISPLAY SCREEN AND MEHOD OF ADDRESSING SAID SCREEN}

The present invention relates to an image display screen and an addressing method for the screen.

In particular, the present invention is directed to a display of the type based on organic electroluminescent materials having an active matrix etched on amorphous silicon (a-Si).

Hydrogenated amorphous silicon thin film transistors offer advantages over polycrystalline silicon (p-Si) thin film transistors in screen designs based on organic electroluminescent materials because they are easier to manufacture and are uniform on relatively significant samples. This is because it represents luminance.

However, the trigger threshold voltage of the amorphous silicon transistor varies over time during the delayed application of the voltage between the gate of this transistor and the source of the transistor.

This change in the trigger threshold voltage causes an image display process on the screen and a change in brightness of the screen over time.

In particular, in the document US2003 / 052614, during each image frame, addressing representing image data, using one identical circuit for addressing this light emitter to the current modulator of each light emitter on this screen, There is a known screen of the type mentioned above, comprising addressing control means intended to alternately apply a voltage and a voltage having a polarity opposite to that of the addressing voltage.

However, this architecture and this drive mode can cause a decrease in screen brightness and flicker effects on the screen because the emission duration is reduced during each frame.

In particular, US 6 011 529 (in particular see FIG. 9) and WO 2004/051617 documents, during each image frame, a plurality of addresses for addressing this light emitter to the current modulator of each light emitter of this screen. There is a known screen of the above-mentioned type, comprising addressing control means intended to apply an addressing voltage which always represents image data having the same polarity, using at least one of the circuits of.

It is an object of the present invention to propose an alternative screen which exhibits a low luminance change over time.

To this end, the subject of the present invention is:

A light emitter, distributed in a light emitter row and a light emitter column to form a light emitter array,

Means for controlling the emission of the light emitter array,

a) a first circuit, coupled with each array of light emitters to control the current flowing through the light emitters, for addressing the light emitters, the circuit comprising:

A first current modulator, intended for driving said light emitter, comprising a gate electrode and two current-carrying electrodes,

A first storage capacitor intended for setting a potential at the gate electrode of the first current modulator

Including, the first circuit,

b) for each optical emitter, at least a second circuit for addressing the optical emitter, wherein the first addressing circuit and the second addressing circuit are coupled in parallel with the same optical emitter; The circuit is,

A second current modulator for said light emitter comprising a gate electrode and two current-carrying electrodes,

A second storage capacitor intended for storing the potential at the gate electrode potential of the second current modulator

Including, the second circuit,

c) addressing control means intended for applying an addressing voltage at the first storage capacitor and at the second storage capacitor, wherein the addressing voltage represents image data and emits current according to the image data. Addressing control means, intended to operate the first addressing circuit or the second addressing circuit for supplying

Emission control means of the light emitter array, including

It is a video display screen comprising a.

This screen is characterized in that an addressing control means is intended to set a bias voltage at the first current modulator or at the second current modulator, the bias voltage having a polarity opposite to that of the addressing voltage.

According to a particular embodiment, this display screen includes one or more of the following characteristics;

The addressing control means first applying an addressing voltage to the first current modulator to start the step for operating the first addressing circuit, and then starting the biasing voltage to bias the first addressing circuit Is intended to apply;

The addressing control means first applies an addressing voltage to the second current modulator to start the step for operating the second addressing circuit and then starts the step of biasing the second addressing circuit Intended to authorize; The act of operating the first addressing circuit occurs concurrently with the act of biasing the second addressing circuit, and the act of operating the second addressing circuit occurs simultaneously with the act of biasing the first addressing circuit. do;

Control means, for each first addressing circuit for an optical emitter, said gate of said first current modulator and said first of said addressing voltage or of said bias voltage to select said optical emitter; A first select switch intended to drive a transmission to the storage capacitor as a function of the select voltage;

For each second addressing circuit for the same optical emitter, of the addressing voltage or of the bias voltage, to the gate and the second storage capacitor of the second current modulator to select the light emitter A second select switch, intended for driving a transmission as a function of said select voltage; And

Means for driving a first selection switch and a second selection switch;

It includes;

The drive means comprises, for each row of light emitters, a first select electrode and a second select electrode respectively connected to the first switch and the second switch for controlling the first select electrode and the second select electrode; And

A selection drive unit intended to alternately transmit said selection voltage to said first selection electrode and then said selection voltage to said second selection electrode

It further includes;

The addressing control means is an addressing electrode for each light emitter row, the addressing electrode to which a first selection switch and a second selection switch are connected, and the addressing voltage and the bias voltage are alternately replaced with the addressing electrode; An addressing drive unit intended to be sent to a designation electrode;

The drive means is a selection electrode for each row of light emitters, the selection electrode to which the first selection switch and the second selection switch are connected for controlling the selection electrode, and the selection voltage being set by the first selection switch and Further comprising a selection drive unit intended to be sent simultaneously to the two selection switches;

Addressing control means, for each light emitter row, a first addressing electrode and a second addressing electrode connected to the first selection switch and the second selection switch, respectively, and on the first addressing electrode and the second; And an addressing drive unit intended to send said addressing voltage or said bias voltage simultaneously on an addressing electrode.

Another subject of the invention is an addressing method for this type of display screen, for driving each optical emitter,

Operating the first addressing circuit to supply current to the light emitter;

Biasing the second addressing circuit to change the trigger threshold voltage of the second modulator;

Actuating a second addressing circuit to supply current to the light emitter;

Biasing the first addressing circuit to change a trigger threshold voltage of the first modulator

Wherein the act of operating the first addressing circuit occurs concurrently with the act of biasing the second addressing circuit, and the act of operating the second addressing circuit comprises: biasing the first addressing circuit. It is characterized in that it occurs simultaneously with the step.

According to a particular embodiment, the display method comprises one or more of the following characteristics;

One or more steps for operating the first addressing circuit are followed by at least one step for biasing the first addressing circuit, and one or more steps for operating the second addressing circuit are biased for the second addressing circuit. Followed by at least one step;

-This way,

Addressing programming for the first storage capacitor by applying an addressing voltage representative of the image data to the capacitor;

A bias programming step for the first current modulator by applying a bias voltage to the modulator, the bias voltage having a polarity opposite to that of the potential stored by the first storage capacitor;

-Bias programming for the second current modulator by applying the bias voltage to the modulator; And

An addressing programming step for said second storage capacitor by applying said addressing voltage to said capacitor;

A bias programming step for the first current modulator is followed by an addressing programming step for a second storage capacitor, and alternately a bias programming step for the second current modulator is followed by an addressing programming step for the first storage capacitor. Follows; And

The bias programming step for the second current modulator occurs concurrently with the addressable programming step for the first storage capacitor, and the bias programming step for the first current modulator is performed on the second storage capacitor. It occurs concurrently with the addressing programming phase.

The invention will be better understood upon reading the following description, which is provided by way of example and with reference to the drawings.

1 is a schematic diagram showing a light emitter and means for controlling the emission of such a light emitter of a screen according to a first embodiment of the invention;

2 (a) to 2 (f) are diagrams illustrating changes over time of various voltages and currents according to a course of an addressing method executed by a device according to the present invention, in particular,

2 (a) is a diagram illustrating a selection voltage applied to the first selection electrode;

2B is a diagram showing a voltage applied to the second selection electrode;

2 (c) is a diagram showing a voltage applied to an addressing electrode;

2 (d) shows a voltage applied across the terminal of the first storage capacitor and a voltage applied across the terminal of the second storage capacitor;

FIG. 2 (e) shows the drain current flowing through the first current modulator and the drain current flowing through the second current modulator;

2 (f) is a diagram showing the current flowing through the light emitter.

3 is a schematic diagram showing a light emitter and means for controlling the emission of such a light emitter of a screen according to a second embodiment of the invention.

4 (a) to 4 (f) are diagrams illustrating the time-dependent conversion of various voltages and currents according to the course of the addressing method executed by the device according to the second embodiment of the present invention.

4A is a diagram illustrating a selection voltage applied to a selection electrode;

4B is a diagram showing a voltage applied to the first addressing electrode;

4C is a diagram illustrating a voltage applied to a second addressing electrode;

4 (d) shows a voltage across a terminal of a first storage capacitor and a voltage across a terminal of a second storage capacitor;

4 (e) shows a drain current flowing through the first current modulator and a drain current flowing through the second current modulator;

4 (f) is a diagram showing the current flowing through the light emitter.

The display screen according to the invention is an active matrix screen comprising light emitters distributed in rows and columns to form an array of light emitters.

The light emitter of the display screen is an organic light emitting diode, known as the abbreviation (OLED). Each emitter is combined with one pixel when the screen is monochromatic and a subpixel when the screen is multicolored. The emitter emits luminous intensity that is directly proportional to the current flowing through it.

1 shows a means 2 for controlling the emission of an array of light emitters 4 according to a first embodiment of the invention. For simplicity, only means for controlling the addressing of a single light emitter are illustrated in this figure.

The control means 2 control the selection of the first addressing circuit 6 connected to the array of light emitters 4, the addressing control means 8 for controlling the addressing of the light emitter columns, the selection of the light emitter rows. A second addressing circuit 12 also connected to the selection control means 10, the control system 11 and the light emitter 4.

The first addressing circuit 6 includes a current modulator 14, a storage capacitor 16 and a select switch 18.

The modulator 14 and the switch 18 are hydrogenated amorphous silicon thin film transistors. More specifically, these are n-type transistors. These include drains, gates, and sources, and are intended to cause current to flow from their drains to their sources when voltages greater than or equal to their trigger threshold voltage are applied between their gates and their sources. .

Alternatively, p-type transistors may be used. In this case, transistors 14 and 18 are intended to allow current to flow from their source to their drain.

The drain of the modulator 14 is connected to the cathode of the light emitter 4. The anode of the light emitter 4 is connected to a DC voltage V _dd generator intended for powering the light emitter. The source of modulator 14 is connected to the ground electrode or to a negative voltage. The gate of the modulator 14 is connected to the source of the switch 18 and to the terminal of the storage capacitor 16. The remaining terminal of the capacitor 16 is connected to the ground electrode. The gate of the switch 18 is connected to the selection control means 10 and the drain of the switch is connected to the addressing control means 8.

The addressing control means 8 for the light emitter row comprises an addressing electrode 20 and an addressing drive unit 22 for each light emitter row. The electrode 20 is connected to the drive unit 22 and to the drain of the switch 18 of the first addressing circuit 6 for the light emitter column.

The selection control means 10 comprises a first selection electrode 24 and a second selection electrode 26 for each row of light emitters, and a selection drive unit 28. The first select electrode 24 is connected to the drive unit 28 and to the gate of the switch 18 of the first addressing circuit 6 for the light emitter row. The second electrode 26 is connected to the drive unit 28 and to the gate of the switch 38 of the second addressing circuit 12 for the light emitter row.

The control system 11 is connected to the addressing drive unit 22 and to the selection drive unit 28.

The second addressing circuit 12 includes the same components as the first addressing circuit 6, namely the current modulator 34, the storage capacitor 36 and the selection switch 38. These components are interconnected in the same manner as in the first addressing circuit 6 and will not be described in detail.

Specifically, the current modulator 34 of the second addressing circuit 12 is connected at the node 32 to the cathode of the light emitter 4. The drain of the switch 38 is connected to the same addressable electrode 20 as the switch 18 and the gate of the switch is connected to the second select electrode 26.

The control system 11 is intended to transmit digital image data and bias voltage related data to the drive unit 22 and to transmit a periodic selection signal to the drive unit 28 at a predetermined frequency.

The addressing drive unit 22 is intended to transmit an addressing voltage V _D representing the image data to all the light emitter rows via the electrode 20. The addressing drive unit 22 is also intended to apply a voltage, called a bias voltage V _P , to the electrode 20 with a polarity opposite to that of the addressing voltage. This voltage is a predetermined negative voltage with a predetermined duration. Preferably, the bias voltage V _P is between -2V and -25V. In general, the reverse or negative bias voltage refers to the potential difference (V _gs ) between the gate electrode and the source electrode of the modulator less than 0V, that is, V _gs <0V.

The drive unit 28 is adapted to the gate of the modulator 14 of the first addressing circuit 6 or to the gate of the second addressing circuit 12 of the addressing voltage V _D and of the bias voltage V _P. To enable the application of 34 to the gate, the periodic select voltages V _S1 , V _S2 are equal to, or equal to, the gate of the switch 18 of the first addressing circuit 6 for the light emitter row. It is intended to apply to the gate of the switch 38 of the second addressing circuit 12 for the light emitter row.

2 (a) to 2 (f) illustrate a method of addressing a display screen according to the first embodiment of the present invention.

The method includes a bias programming step A for the modulator 34 of the second addressing circuit 12. The selection drive unit 28 transmits the selection voltage V _S2 to the second selection electrode 26, as illustrated in FIG. 2B. The selection switch 38 is released by the application of this selection voltage V _S2 to the gate.

At the same time, the addressing drive unit 22 applies the bias voltage V _P of the cathode V _gs <0 to the addressing electrode 20. The bias voltage V _P is applied at the gate of the current modulator 34 and at the terminal of the storage capacitor 36. The drain current I _{d2 that} was flowing through the modulator 34 to drive the light emitter 4 during the previous frame is now directed to zero during this new frame as shown by the dashed line graph in FIG. 2 (e).

At the same time, the storage capacitor 36 which previously stored the voltage V _D applied during the previous frame is polarized to the bias voltage V _P , as illustrated in FIG. 2 (d); As the dashed line graph in this figure shows, the storage capacitor 36 remains at the gate of the modulator 34 during the biasing step for the second address designating circuit 12 and until the end of the next programming step for the modulator 34. Maintain the bias voltage. All of the steps B, C and D form a step for biasing the second addressing circuit 12.

The trigger threshold voltage of the modulator 34, which has undergone a change through the application of an addressing voltage during the previous image frame, is applied through the application of the bias voltage V _P , but in the opposite direction to the previous change, during the bias phase and over the new frame. Change again.

The bias voltage applied at the gate of modulator 34 during the new frame reverses the change in trigger threshold voltage and restores the trigger threshold voltage to its initial value, that is, the value it had before changing through the application of an addressing voltage at the gate during the previous frame. Has the effect.

During the addressing programming step (B) for the modulator 14 of the first addressing circuit 6, the selection driving unit 28 generates a selection voltage V _{S1 and} applies this voltage to the first electrode 24. Is authorized.

At the same time, the addressing drive unit 22 transmits an addressing voltage V _Da representing the image data to the addressing electrode 20. The selection switch 18 at the intersection of the addressing electrode 20 and the first selection electrode 24 is released to transfer the addressing voltage V _Da to the modulator 14 and to the first addressing circuit 6. Transmit to the storage capacitor 16. Since the addressing voltage V _Da is greater than the trigger threshold voltage of the modulator 14, the drain current I _d1 is established between the drain and the source of the modulator 14, as illustrated in FIG. 2 (f). Flow through the light emitter 4. Capacitor 16 stores a potential representing an addressing voltage V _Da at the gate of modulator 14 to maintain the brightness of light emitter 4 at a time interval corresponding to the duration of the image frame. Thus, the light emitter 4 emits light during step C to the end of the image frame.

It is thus recognized that during steps B, C and D, the current is supplied to the optical emitter 4 by the first addressing circuit 6. Thus steps B, C and D together form a step for operating the first addressing circuit 6.

During the bias programming step D for the modulator 14 of the first addressing circuit 6, the select drive unit 28 transmits a select voltage V _S1 to the first electrode 24. At the same time as applying the selection voltage, the addressing drive unit 22 applies the bias voltage V _P to the electrode 20.

The select switch 18 at the intersection of the first electrode 24 and the addressing electrode 20 is disconnected and at this time sends a bias voltage V _P to the modulator 14 and to the storage capacitor 16. The storage capacitor is discharged and stores the charge transmitted by the bias voltage during the bias steps E, F for the first addressing circuit 6, as shown in FIG. 2 (d). The drain current I _d1 of the previous frame stops flowing through the modulator 14. The trigger threshold voltage of the modulator 14 changed and increased during the image frame will decrease during the new frame, especially during step F.

The next image frame begins with an addressing programming step E for modulator 34 of the second addressing circuit 12. During this step, the selection drive unit 28 applies the selection voltage V _S2 to the electrode 26. At the same time, the addressing drive unit 22 applies the addressing voltage V _Db to the electrode 20.

The switch 38 of the second addressing circuit 12 is disconnected and an addressing voltage V _Db representing the image data is applied at the gate of the modulator 34 and at the terminal of the storage capacitor 36. Drain current I _d2 is generated between the drain and source of modulator 34. This current has a magnitude proportional to the value of the image data to be transmitted during this image frame. This current flows through the light emitter 4 during step F to the end of the image frame.

It is thus recognized that during steps E and F, the current is supplied to the optical emitter 4 by the second addressing circuit 12. Thus steps E and F together form a step for operating the second addressing circuit 12.

As a result, the control system 11 and the drive units 22 and 28 control the addressing of the selection voltage, the addressing voltage and the bias voltage to be as follows.

An anode addressing voltage is applied at the gate of the modulator 14 of the first addressing circuit 6 to drive the optical emitter 4, followed by a bias voltage of the cathode to compensate for the change in the trigger threshold voltage. To the gate of the modulator 34 of the second addressing circuit 12;

In the opposite manner, then the addressing voltage of the anode is applied at the gate of the modulator 34 of the second addressing circuit 12 to drive the light emitter 4, followed by the bias voltage of the cathode. Is applied at the gate of the modulator 14 of the first addressing circuit 6 to compensate for the change of?

For each image frame, the emitters are sequentially turned off by the first modulator 14 during the step for operating the first addressing circuit and then by the second modulator 34 during the step for operating the second addressing circuit. Current is supplied to 4).

In each image frame, the trigger threshold voltage of the modulator 14 of the first addressing circuit and of the modulator 34 of the second addressing circuit is sequentially increased and then decreased. Such a device thus advantageously provides for compensating for a trigger threshold voltage change of the modulator of the panel.

3 shows a light emitter 4 and means 40 for controlling the emission of the emitter according to the second embodiment of the invention.

In this embodiment, the control means 40 comprises first addressing circuit 6 and second addressing circuit 12, each of which is connected to an array of light emitters 4, addressing control means for a row of light emitters. 42, selection control means 44 and control system 56 for a row of light emitters.

The first addressing circuit 6 and the second addressing circuit 12 comprise the same components, connected in the same manner as the addressing circuit described with reference to FIG. 1. This component is identified with the same reference numeral as in FIG. 1 and will not be described later.

The addressing control means 42 comprises an addressing drive unit 46, a first addressing electrode 48 and a second addressing electrode 50 for each light emitter row. The first addressing electrode 48 is connected to the drive unit 46 and to the drain of the switches 18 of all the first addressing circuits 6 in the light emitter column. The second addressing electrode 50 is connected to the drive unit 46 and to the drain of the switch 38 of all the second addressing circuits 12 in the light emitter column.

Addressing the drive unit 46 is intended to send an addressing voltage (V _D2) on the first electrode 48, an addressing voltage (V _D1) and the second electrode 50 in the same time on the way.

The selection control means 44 comprises a selection drive unit 54 and a single selection electrode 52 for each row of light emitters. The select electrode 52 is connected to the drive unit 54, to the gate of the switch 18 of the first addressing circuit 6, and to the gate of the switch 38 of the second addressing circuit of the row of light emitters. .

The control system 56 is connected to the drive unit 54 and to the drive unit 46. This control system 56 is intended to transmit digital image data and data related to the bias voltage to the drive unit 46. It is also intended to send a periodic selection signal to the drive unit 54.

An addressing method for a display screen according to a second embodiment of the present invention is illustrated in Figs. 4 (a) to 4 (f).

The method includes a step G for programming the addressing of the capacitor 16 and for programming the bias of the modulator 34 simultaneously. The drive unit 46 transmits an addressing voltage V _Da representing the image data to the first electrode 48 and a bias voltage V _P to the second electrode 50.

At the same time, the drive unit 54 and transmits the selected voltage (V _S) on the selection electrode (52). The switch 18 of the first addressing circuit and the switch 38 of the second programming circuit are disconnected so that a bias voltage V _P is applied at the gate of the modulator 34 and at the terminal of the capacitor 36, and the address The specified voltage V _Da is applied at the gate of the modulator 14 and at the terminal of the storage capacitor 16.

After the storage capacitor 36 discharges, it is charged to a negative potential equal to the bias voltage V _P. This voltage held by the storage capacitor 36 at the gate of the modulator 34 attempts to gradually reduce the trigger threshold voltage of the modulator 34, especially during step H. As shown by the dashed line graph in FIG. 4E, the drain current I _d2 becomes zero and remains zero during step H.

Capacitor 16 charges to potential V _Da and drain current I _d1 is established between the drain and source of modulator 14. Light emitter 4 is driven by current I _d1 during step H to the end of the image frame.

Thus, during steps G and H, current is supplied to the light emitter 4 by the first addressing circuit 6; Thus, steps G and H together form a step for operating the first addressing circuit. Moreover, during steps G and H, a bias voltage is applied at the gate of the modulator 34 to compensate for the change in trigger threshold voltage. Thus, steps G and H together form a step for biasing the second addressing circuit.

During step I for programming the addressing of the storage capacitor 36 and for simultaneously programming the bias of the modulator 14, the drive unit 46 applies a bias voltage V _P to the first electrode 48. Then, the addressing electrode V _Db representing the image data is transmitted to the second electrode 50.

A switch (18 and 38) are opened at the same time by applying a select voltage (V _S) to the electrode (52). The bias voltage V _P is transmitted to the gate of the modulator 14 and to the terminal of the capacitor 16. The capacitor 16 discharges and then charges negatively. As shown by the solid line graph in Fig. 4E, the drain current I _d1 becomes zero and remains zero during step J.

During steps I and J, a bias voltage V _P is applied at the gate of the modulator 14. Thus steps I and J together form a step for biasing the first addressing circuit 6.

At the same time, an addressing voltage V _Db is applied at the gate of the modulator 34 and at the terminal of the capacitor 36. This voltage held by the capacitor 36 at the gate of the modulator 34 produces a drain current I _d2 which drives the optical emitter 4 during step J and until the next programming step for the next image data. do.

During steps I and J, current is supplied to the light emitter 4 by the second addressing circuit 12; Thus, these steps together form a step for operating the second addressing circuit.

As a result, the control system 56 and the drive units 46 and 54 control the addressing of the selection voltage, the addressing voltage and the bias voltage to be as follows.

An anode addressing voltage is applied at the gate of the modulator 14 of the first addressing circuit 6 to drive the light emitter 4, while at the same time the bias voltage of the cathode compensates for the change in the trigger threshold voltage To the gate of the modulator 34 of the second addressing circuit 12;

In the opposite manner, then the addressing voltage of the anode is applied at the gate of the modulator 34 of the second addressing circuit 12 to drive the light emitter 4, while at the same time the bias voltage of the cathode is the trigger threshold voltage. Is applied at the gate of the modulator 14 of the first addressing circuit 6 to compensate for the change of?

The light emitter 4 is thus in turn supplied with a modulating current by the modulator 14 and then by the modulator 34.

The first addressing circuit 6 and the second addressing circuit 12 are selectively operated to supply current to the light emitter 4.

When modulator 14 drives optical emitter 4, modulator 34 applies a bias voltage corresponding to a high negative voltage to bring the trigger threshold voltage of modulator 34 changed during the previous step back to an initial value. Biased by application at the gate.

Alternatively, when modulator 34 drives light emitter 4, modulator 14 is biased by the same negative bias voltage to cause the trigger threshold voltage previously changed in one direction to change in the opposite direction. . Thus, including two addressing circuits associated with each light emitter contributes to compensating for a trigger threshold change of the modulator of the display screen.

In the embodiment just described, the switching of the operation of one addressing circuit of the screen according to the invention and the operation of the other circuit occurs in each image frame; Without departing from the invention, it is possible to proceed in this manner of modification between a series of image frames and not in each image frame.

In the described embodiment, the bias and actuation steps are performed simultaneously and have the same duration. As a variant, the control means may control the modulators 14 and 34 so that the bias and actuation steps for the first and second circuits are performed simultaneously but with different durations.

According to a preferred embodiment, the bias voltage applied to one or the other modulators of the optical emitter varies from image to frame as a function of the addressing voltage applied to this modulator during the previous frame; Preferably, this bias voltage is the same as the addressing voltage of the previous frame but of opposite sign.

The invention is applicable to video display screens and addressing methods for these screens, in particular for displays of the type based on organic electroluminescent materials having an active matrix etched on amorphous silicon (a-Si). It is possible.

Claims (13)

As an image display screen, A light emitter 4, distributed in a light emitter row and a light emitter column to form a light emitter array, Means (2, 6, 8, 10, 12; 40, 42, 44) for controlling the emission of the light emitter array, a) a first circuit (6, 14, 16, 18), coupled with each array of light emitters to control the current flowing through the light emitters, for addressing the light emitters (4), said circuit ( 6), A first current modulator 14, intended for driving the light emitter 4, comprising a gate electrode and two current-carrying electrodes, A first storage capacitor 16 intended for setting a potential at the gate electrode of the first current modulator 14 Including, the first circuit (6, 14, 16, 18), b) for each optical emitter 4, at least one second circuit 12, 34, 36, 38 for addressing the optical emitter, the first addressing circuit 6 and the second; The addressing circuit 12 is coupled in parallel with the same optical emitter 4 and the second circuit 12 is A second current modulator 34 for the optical emitter 4 comprising a gate electrode and two current-carrying electrodes, A second storage capacitor 36 intended for storing the potential at the gate electrode potential of the second current modulator 34. At least one second circuit 12, 34, 36, 38, including: c) addressing control means 8, 11, 20 intended for applying an addressing voltage V _D ; V _D1 , V _D2 at the first storage capacitor 16 and at the second storage capacitor 36. 22, 42, 46, 48, 50, 56, the addressing voltage representing image data, and the first addressing circuit 6 for supplying current to the light emitter 4 in accordance with the image data. Or addressing control means 8, 11, 20, 22; 42, 46, 48, 50, 56 intended to operate second addressing circuit 12. Emission control means (2, 6, 8, 10, 12; 40, 42, 44) of the light emitter array, including In the image display screen comprising: The addressing control means (8, 11, 20, 22; 42, 46, 48, 50, 56) may have a bias voltage (V _P ) at the first current modulator 14 or at the second current modulator 34. And the bias voltage has a polarity opposite to that of the addressed voltage. According to claim 1, The addressing control means 8, 11, 20, 22; 42, 46, 48, 50, 56 starts the steps B, C, D; G, H for operating the first addressing circuit 6. First applying an addressing voltage (V _D ; D _D1 , V _D2 ) to the first current modulator 14, and then biasing the first addressing circuit 6 (E, F; I, J). And a bias voltage (V _P ) to be initiated. The method of claim 2, The addressing control means 8, 11, 20, 22; 42, 46, 48, 50, 56 are adapted to start the steps E, F; I, J for operating the second addressing circuit 12. Steps B, C, D; G, H for first applying an addressing voltage V _D ; D _D1 , V _D2 to the second current modulator 34 and then biasing the second addressing circuit 12. Is intended to apply a bias voltage (V _P ) to start (), the step for operating the first addressing circuit 6 is synchronized with the step for biasing the second addressing circuit 12, And wherein the step for operating the second addressing circuit (12) is synchronized with the step for biasing the first addressing circuit (1). The method according to any one of claims 1 to 3, The control means, For each first addressing circuit 6 for an optical emitter, of the addressing voltage V _D ; V _D1 , V _D2 and of the bias voltage to select the optical emitter 4, First select switch 18 intended to drive a transmission of the first current modulator 14 to the gate and the first storage capacitor 16 as a function of selection voltages V _S1 , V _S2 ; V _S. ); For each second addressing circuit 12 for the same optical emitter, of the addressing voltage V _D ; V _D1 , V _D2 and of the bias voltage to select the optical emitter 4. A second selection switch intended to drive a transmission of the second current modulator 34 to the gate and the second storage capacitor 36 as a function of the selection voltages V _S1 , V _S2 ; V _S. (38); And Means 11, 24, 26, 28; 52, 54, 56 for driving the first selector switch 18 and the second selector switch 38; Selection control means (10, 11, 24, 26, 28; 44, 52, 54, 56) And a video display screen. The method of claim 4, wherein The drive means 11, 24, 26, 28; 52, 54, 56, For each row of light emitters, a first selector electrode 24 and a second selector electrode 26 connected to and controlling the first switch 18 and the second switch 38 respectively; And A selection drive unit 28 intended to alternately transmit the selection voltage V _S1 to the first selection electrode 24 and then the selection voltage V _S2 to the second selection electrode 26. ) The video display screen, characterized in that it further comprises. The method of claim 5, The addressing control means 8, 20, 22; 42, 46, 48, 50, An addressing electrode 20 for each row of light emitters, the addressing electrode 20 to which the first selector switch 18 and the second selector switch 38 are connected; And An addressing drive unit 22 intended to alternately send the addressing voltage V _D and the bias voltage V _P to the addressing electrode 20. Image display screen comprising a. The method of claim 4, wherein The drive means (11, 24, 26, 28; 52, 54, 56), A selection electrode 52 for each row of light emitters, the selection wire 52 connected to which the first selection switch 18 and the second selection switch 38 are to be controlled; And A selection drive unit 54 intended to send the selection voltage V _S to the first selection switch 18 and the second selection switch 38 simultaneously. The video display screen further comprises. The method of claim 7, wherein The addressing control means 8, 20, 22; 42, 46, 48, 50, A first addressing electrode 48 and a second addressing electrode 50, each connected to a first selection switch 18 and a second selection switch 38, for each light emitter row; And An addressing drive unit 46 intended to send the addressing voltage V _D1 or the bias voltage V _P simultaneously on the first addressing electrode 48 and on the second addressing electrode 50. Including, a video display screen. Addressing method for an image display screen comprising an optical emitter 4, a first addressing circuit 6 and a second addressing circuit 12, wherein the first addressing circuit 6 is an optical emitter A first current modulator 14 connected to (4), and a first storage capacitor 16 intended to store a potential at a gate of the first current modulator 14, wherein the second addressing circuit 12 A second current modulator (34) connected to the light emitter (4), and a second storage capacitor intended to store a potential at the gate of the second current modulator (34); Each modulator 14, 34 comprises in particular a gate electrode and a source electrode; Wherein each modulator allows current to pass through the modulator when a voltage greater than the trigger threshold voltage is applied between the gate electrode and the source electrode. For driving each light emitter 4, Steps B, C, D; G, H for operating the first addressing circuit 6 to supply current to the light emitter 4; -Biasing the second addressing circuit 12 to change the trigger threshold voltage of the second modulator 34 (B, C, D; G, H); Steps E, F; I, J for operating the second addressing circuit 12 to supply current to the light emitter 4; And -Step (E, F; I, J) for biasing the first addressing circuit 6 to change the trigger threshold voltage of the first modulator 14 Wherein the step for operating the first addressing circuit 6 occurs concurrently with the step for biasing the second addressing circuit 12 and the step for driving the second addressing circuit 12 Characterized in that it occurs simultaneously with the step for biasing the first addressing circuit (6). The method of claim 9, One or more steps for operating the first addressing circuit 6 are followed by at least one step for biasing the first addressing circuit 6, and one or more steps for operating the second addressing circuit 12. And at least one step for biasing the second addressing circuitry (12) is followed by the step. The method of claim 9 or 10, An addressing programming step (B; G) for said first storage capacitor by applying an addressing voltage (V _D ; V _D1 , V _D2 ) representing image data to said capacitor; A bias programming step (D; I) for the first current modulator 14 by applying a bias voltage V _P to the modulator, the bias voltage being the polarity of the potential stored by the first storage capacitor 16. A bias programming step (D; I) having a polarity opposite to; A bias programming step (A; G) for said second current modulator (34) by applying said bias voltage (V _P ) to said modulator; And An addressing programming step (E; I) for the second storage capacitor 36 by applying the addressing voltage V _D ; V _D1 , V _D2 to the capacitor Addressing method for a video display screen, characterized in that it comprises a. The method of claim 11, wherein A bias programming step (D) for the first current modulator 14 is followed by an addressing programming step (E) for a second storage capacitor 36, which in turn is a bias for the second current modulator 34. A programming method (A) is followed by an addressing programming step (B) for the first storage capacitor (16). The method of claim 11, wherein The bias programming step G for the second current modulator 34 occurs concurrently with the addressable programming step G for the first storage capacitor 16 and is coupled to the first current modulator 14. Wherein said bias programming step (I) occurs concurrently with said addressing programming step (I) for said second storage capacitor (36).

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