JP2007519949A - Image display screen, addressing method - Google Patents

Image display screen, addressing method Download PDF

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JP2007519949A
JP2007519949A JP2006546220A JP2006546220A JP2007519949A JP 2007519949 A JP2007519949 A JP 2007519949A JP 2006546220 A JP2006546220 A JP 2006546220A JP 2006546220 A JP2006546220 A JP 2006546220A JP 2007519949 A JP2007519949 A JP 2007519949A
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addressing
voltage
circuit
light emitter
current regulator
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JP5074769B2 (en
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ロワ，フィリップ ル
プラ，クリストフ
アマルディ，ファビアン
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Thomson Licensing SAS
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Abstract

本発明は表示画面に関し、前記表示画面は、発光体の配列を形成するよう発光体の行及び発光体の列に配された発光体、配列の各発光体に関連付けられ前記発光体に電力を供給する第１の電流調整器及び前記第１の電流調整器のゲート電極に電位を蓄積する第１の蓄電コンデンサーを有する第１のアドレス指定回路、を有する。画面は、発光体の少なくとも１つの第２のアドレス指定回路を有する。第１及び第２のアドレス指定回路は、同一の発光体と関連付けられる。第２の回路は、発光体の第２の電流調整器及び第２の電流調整器のゲート電極に電位を蓄える第２の蓄電コンデンサーを有する。本発明は、前記画面のアドレス指定方法に関する。  The present invention relates to a display screen, wherein the display screen is associated with each light emitter in the array of light emitters and rows of light emitters to form an array of light emitters and power to the light emitters. A first addressing circuit having a first current regulator to be supplied and a first storage capacitor for storing a potential in a gate electrode of the first current regulator; The screen has at least one second addressing circuit for the light emitter. The first and second addressing circuits are associated with the same light emitter. The second circuit includes a second storage capacitor that stores a potential in the second current regulator of the light emitter and the gate electrode of the second current regulator. The present invention relates to an addressing method for the screen.

Description

本発明は、画像表示画面及び前記画面のアドレス指定方法に関する。   The present invention relates to an image display screen and an addressing method for the screen.

特に、本発明は、アモルファスシリコン（ａ−Ｓｉ）にエッチングされたアクティブマトリックスを有する有機電場発光物質に基づく種類の表示画面に関する。   In particular, the invention relates to a display screen of the type based on an organic electroluminescent material having an active matrix etched in amorphous silicon (a-Si).

水素化アモルファスシリコン薄膜トランジスターは、多結晶シリコン（ｐ−Ｓｉ）薄膜トランジスターより、製造が容易で且つ有意に大きい画面で均一の輝度を示すので、有機電場発光物質に基づく画面の設計に有利である。   Hydrogenated amorphous silicon thin film transistors are easier to manufacture than polycrystalline silicon (p-Si) thin film transistors and exhibit uniform brightness on a significantly larger screen, which is advantageous for screen designs based on organic electroluminescent materials. .

しかしながら、アモルファスシリコントランジスターのトリガー閾値電圧は、時間の経過に伴いゲートとソース間に長期に電圧を印加する間に変化する。   However, the trigger threshold voltage of an amorphous silicon transistor changes with the passage of time while applying a voltage for a long time between the gate and the source.

このトリガー閾値電圧の変化は、画面の画像生成処理に影響し、画面の輝度を時間の経過に伴い変化させる。   The change in the trigger threshold voltage affects the screen image generation process, and changes the screen brightness with the passage of time.

特に、特許文献１は、アドレス制御手段を有する以上に説明された種類の画面を記載している。前記アドレス制御手段は、各画像フレームの間、この画面の各発光体の電流調整器に、及びこの発光体のアドレス指定回路と全く同一の使用している回路に、画像データを表すアドレス電圧及びアドレス電圧と反対の極性を有する電圧を交互に印加する。   In particular, Patent Document 1 describes a screen of the type described above having an address control means. The address control means includes an address voltage representing image data and a current regulator for each light emitter on this screen during each image frame, and a circuit that is used exactly the same as the addressing circuit for this light emitter. A voltage having a polarity opposite to that of the address voltage is applied alternately.

しかしながら、このアーキテクチャ及びこの駆動モードは、各フレームの間に発光持続時間を減少させるので、画面の輝度を低下させ、画面にちらつき効果を生じさせる。   However, this architecture and this drive mode reduce the light emission duration during each frame, thus reducing the screen brightness and creating a flicker effect on the screen.

特に、特許文献２（特に図９を参照）及び３は、アドレス制御手段を有する以上に説明された種類の画面を記載している。前記アドレス制御手段は、各画像フレームの間、この画面の各発光体の電流調整器に、及び複数のこの発光体のアドレス指定回路の少なくとも１つを用い、常に同じ極性を有する画像データを表すアドレス電圧を印加する。
米国特許第２００３／０５２６１４号明細書 米国特許第６０１１５２９号明細書 国際公開第２００４／０５１６１７号パンフレット In particular, Patent Documents 2 (see particularly FIG. 9) and 3 describe screens of the type described above having address control means. The address control means always represents image data having the same polarity during each image frame by using at least one of the current regulators of the light emitters of the screen and a plurality of addressing circuits of the light emitters. Apply address voltage.
US 2003/052614 US Pat. No. 6,011,529 International Publication No. 2004/051617 Pamphlet

本発明の目的は、時間の経過に伴う輝度の変化が少ない画面を提案することである。   An object of the present invention is to propose a screen in which a change in luminance with time is small.

この目的のため、本発明は画像表示画面を提供する。   For this purpose, the present invention provides an image display screen.

画像表示画面は、発光体の配列を形成するよう発光体の行及び発光体の列に配された発光体、配列の発光体の発光を制御する手段、を有する。   The image display screen includes light emitters arranged in rows and columns of light emitters so as to form an array of light emitters, and means for controlling light emission of the light emitters in the array.

手段は、
（ａ）前記発光体に電力を供給しゲート電極と２つの電流通過電極を有する第１の電流調整器、第１の電流調整器のゲート電極に電位を設定する第１の蓄電コンデンサーを有し、発光体を流れる電流を制御するよう配列の各発光体と関連付けられ、発光体をアドレス指定する第１の回路、
（ｂ）ゲート電極と２つの電流通過電極を有する前記発光体の第２の電流調整器、第２の電流調整器のゲート電極に電位を蓄積する第２の蓄電コンデンサーを有し、発光体毎に、発光体をアドレス指定する少なくとも１つの第２の回路、
（ｃ）前記第１の蓄電コンデンサー及び前記第２の蓄電コンデンサーに、画像データを表し及び前記画像データに従い発光体に電流を供給するため第１又は第２のアドレス指定回路の何れかをアクティブにするアドレス指定電圧を印加する、アドレス指定制御手段、を有する。 Means
(A) a first current regulator that supplies power to the light emitter and includes a gate electrode and two current passing electrodes; a first storage capacitor that sets a potential at the gate electrode of the first current regulator; A first circuit associated with each light emitter in the array to control the current flowing through the light emitter and addressing the light emitter;
(B) a second current regulator of the light emitter having a gate electrode and two current passing electrodes, a second storage capacitor for storing a potential in the gate electrode of the second current regulator, and each light emitter At least one second circuit for addressing the illuminant,
(C) activating either the first or second addressing circuit to represent the image data to the first storage capacitor and the second storage capacitor and to supply current to the light emitter in accordance with the image data Addressing control means for applying an addressing voltage to be applied.

前記第１及び第２のアドレス指定回路は、同一の発光体と並列に配置される。   The first and second addressing circuits are arranged in parallel with the same light emitter.

画面は、アドレス指定制御手段は、前記アドレス指定電圧の極性と反対の極性を有するバイアス電圧を、前記第１の電流調整器又は前記第２の電流調整器の何れかに設定することを特徴とする。   In the screen, the addressing control means sets a bias voltage having a polarity opposite to the polarity of the addressing voltage in either the first current regulator or the second current regulator. To do.

特定の実施例によると、表示画面は以下の特徴の１つ以上を有する。   According to particular embodiments, the display screen has one or more of the following features.

アドレス指定制御手段は、前記第１の電流調整器に最初にアドレス指定電圧を印加し、第１のアドレス指定回路を起動する段階を開始し、次にバイアス電圧を印加し、第１のアドレス指定回路をバイアスする段階を開始する。   The addressing control means first applies an addressing voltage to the first current regulator to start a first addressing circuit, and then applies a bias voltage to apply the first addressing Begin the stage of biasing the circuit.

アドレス指定手段は、前記第２の電流調整器に最初にアドレス指定電圧を印加し、第２のアドレス指定回路を起動する段階を開始し、次にバイアス電圧を印加し、第２のアドレス指定回路をバイアスする段階を開始する。第１のアドレス指定回路を起動する段階は、第２のアドレス指定回路をバイアスする段階と同期し、第２のアドレス指定回路を起動する段階は、第１のアドレス指定回路をバイアスする段階と同期する。   The addressing means first applies an addressing voltage to the second current regulator to start a second addressing circuit, and then applies a bias voltage to the second addressing circuit. Begin the phase of biasing. The step of activating the first addressing circuit is synchronized with the step of biasing the second addressing circuit, and the step of activating the second addressing circuit is synchronized with the step of biasing the first addressing circuit. To do.

制御手段は、発光体の第１のアドレス指定回路毎に、前記アドレス指定電圧又は前記バイアス電圧の前記第１の蓄電コンデンサー及び前記第１の電流調整器の前記ゲートへの送信を、前記発光体を選択するために、選択電圧に応じて駆動する、第１の選択スイッチ、同一の発光体の第２のアドレス指定回路毎に、前記アドレス指定電圧又は前記バイアス電圧の前記第２の蓄電コンデンサー及び前記第２の電流調整器の前記ゲートへの送信を、前記発光体を選択するために、前記選択電圧に応じて駆動する、第２の選択スイッチ、及び前記第１及び第２の選択スイッチを駆動する手段、を有する選択制御手段を有する。   For each first addressing circuit of the light emitter, the control means transmits the addressing voltage or the bias voltage to the gate of the first storage capacitor and the first current regulator. A first selection switch that is driven according to a selection voltage, a second storage capacitor of the addressing voltage or the bias voltage for each second addressing circuit of the same light emitter, and A second selection switch for driving transmission of the second current regulator to the gate according to the selection voltage to select the light emitter; and a first selection switch and a second selection switch. Selection control means having means for driving.

駆動手段は、発光体の各行に、制御するためそれぞれ第１及び第２の選択スイッチに接続された第１及び第２の選択電極、及び最初に前記選択電圧を前記第１の選択電極へ、次に前記選択電圧を前記第２の選択電極へ交互に送信する選択駆動装置、を更に有する。   The driving means includes, for each row of light emitters, first and second selection electrodes connected to first and second selection switches, respectively, for control, and initially the selection voltage to the first selection electrode, Next, the apparatus further includes a selection driving device that alternately transmits the selection voltage to the second selection electrode.

アドレス指定制御手段は、発光体の各列にアドレス指定電極を有し、第１及び第２の選択スイッチは、前記アドレス指定電極と接続され、及びアドレス指定駆動装置は、前記アドレス指定電圧及び前記バイアス電圧を前記アドレス指定電極へ交互に送る。   The addressing control means includes an addressing electrode in each column of the light emitters, the first and second selection switches are connected to the addressing electrode, and the addressing driving device includes the addressing voltage and the Bias voltage is sent alternately to the addressing electrodes.

駆動手段は、発光体の各行に、選択電極を更に有し、第１及び第２の選択スイッチは、制御するため前記選択電極と接続され、及び選択駆動装置は、前記選択電圧を第１及び第２の選択スイッチへ同時に送る。   The driving means further includes a selection electrode in each row of the light emitters, the first and second selection switches are connected to the selection electrode for control, and the selection driving device applies the selection voltage to the first and the second voltages. Send simultaneously to the second selection switch.

アドレス指定制御手段は、発光体の各列に、それぞれ第１及び第２の選択スイッチと接続される第１及び第２のアドレス指定電極、及び前記アドレス指定電圧又は前記バイアス電圧の何れかを第１の前記アドレス指定電極と前記第２のアドレス指定電極へ同時に送るアドレス指定駆動装置、を有する。   The addressing control means assigns, to each column of light emitters, the first and second addressing electrodes connected to the first and second selection switches, respectively, and either the addressing voltage or the bias voltage. A first addressing electrode and a second addressing electrode for simultaneously sending to the second addressing electrode.

本発明は、更に、前記種類の表示画面のアドレス指定方法を提供する。アドレス指定方法は、各発光体を駆動するために、電流を発光体に供給するため第１のアドレス指定回路を起動する段階、第２の調整器のトリガー閾値電圧を変化するため第２のアドレス指定回路をバイアスする段階、電流を発光体に供給するため、第２のアドレス指定回路を起動する段階、第１の調整器のトリガー閾値電圧を変化するため第１のアドレス指定回路をバイアスする段階、を有し、第１のアドレス指定回路を起動する段階は、第２のアドレス指定回路をバイアスする段階と同期し、及び第２のアドレス指定回路を起動する段階は、第１のアドレス指定回路をバイアスする段階と同期することを特徴とする。   The present invention further provides a method for addressing the type of display screen. The addressing method includes activating a first addressing circuit to supply current to the light emitters to drive each light emitter, and a second address to change the trigger threshold voltage of the second regulator. Biasing the designating circuit; activating a second addressing circuit to supply current to the light emitter; and biasing the first addressing circuit to change a trigger threshold voltage of the first regulator. And the step of activating the first addressing circuit is synchronized with the step of biasing the second addressing circuit, and the step of activating the second addressing circuit is the first addressing circuit. It is characterized by synchronizing with the step of biasing.

特定の実施例によると、表示方法は以下の特徴の１つ以上を有する。   According to a particular embodiment, the display method has one or more of the following features.

第１のアドレス指定回路を起動する１つ以上の段階の次に、第１のアドレス指定回路をバイアスする少なくとも１つの段階が続き、及び第２のアドレス指定回路を起動する１つ以上の段階の次に、第２のアドレス指定回路をバイアスする少なくとも１つ以上の段階が続く。   The one or more stages for activating the first addressing circuit are followed by at least one stage for biasing the first addressing circuit, and one or more stages for activating the second addressing circuit. Next follows at least one or more stages of biasing the second addressing circuit.

前記方法は、画像データを表すアドレス指定電圧を前記第１の蓄電コンデンサーに印加することによる、前記第１の蓄電コンデンサーのアドレス指定設定段階、第１の蓄電コンデンサーにより蓄えられた電位の極性と反対の極性を有する前記バイアス電圧を前記第１の電流調整器に印加することによる、前記第１の調整器のバイアス設定段階、前記バイアス電圧を前記第２の電流調整器に印加することによる、前記第２の調整器のバイアス設定段階、及び前記アドレス指定電圧を前記第２の蓄電コンデンサーに印加することによる、前記第２の蓄電コンデンサーのアドレス指定設定段階、を有する。   In the method, an addressing setting step of the first storage capacitor by applying an addressing voltage representing image data to the first storage capacitor, opposite to a polarity of a potential stored by the first storage capacitor. A bias setting step of the first regulator by applying the bias voltage having the following polarity to the first current regulator, and by applying the bias voltage to the second current regulator, A second regulator bias setting step, and an addressing setting step of the second storage capacitor by applying the addressing voltage to the second storage capacitor.

前記第１の電流調整器のバイアス設定段階の次に、第２の蓄電コンデンサーのアドレス指定設定段階が続き、及び交代に前記第２の電流調整器のバイアス設定段階の次に、第１の蓄電コンデンサーのアドレス指定設定段階が続く。   The bias setting stage of the first current regulator is followed by an addressing and setting stage of a second storage capacitor, and, alternately, the first storage capacitor is followed by the bias setting stage of the second current regulator. The capacitor addressing setup phase follows.

前記第２の電流調整器の前記バイアス設定段階は、前記第１の蓄電コンデンサーの前記アドレス指定設定段階と同時であり、及び前記第１の電流調整器の前記バイアス設定段階は、前記第２の蓄電コンデンサーの前記アドレス指定設定段階と同時である。   The bias setting stage of the second current regulator is simultaneous with the addressing setting stage of the first storage capacitor, and the bias setting stage of the first current regulator is the second current regulator. At the same time as the addressing setting stage of the storage capacitor.

本発明は、例としてのみ与えられる以下の説明及び図を参照しより理解される。   The invention will be better understood with reference to the following description and figures, given by way of example only.

本発明による表示画面は、発光体の配列を形成するよう行及び列に配置された発光体を有するアクティブマトリックスである。   The display screen according to the present invention is an active matrix having light emitters arranged in rows and columns to form an array of light emitters.

表示画面の発光体は、ＯＬＥＤという略語で知られる有機発光ダイオードである。それらのそれぞれは、画面が白黒の場合１つの画素と関連付けられ、又は画面が多色の場合サブピクセルと関連付けられる。それらは、それらに流れる電流に直接比例する光度を発光する。   The light emitter of the display screen is an organic light emitting diode known by the abbreviation OLED. Each of them is associated with one pixel when the screen is black and white, or with a sub-pixel when the screen is multicolor. They emit light intensity that is directly proportional to the current flowing through them.

図１は、本発明の第１の実施例による配列の発光体４の発光を制御する手段２を示す。簡単のため、単一の発光体のアドレス指定の制御手段のみ、この図に示されている。   FIG. 1 shows a means 2 for controlling the light emission of an array of light emitters 4 according to a first embodiment of the invention. For simplicity, only a single light emitter addressing control means is shown in this figure.

制御手段２は、配列の発光体４と接続された第１のアドレス指定回路６、発光体の列のアドレス指定を制御するアドレス指定制御手段８、発光体の行の選択を制御する選択制御手段１０、制御システム１１、及び発光体４と接続された第２のアドレス指定回路１２を有する。   The control means 2 includes a first addressing circuit 6 connected to the light emitters 4 in the array, an address designation control means 8 for controlling address designation of the columns of the light emitters, and a selection control means for controlling selection of the rows of the light emitters. 10, a control system 11, and a second addressing circuit 12 connected to the light emitter 4.

第１のアドレス指定回路６は、電流調整器１４、蓄電コンデンサー１６、及び選択スイッチ１８を有する。   The first addressing circuit 6 includes a current regulator 14, a storage capacitor 16, and a selection switch 18.

調整器１４及びスイッチ１８は、水素化アモルファスシリコン薄膜トランジスターである。より詳細には、これらはｎ型トランジスターである。それらはドレイン、ゲート、及びソースを有し、それらのトリガー閾値電圧より大きい又は等しい電圧がそれらのゲートとそれらのソースの間に印加された場合、それらのドレインからそれらのソースへそれらを流れる電流を有する。   The regulator 14 and the switch 18 are hydrogenated amorphous silicon thin film transistors. More particularly, these are n-type transistors. They have drains, gates, and sources, and the current that flows them from their drains to their sources when a voltage greater than or equal to their trigger threshold voltage is applied between their gates and their sources Have

代案として、ｐ型トランジスターが利用されて良い。その場合、トランジスター１４及び１８は、それらのソースからそれらのドレインへそれらを流れる電流を有する。   As an alternative, a p-type transistor may be used. In that case, transistors 14 and 18 have a current flowing through them from their sources to their drains.

調整器１４のドレインは、発光体４の陰極と接続される。発光体４の陽極は、発光体に電力を供給する直流電圧源Ｖｄｄと接続される。調整器１４のソースは、接地電極又は負の電圧と接続される。調整器１４のゲートは、スイッチ１８のソース及び蓄電コンデンサー１６の端子と接続される。蓄電コンデンサー１６の他の端子は、接地電極と接続される。スイッチ１８のゲートは選択制御手段１０と接続され、及びスイッチ１８のドレインはアドレス指定制御手段８と接続される。   The drain of the regulator 14 is connected to the cathode of the light emitter 4. The anode of the light emitter 4 is connected to a DC voltage source Vdd that supplies power to the light emitter. The source of the regulator 14 is connected to the ground electrode or a negative voltage. The gate of the regulator 14 is connected to the source of the switch 18 and the terminal of the storage capacitor 16. The other terminal of the storage capacitor 16 is connected to the ground electrode. The gate of the switch 18 is connected to the selection control means 10, and the drain of the switch 18 is connected to the addressing control means 8.

発光体の列のアドレス指定制御手段８は、発光体の各列のアドレス指定電極２０、及びアドレス指定駆動装置２２を有する。電極２０は、駆動装置２２及び発光体の列の第１のアドレス指定回路６のスイッチ１８のドレインと接続される。   The illuminant column addressing control means 8 has an addressing electrode 20 and an addressing driving device 22 for each column of illuminants. The electrode 20 is connected to the drive 22 and the drain of the switch 18 of the first addressing circuit 6 in the row of light emitters.

選択制御手段１０は、発光体の各行に第１の選択電極２４及び第２の選択電極２６を、及び選択駆動装置２８を有する。第１の選択電極２４は、駆動装置２８及び発光体の行の第１のアドレス指定回路６のスイッチ１８のゲートと接続される。第２の選択電極２６は、駆動装置２８及び発光体の行の第２のアドレス指定回路１２のスイッチ３８のゲートと接続される。   The selection control means 10 includes a first selection electrode 24 and a second selection electrode 26 in each row of light emitters, and a selection drive device 28. The first selection electrode 24 is connected to the drive device 28 and the gate of the switch 18 of the first addressing circuit 6 in the row of light emitters. The second select electrode 26 is connected to the drive 28 and the gate of the switch 38 of the second addressing circuit 12 in the row of light emitters.

制御システム１１は、アドレス指定駆動装置２２及び選択駆動装置２８と接続される。   The control system 11 is connected to the addressing drive device 22 and the selection drive device 28.

第２のアドレス指定回路１２は、第１のアドレス指定回路６と同じ要素を有する。つまり、電流調整器３４、蓄電コンデンサー３６、及び選択スイッチ３８である。これらの要素は、第１のアドレス指定回路６と同様に相互接続されるので、詳細は省略する。   The second addressing circuit 12 has the same elements as the first addressing circuit 6. That is, the current regulator 34, the storage capacitor 36, and the selection switch 38. Since these elements are interconnected in the same manner as the first addressing circuit 6, details are omitted.

特に、第２のアドレス指定回路１２の調整器３４は、端子３２で発光体４の陰極と接続される。スイッチ３８のドレインは、スイッチ１８と同様のアドレス指定電極２０と接続され、及びスイッチ１８のゲートは第２の選択電極２６と接続される。   In particular, the regulator 34 of the second addressing circuit 12 is connected to the cathode of the light emitter 4 at the terminal 32. The drain of the switch 38 is connected to the addressing electrode 20 similar to the switch 18, and the gate of the switch 18 is connected to the second selection electrode 26.

制御システム１１は、デジタル画像データ及びバイアス電圧に関するデータを駆動装置２２へ及び周期的選択信号を駆動装置２８へ所定の周波数で送信する。   The control system 11 transmits digital image data and data relating to the bias voltage to the driving device 22 and a periodic selection signal to the driving device 28 at a predetermined frequency.

アドレス指定駆動装置２２は、画像データを表すアドレス指定電圧ＶＤを列の全ての発光体へ電極２０を経由して送信する。アドレス指定駆動装置２２はまた、電極２０に、アドレス指定電圧の極性に対し反対の極性を有するバイアス電圧Ｖｐと称される電圧を印加する。この電圧は、所定の持続期間を有する所定の負の電圧である。望ましくは、バイアス電圧Ｖｐは、−２ボルトと−２５ボルトの間である。一般に、逆電圧又は負のバイアス電圧は、調整器のゲート及びソース電極の間の電位差Ｖｇｓと称され、０ボルトより小さく、Ｖｇｓ＜０ボルトである。 Addressing driving device 22 transmits the address voltage V D representing the image data via the electrode 20 to all light emitters of the column. The addressing driver 22 also applies to the electrode 20 a voltage called a bias voltage Vp having a polarity opposite to the polarity of the addressing voltage. This voltage is a predetermined negative voltage having a predetermined duration. Desirably, the bias voltage Vp is between -2 volts and -25 volts. In general, the reverse or negative bias voltage is referred to as the potential difference Vgs between the gate and source electrodes of the regulator and is less than 0 volts and Vgs <0 volts.

駆動装置２８は、周期的選択電圧ＶＳ１、ＶＳ２を発光体の行の第１のアドレス指定回路６のスイッチ１８のゲート、又は発光体の同じ行の第２のアドレス指定回路１２のスイッチ３８のゲートに印加し、アドレス指定電圧ＶＤ又はバイアス電圧Ｖｐを、第１のアドレス指定回路６の調整器１４のゲート又は第２のアドレス指定回路１２の調整器３４のゲートに印加する。 The driving device 28 applies the periodic selection voltages V S1 , V S2 to the gate of the switch 18 of the first addressing circuit 6 in the row of light emitters or the switch 38 of the second addressing circuit 12 in the same row of light emitters. The addressing voltage V D or the bias voltage Vp is applied to the gate of the regulator 14 of the first addressing circuit 6 or the gate of the regulator 34 of the second addressing circuit 12.

図２は、本発明による装置により実行されるアドレス指定方法の発生による種々の電圧及び電流の時間的変化を表すグラフである。図２Ａ乃至２Ｆは、本発明の第１の実施例による表示画面のアドレス指定方法を示す。   FIG. 2 is a graph representing the time variation of various voltages and currents due to the occurrence of the addressing method performed by the device according to the invention. 2A to 2F show a display screen addressing method according to the first embodiment of the present invention.

この方法は、第２のアドレス指定回路１２の調整器３４のバイアス設定段階Ａを有する。図２Ｂに示されるように、選択駆動装置２８は、選択電圧ＶＳ２を第２の電極２６へ送信する。選択スイッチ３８は、この選択電圧ＶＳ２をゲートに印加されることにより、導通する。 This method has a bias setting stage A of the regulator 34 of the second addressing circuit 12. As illustrated in FIG. 2B, the selection driving device 28 transmits the selection voltage V S2 to the second electrode 26. The selection switch 38 is turned on by applying the selection voltage V S2 to the gate.

同時に、アドレス指定駆動装置２２は、負の極性（Ｖｇｓ＜０）のバイアス電圧Ｖｐをアドレス指定電極２０に印加する。バイアス電圧Ｖｐは、電流調整器３４のゲート及び蓄電コンデンサー３６の端子に印加される。前のフレームの期間に発光体４に電力を供給するため電流調整器３４を流れていたドレイン電流Ｉｄ２は、図２Ｅに点線により示されるこの新しいフレームの期間に０に向かう。 At the same time, the addressing driving device 22 applies a bias voltage Vp having a negative polarity (Vgs <0) to the addressing electrode 20. The bias voltage Vp is applied to the gate of the current regulator 34 and the terminal of the storage capacitor 36. The drain current I d2, which was flowing through the current regulator 34 to supply power to the light emitter 4 during the previous frame period, goes to 0 during this new frame period indicated by the dotted line in FIG. 2E.

同時に、前のフレームの期間に印加された電圧ＶＤを事前に蓄電していた蓄電コンデンサー３６は、バイアス電圧Ｖｐで図２Ｄに示されるように分極される。図２Ｄに点線の曲線で示されるように、蓄電コンデンサー３６は、第２のアドレス指定回路１２のバイアス段階の間、及び調整器３４の次の設定段階の終了までこのバイアス電圧を調整器３４のゲートに維持する。段階Ｂ、Ｃ及びＤは共に、第２のアドレス指定回路１２のバイアス段階を形成する。 At the same time, the power storage capacitor 36 which has been power storage prior to the voltage V D applied to the period of a frame in advance, are polarized as shown in Figure 2D with the bias voltage Vp. As indicated by the dotted curve in FIG. 2D, the storage capacitor 36 reduces the bias voltage of the regulator 34 during the bias phase of the second addressing circuit 12 and until the end of the next setting phase of the regulator 34. Keep on the gate. Stages B, C and D together form the bias stage of the second addressing circuit 12.

前の画像フレームの期間にアドレス指定電圧の印加を通じて変化していた、調整器３４のトリガー閾値電圧は、バイアス段階の間及び新しいフレームの間を通して、バイアス電圧Ｖｐの印加により、再び変化されるが、前の変化とは逆方向へ変化される。   The trigger threshold voltage of regulator 34, which has changed through the application of the addressing voltage during the previous image frame, is changed again by the application of the bias voltage Vp during the bias phase and through the new frame. , It is changed in the opposite direction to the previous change.

新しいフレームの期間に調整器３４のゲートに印加されたバイアス電圧は、そのトリガー閾値電圧の変化を反対にし、及びトリガー閾値電圧を初期値、つまり前のフレームの期間にゲートにアドレス指定電圧を印加されることにより変化される前の電圧に戻す効果を有する。   The bias voltage applied to the gate of the regulator 34 during the new frame reverses the change in its trigger threshold voltage and applies the trigger threshold voltage to the initial value, ie, the addressing voltage to the gate during the previous frame. This has the effect of returning to the voltage before being changed.

第１のアドレス指定回路６の調整器１４のアドレス指定設定段階Ｂの間、選択駆動装置２８は、選択電圧ＶＳ１を生成し、それを第１の電極２４に印加する。 During the addressing setting stage B of the regulator 14 of the first addressing circuit 6, the selection drive 28 generates a selection voltage V S1 and applies it to the first electrode 24.

同時に、アドレス指定駆動装置２２は、画像データを表すアドレス指定電圧ＶＤａをアドレス指定電極２０に印加する。選択スイッチ１８は、アドレス指定電極２０と第１の選択電極２４の交点にあり、導通されアドレス指定電圧ＶＤａを調整器１４及び第１のアドレス指定回路６の蓄電コンデンサー１６へ送信する。アドレス指定電圧ＶＤａは調整器１４のトリガー閾値電圧より大きいので、ドレイン電流Ｉｄ１は調整器１４のドレインとソースの間に生じ、従って図２Ｆに示されるように発光体４を流れる。コンデンサー１６は、アドレス指定電圧ＶＤａを表す電位を調整器１４のゲートに蓄積し、画像フレームの期間に対応する時間間隔に亘り発光体４の輝度を維持する。このように、段階Ｃの間、画像フレームの終了まで、発光体４は発光する。 At the same time, the addressing driving device 22 applies an addressing voltage V Da representing image data to the addressing electrode 20. The selection switch 18 is at the intersection of the addressing electrode 20 and the first selection electrode 24 and is turned on to transmit the addressing voltage V Da to the regulator 14 and the storage capacitor 16 of the first addressing circuit 6. Since the addressing voltage V Da is greater than the trigger threshold voltage of the regulator 14, a drain current I d1 occurs between the drain and source of the regulator 14 and thus flows through the light emitter 4 as shown in FIG. 2F. The capacitor 16 stores a potential representing the addressing voltage V Da at the gate of the regulator 14 and maintains the luminance of the light emitter 4 over a time interval corresponding to the period of the image frame. Thus, during stage C, the light emitter 4 emits light until the end of the image frame.

段階Ｂ、Ｃ及びＤの間、従って、発光体４は第１のアドレス指定回路６により電流を供給される。段階Ｂ、Ｃ及びＤは従って共に、第１のアドレス指定回路６の起動段階を形成する。   During the stages B, C and D, the light emitter 4 is therefore supplied with current by the first addressing circuit 6. Stages B, C and D thus together form the start-up stage of the first addressing circuit 6.

第１のアドレス指定回路６の調整器１４のバイアス設定段階Ｄの間、選択駆動装置２８は、選択電圧ＶＳ１を生成し、それを第１の電極２４に印加する。選択電圧の印加と同時に、アドレス指定駆動装置２２は、バイアス電圧Ｖｐを電極２０に印加する。 During the bias setting stage D of the regulator 14 of the first addressing circuit 6, the selection driver 28 generates a selection voltage V S1 and applies it to the first electrode 24. Simultaneously with the application of the selection voltage, the addressing driver 22 applies the bias voltage Vp to the electrode 20.

選択スイッチ１８は、第１の電極２４とアドレス指定電極２０の交点にあり、導通され今度はバイアス電圧Ｖｐを調整器１４及び蓄電コンデンサー１６へ送信する。図２Ｄに示されるように、蓄電コンデンサーは放電され、第１のアドレス指定回路６のバイアス段階Ｄ、Ｆの間にバイアス電圧により送信された電荷を格納する。前のフレームのドレイン電流Ｉｄ１は、調整器１４の電流を止める。画像フレームの期間に変化し増加した調整器１４のトリガー閾値電圧は、新しいフレームの期間、特に段階Ｆの間に減少する。 The selection switch 18 is at the intersection of the first electrode 24 and the addressing electrode 20 and is turned on, and this time transmits the bias voltage Vp to the regulator 14 and the storage capacitor 16. As shown in FIG. 2D, the storage capacitor is discharged and stores the charge transmitted by the bias voltage between the bias stages D and F of the first addressing circuit 6. The drain current I d1 of the previous frame stops the regulator 14 current. The trigger threshold voltage of the regulator 14 that has changed and increased during the image frame decreases during the new frame, especially during phase F.

次の画像フレームは、第２のアドレス指定回路１２の調整器３４のアドレス指定設定段階Ｅで開始する。この段階の間、選択駆動装置２８は選択電圧ＶＳ２を電極２６に印加する。同時に、アドレス指定駆動装置２２は、アドレス指定電圧ＶＤｂを電極２０に印加する。 The next image frame starts at the addressing setting stage E of the adjuster 34 of the second addressing circuit 12. During this stage, the selective driving device 28 applies a selective voltage V S2 to the electrode 26. At the same time, the addressing drive device 22 applies an addressing voltage V Db to the electrode 20.

第２のアドレス指定回路１２のスイッチ３８は導通され、画像データを表すアドレス指定電圧ＶＤｂは、調整器３４のゲート及び蓄電コンデンサー３６の端子に印加される。ドレイン電流Ｉｄ２は、調整器３４のドレインとソースの間で生成される。この電流は、この画像フレームの期間に送信されるべき画像データの値に比例する振幅を有する。段階Ｆの間、画像フレームの終了まで、この電流は発光体４を流れる。 The switch 38 of the second addressing circuit 12 is turned on, and the addressing voltage V Db representing the image data is applied to the gate of the regulator 34 and the terminal of the storage capacitor 36. A drain current I d2 is generated between the drain and source of the regulator 34. This current has an amplitude proportional to the value of the image data to be transmitted during this image frame. During phase F, this current flows through the light emitter 4 until the end of the image frame.

段階Ｅ及びＦの間、従って、発光体４は第２のアドレス指定回路１２により電流を供給される。段階Ｅ及びＦは共に従って、第２のアドレス指定回路１２の起動段階を形成する。   During steps E and F, the light emitter 4 is therefore supplied with current by the second addressing circuit 12. Stages E and F together form the start-up stage of the second addressing circuit 12.

続いて、制御システム１１及び駆動装置２２及び２８は、選択のアドレス指定、アドレス指定及びバイアス電圧を制御する。これにより、正の極性のアドレス指定電圧は、第１のアドレス指定回路６の調整器１４のゲートに印加され、発光体４に電力を供給する。続いて負の極性のバイアス電圧は、第２のアドレス指定回路１２の調整器３４のゲートに印加され、トリガー閾値電圧の変化を補償する。次に反対に、正の極性のアドレス指定電圧は、第２のアドレス指定回路１２の調整器３４のゲートに印加され、発光体４に電力を供給する。続いて負の極性のバイアス電圧は、第１のアドレス指定回路６の調整器１４のゲートに印加され、トリガー閾値電圧の変化を補償する。   Subsequently, the control system 11 and the drive units 22 and 28 control the selection addressing, addressing and bias voltage. Thereby, a positive polarity addressing voltage is applied to the gate of the regulator 14 of the first addressing circuit 6 to supply power to the light emitter 4. Subsequently, a negative polarity bias voltage is applied to the gate of the regulator 34 of the second addressing circuit 12 to compensate for changes in the trigger threshold voltage. Then, conversely, a positive polarity addressing voltage is applied to the gate of the regulator 34 of the second addressing circuit 12 to supply power to the light emitter 4. Subsequently, a negative polarity bias voltage is applied to the gate of the regulator 14 of the first addressing circuit 6 to compensate for changes in the trigger threshold voltage.

ある画像フレームから他の画像フレームへ、発光体４は、第１のアドレス指定回路の起動段階の間、第１の調整器１４により、そして次に第２のアドレス指定回路の起動段階の間、第２の調整器３４により、交代で電流を供給される。   From one image frame to another, the light emitter 4 is driven by the first regulator 14 during the activation phase of the first addressing circuit and then during the activation phase of the second addressing circuit. A current is supplied alternately by the second regulator 34.

第１のアドレス指定回路の調整器１４及び第２のアドレス指定回路の調整器３４のトリガー閾値電圧は増加され、そして次に各画像フレームでは反対に減少される。従ってこのような装置は、有利に、パネルの調整器のトリガー閾値電圧の変化を補償する。   The trigger threshold voltages of the first addressing circuit adjuster 14 and the second addressing circuit adjuster 34 are increased and then decreased oppositely in each image frame. Such an arrangement therefore advantageously compensates for changes in the trigger threshold voltage of the panel regulator.

図３は、本発明の第２の実施例による発光体４及びその発光制御手段４０を示す。   FIG. 3 shows a light emitter 4 and its light emission control means 40 according to a second embodiment of the present invention.

この実施例では、制御手段４０は、配列の発光体４とそれぞれ接続された第１のアドレス指定回路６及び第２のアドレス指定回路１２、発光体の列のアドレス指定制御手段４２、発光体の行の選択制御手段４４、及び制御システム５６を有する。   In this embodiment, the control means 40 includes a first addressing circuit 6 and a second addressing circuit 12 respectively connected to the light emitters 4 in the array, an addressing control means 42 for the light emitter columns, and A row selection control means 44 and a control system 56 are provided.

第１及び第２のアドレス指定回路６、１２は、図１を参照して説明されたアドレス指定回路と同様に接続された同じ要素を有する。それらは図１と同一の参照符号により示され、以下では説明されない。   The first and second addressing circuits 6 and 12 have the same elements connected in the same way as the addressing circuit described with reference to FIG. They are denoted by the same reference numerals as in FIG. 1 and will not be described below.

アドレス制御手段４２は、アドレス指定駆動装置４６、第１のアドレス指定電極４８及び第２のアドレス指定電極５０を発光体の各列に有する。第１のアドレス指定電極４８は、駆動装置４６及び発光体の列の全ての第１のアドレス指定回路６のスイッチ１８のドレインと接続される。第２のアドレス指定電極５０は、駆動装置４６及び発光体の列の全ての第２のアドレス指定回路１２のスイッチ３８のドレインと接続される。   The address control means 42 has an addressing drive 46, a first addressing electrode 48, and a second addressing electrode 50 in each column of light emitters. The first addressing electrode 48 is connected to the drains of the switches 18 of all the first addressing circuits 6 in the drive unit 46 and the row of light emitters. The second addressing electrode 50 is connected to the drains of the switches 38 of all the second addressing circuits 12 in the drive unit 46 and the light emitter column.

アドレス指定駆動装置４６は、アドレス指定電圧ＶＤ１を第１の電極４８に送信し、及び同時に、アドレス指定電圧ＶＤ２を第２の電極５０に送信する。 The addressing driver 46 transmits the addressing voltage V D1 to the first electrode 48 and simultaneously transmits the addressing voltage V D2 to the second electrode 50.

選択制御手段４４は、選択駆動装置５４及び発光体の各行に単一の選択電極５２を有する。選択電極５２は、駆動装置５４及び第１のアドレス指定回路６のスイッチ１８のゲート及び発光体の行の第２のアドレス指定回路１２のスイッチ３８のゲートと接続される。   The selection control means 44 has a selection drive device 54 and a single selection electrode 52 in each row of light emitters. The select electrode 52 is connected to the drive 54 and the gate of the switch 18 of the first addressing circuit 6 and the gate of the switch 38 of the second addressing circuit 12 in the row of light emitters.

制御システム５６は、駆動装置５４及び駆動装置４６と接続される。制御システム５６は、デジタル画像データ及びバイアス電圧に関するデータを駆動装置４６へ送信する。制御システム５６はまた、周期的選択信号を駆動装置５４へ送信する。   The control system 56 is connected to the drive device 54 and the drive device 46. The control system 56 transmits digital image data and data relating to the bias voltage to the driving device 46. The control system 56 also sends a periodic selection signal to the drive unit 54.

図４は、本発明の第２の実施例による装置により実行されるアドレス指定方法の発生による種々の電圧及び電流の時間的変化を表すグラフである。図４Ａ乃至４Ｆは、本発明の第２の実施例による表示画面のアドレス指定方法を示す。   FIG. 4 is a graph showing the time variation of various voltages and currents due to the occurrence of the addressing method performed by the apparatus according to the second embodiment of the present invention. 4A to 4F show a display screen addressing method according to a second embodiment of the present invention.

この方法は、コンデンサー１６のアドレス指定を設定し、同時に調整器３４のバイアスを設定する段階Ｇを有する。駆動装置４６は、画像データを表すアドレス指定電圧ＶＤａを第１の電極４８へ送信し、及びバイアス電圧Ｖｐを第２の電極５０へ送信する。 The method includes stage G of setting the addressing of the capacitor 16 and simultaneously setting the bias of the regulator 34. The driving device 46 transmits an addressing voltage V Da representing image data to the first electrode 48 and transmits a bias voltage Vp to the second electrode 50.

同時に、アドレス指定駆動装置５４は、選択電圧Ｖｓを選択電極５２に送信する。第１のアドレス指定回路のスイッチ１８及び第２の設定回路のスイッチ３８は、導通され、バイアス電圧Ｖｐは調整器３４のゲート及びコンデンサー３６の端子に印加され、及びアドレス指定電圧ＶＤａは、調整器１４のゲート及び蓄電コンデンサー１６の端子に印加される。 At the same time, the addressing drive unit 54 transmits the selection voltage Vs to the selection electrode 52. The switch 18 of the first addressing circuit and the switch 38 of the second setting circuit are turned on, the bias voltage Vp is applied to the gate of the regulator 34 and the terminal of the capacitor 36, and the addressing voltage V Da is adjusted. Applied to the gate of the capacitor 14 and the terminal of the storage capacitor 16.

蓄電コンデンサー３６は放電し、次にバイアス電圧Ｖｐと等しい負の電位を充電する。この電圧は、蓄電コンデンサー３６により調整器３４のゲートに維持され、特に段階Ｈの間に、調整器３４のトリガー閾値電圧を徐々に低下させる。図４Ｅに点線の曲線により示されるように、ドレイン電流Ｉｄ２はゼロになり、段階Ｈの間、ゼロのままである。 The storage capacitor 36 is discharged and then charged with a negative potential equal to the bias voltage Vp. This voltage is maintained at the gate of the regulator 34 by the storage capacitor 36, and gradually reduces the trigger threshold voltage of the regulator 34, particularly during stage H. As indicated by the dotted curve in FIG. 4E, the drain current I d2 becomes zero and remains zero during stage H.

コンデンサー１６は電位ＶＤａを充電し、及びドレイン電流Ｉｄ１は、調整器１４のドレインとソースの間で生成される。段階Ｈの間、画像フレームの終了まで、発光体４は電流Ｉｄ１を供給される。 The capacitor 16 charges the potential V Da and the drain current I d1 is generated between the drain and source of the regulator 14. During phase H, the light emitter 4 is supplied with a current I d1 until the end of the image frame.

段階Ｇ及びＨの間、発光体４は従って第１のアドレス指定回路６により電流を供給される。段階Ｇ及びＨは従って共に、第１のアドレス指定回路の起動段階を形成する。更に、段階Ｇ及びＨの間、バイアス電圧は調整器３４のゲートに印加され、そのトリガー閾値電圧の変化を補償する。段階Ｅ及びＦはまた、従って共に、第２のアドレス指定回路のバイアス段階を形成する。   During stages G and H, the light emitter 4 is therefore supplied with current by the first addressing circuit 6. Stages G and H together thus form the start-up stage of the first addressing circuit. Further, during stages G and H, a bias voltage is applied to the gate of regulator 34 to compensate for changes in its trigger threshold voltage. Stages E and F also therefore together form a bias stage of the second addressing circuit.

段階Ｉの間、蓄電コンデンサー３６のアドレス指定を設定するため、及び同時に調整器３４のバイアスを設定するため、駆動装置４６はバイアス電圧Ｖｐを第１の電極４８へ送信し、及び画像データを表すアドレス指定電圧ＶＤｂを第２の電極５０へ送る。 During stage I, in order to set the addressing of the storage capacitor 36 and at the same time to set the bias of the regulator 34, the drive 46 sends a bias voltage Vp to the first electrode 48 and represents the image data. Addressing voltage V Db is sent to the second electrode 50.

選択スイッチ１８及び３８は、選択電圧Ｖｓを電極５２に印加することにより、同時に開かれる。バイアス電圧Ｖｐは、調整器１４のゲート及びコンデンサー１６に送信される。コンデンサー１６は放電しそして負に充電する。図４Ｅに実線の曲線により示されるように、ドレイン電流Ｉｄ１はゼロになり、段階Ｊの間、ゼロのままである。 The selection switches 18 and 38 are opened simultaneously by applying a selection voltage Vs to the electrode 52. The bias voltage Vp is transmitted to the gate of the regulator 14 and the capacitor 16. Capacitor 16 discharges and charges negatively. As shown by the solid curve in FIG. 4E, the drain current I d1 becomes zero and remains zero during stage J.

段階Ｉ及びＪの間、バイアス電圧Ｖｐは、調整器１４のゲートに印加される。段階Ｉ及びＪは従って共に、第１のアドレス指定回路６をバイアスする段階を形成する。   During stages I and J, a bias voltage Vp is applied to the gate of regulator 14. Stages I and J thus together form a stage for biasing the first addressing circuit 6.

同時に、バイアス電圧ＶＤｂは、電流調整器３４のゲート及びコンデンサー３６の端子に印加される。この電圧は、コンデンサー３６により調整器３４のゲートに維持され、段階Ｊの間及び新しい画像データの次の設定段階まで、発光体４に電力を供給するドレイン電流Ｉｄ２を生成する。 At the same time, the bias voltage V Db is applied to the gate of the current regulator 34 and the terminal of the capacitor 36. This voltage is maintained at the gate of the regulator 34 by the capacitor 36 and generates a drain current Id2 that supplies power to the light emitter 4 during stage J and until the next set stage of new image data.

段階Ｉ及びＪの間、発光体４は従って第２のアドレス指定回路１２により電流を供給される。これら段階は従って共に、第２のアドレス指定回路の起動段階を形成する。   During stages I and J, the light emitter 4 is therefore supplied with current by the second addressing circuit 12. Together these steps form the start-up phase of the second addressing circuit.

続いて、制御システム５６及び駆動装置４６及び５４は、選択のアドレス指定、アドレス指定及びバイアス電圧を以下のように制御する。これにより、正の極性のアドレス指定電圧は、第１のアドレス指定回路６の調整器１４のゲートに印加され、発光体４に電力を供給すると同時に、負の極性のバイアス電圧は、第２のアドレス指定回路１２の調整器３４のゲートに印加され、トリガー閾値電圧の変化を補償する。次に反対に、正の極性のアドレス指定電圧は、第２のアドレス指定回路１２の調整器３４のゲートに印加され、発光体４に電力を供給すると同時に、負の極性のバイアス電圧は、第１のアドレス指定回路６の調整器１４のゲートに印加され、トリガー閾値電圧の変化を補償する。   Subsequently, the control system 56 and the drivers 46 and 54 control the selection addressing, addressing and bias voltage as follows. As a result, a positive polarity addressing voltage is applied to the gate of the regulator 14 of the first addressing circuit 6 to supply power to the light emitter 4 and at the same time a negative polarity bias voltage is Applied to the gate of the regulator 34 of the addressing circuit 12 to compensate for changes in the trigger threshold voltage. Conversely, a positive polarity addressing voltage is applied to the gate of the regulator 34 of the second addressing circuit 12 to supply power to the light emitter 4 and at the same time a negative polarity bias voltage is 1 applied to the gate of the regulator 14 of the addressing circuit 6 to compensate for changes in the trigger threshold voltage.

発光体４は従って、調整器１４及び次に調整器３４により交互に調整された電流を供給される。   The illuminant 4 is therefore supplied with a current that is alternately regulated by the regulator 14 and then the regulator 34.

第１及び第２のアドレス指定回路６、１２は、交互に起動され発光体４に電流を供給する。   The first and second addressing circuits 6 and 12 are activated alternately to supply current to the light emitter 4.

調整器１４が発光体４に電力を供給する場合、調整器３４は高い負の電位に相当するバイアス電圧をそのゲートに印加することによりバイアスされ、前の段階の間に変化した調整器３４のトリガー閾値電圧をその初期値に戻す。   When the regulator 14 supplies power to the light emitter 4, the regulator 34 is biased by applying a bias voltage corresponding to a high negative potential to its gate, and the regulator 34 has changed during the previous phase. Return the trigger threshold voltage to its initial value.

その他の場合、調整器３４が発光体４に電力を供給する場合、調整器１４はこの同じ負のバイアス電圧によりバイアスされ、事前にある方向に変化されているそのトリガー閾値電圧を反対方向に変化する。従って、各発光体に関連する２つのアドレス指定回路の包含は、表示画面の調整器のトリガー閾値電圧の変化を補償する。   Otherwise, when the regulator 34 supplies power to the light emitter 4, the regulator 14 is biased by this same negative bias voltage and changes its trigger threshold voltage that has been changed in one direction in the opposite direction. To do. Thus, the inclusion of two addressing circuits associated with each light emitter compensates for changes in the trigger threshold voltage of the display screen regulator.

以上に説明された実施例では、本発明による１つの及び他のアドレス指定回路の起動の切り替えは、各画像フレームで行われる。しかしながら、本発明から逸脱することなく、この切り替えを各画像フレームにおいてではなく、複数の画像フレームの間に行うことも可能である。   In the embodiment described above, activation switching of one and other addressing circuits according to the present invention is performed in each image frame. However, it is possible to switch between multiple image frames instead of in each image frame without departing from the invention.

以上に説明された実施例では、バイアス及び起動段階は、同時に実行され等しい期間を有する。変形として、制御手段はまた、調整器１４及び３４を制御可能であり、第１及び第２の回路のバイアス及び起動段階は、同時に実行されるが、異なる期間を有する。   In the embodiment described above, the bias and start-up phases are performed simultaneously and have equal duration. As a variant, the control means can also control the regulators 14 and 34, wherein the biasing and activation phases of the first and second circuits are performed simultaneously but with different periods.

好適な実施の形態によると、発光体の１つ又は他の調整器に印加されたバイアス電圧は、１つの画像フレームから他の画像フレームへ、前のフレームの間にこの調整器に印加されたアドレス指定電圧に応じて変化する。望ましくは、このバイアス電圧は、前のフレームの前記アドレス指定電圧と等しいが反対の極性を有する。   According to a preferred embodiment, a bias voltage applied to one or other adjusters of the light emitter was applied to this adjuster during the previous frame from one image frame to another. Varies according to the addressing voltage. Desirably, this bias voltage is equal to the addressing voltage of the previous frame but has the opposite polarity.

発光体及び本発明の第１の実施例による画面の発光体の発光を制御する手段を表すブロック図である。It is a block diagram showing the light-emitting body and the means for controlling the light emission of the screen light-emitting body according to the first embodiment of the present invention. 第１の選択電極に印加された選択電圧を表すグラフである。It is a graph showing the selection voltage applied to the 1st selection electrode. 第２の選択電極に印加された電圧を表すグラフである。It is a graph showing the voltage applied to the 2nd selection electrode. アドレス指定電極に印加された電圧を表すグラフである。It is a graph showing the voltage applied to the addressing electrode. 第１の蓄電コンデンサーの端子間に印加された電圧、及び第２の蓄電コンデンサーの端子間に印加された電圧を表すグラフであるIt is a graph showing the voltage applied between the terminals of a 1st electrical storage capacitor, and the voltage applied between the terminals of a 2nd electrical storage capacitor. 第１の電流調整器に流れるドレイン電流、及び第２の電流調整器に流れるドレイン電流を表すグラフである。It is a graph showing the drain current which flows into the 1st current regulator, and the drain current which flows into the 2nd current regulator. 発光体に流れる電流を表すグラフである。It is a graph showing the electric current which flows into a light-emitting body. 発光体及び本発明の第２の実施例による画面の発光体の発光を制御する手段を表すブロック図である。It is a block diagram showing the means to control light emission of the light emitter and the screen light emitter according to the second embodiment of the present invention. 選択電極に印加された選択電圧を表すグラフである。It is a graph showing the selection voltage applied to the selection electrode. 第１のアドレス指定電極に印加された電圧を表すグラフである。4 is a graph representing a voltage applied to a first addressing electrode. 第２のアドレス指定電極に印加された電圧を表すグラフである。6 is a graph representing a voltage applied to a second addressing electrode. 第１の蓄電コンデンサーの端子間の電圧、及び第２の蓄電コンデンサーの端子間の電圧を表すグラフであるIt is a graph showing the voltage between the terminals of a 1st electrical storage capacitor, and the voltage between the terminals of a 2nd electrical storage capacitor. 第１の電流調整器に流れるドレイン電流、及び第２の電流調整器に流れるドレイン電流を表すグラフである。It is a graph showing the drain current which flows into the 1st current regulator, and the drain current which flows into the 2nd current regulator. 発光体に流れる電流を表すグラフである。It is a graph showing the electric current which flows into a light-emitting body.

Claims (13)

画像表示画面であって、
発光体の配列を形成するよう発光体の行及び発光体の列に配された発光体、配列の発光体の発光を制御する手段、を有し、前記手段は、
（ａ）前記発光体に電力を供給しゲート電極と２つの電流通過電極を有する第１の電流調整器、第１の電流調整器のゲート電極に電位を設定する第１の蓄電コンデンサーを有し、発光体を流れる電流を制御するよう配列の各発光体と関連付けられ、発光体をアドレス指定する第１の回路、
（ｂ）ゲート電極と２つの電流通過電極を有する前記発光体の第２の電流調整器、第２の電流調整器のゲート電極に電位を蓄積する第２の蓄電コンデンサーを有し、発光体毎に、発光体をアドレス指定する少なくとも１つの第２の回路、
（ｃ）前記第１の蓄電コンデンサー及び前記第２の蓄電コンデンサーに、画像データを表し及び前記画像データに従い発光体に電流を供給するため第１又は第２のアドレス指定回路の何れかをアクティブにするアドレス指定電圧を印加する、アドレス指定制御手段、を有し、
前記第１及び前記第２のアドレス指定回路は、同一の発光体と並列に配置され、
画面は、アドレス指定制御手段は、前記アドレス指定電圧の極性と反対の極性を有するバイアス電圧を、前記第１の電流調整器又は前記第２の電流調整器の何れかに設定する、
ことを特徴とする、画像表示画面。 An image display screen,
Light emitters arranged in rows of light emitters and columns of light emitters to form an array of light emitters, means for controlling light emission of the light emitters of the array, said means comprising:
(A) a first current regulator that supplies power to the light emitter and includes a gate electrode and two current passing electrodes; a first storage capacitor that sets a potential at the gate electrode of the first current regulator; A first circuit associated with each light emitter in the array to control the current flowing through the light emitter and addressing the light emitter;
(B) a second current regulator of the light emitter having a gate electrode and two current passing electrodes, a second storage capacitor for storing a potential in the gate electrode of the second current regulator, and each light emitter At least one second circuit for addressing the illuminant,
(C) activating either the first or second addressing circuit to represent the image data to the first storage capacitor and the second storage capacitor and to supply current to the light emitter in accordance with the image data An addressing control means for applying an addressing voltage to be
The first and second addressing circuits are arranged in parallel with the same light emitter,
In the screen, the addressing control means sets a bias voltage having a polarity opposite to the polarity of the addressing voltage in either the first current regulator or the second current regulator.
An image display screen characterized by that. アドレス指定制御手段は、前記第１の電流調整器に最初にアドレス指定電圧を印加し、第１のアドレス指定回路を起動する段階を開始し、次にバイアス電圧を印加し、第１のアドレス指定回路をバイアスする段階を開始する、ことを特徴とする、請求項１記載の表示画面。   The addressing control means first applies an addressing voltage to the first current regulator to start a first addressing circuit, and then applies a bias voltage to apply the first addressing The display screen according to claim 1, wherein the step of biasing the circuit is started. アドレス指定手段は、前記第２の電流調整器に最初にアドレス指定電圧を印加し、第２のアドレス指定回路を起動する段階を開始し、次にバイアス電圧を印加し、第２のアドレス指定回路をバイアスする段階を開始し、第１のアドレス指定回路を起動する段階は、第２のアドレス指定回路をバイアスする段階と同期し、第２のアドレス指定回路を起動する段階は、第１のアドレス指定回路をバイアスする段階と同期する、ことを特徴とする、請求項２記載の表示画面。   The addressing means first applies an addressing voltage to the second current regulator to start a second addressing circuit, and then applies a bias voltage to the second addressing circuit. The step of starting the first addressing circuit is synchronized with the step of biasing the second addressing circuit, and the step of starting the second addressing circuit includes the step of starting the first addressing circuit. The display screen according to claim 2, wherein the display screen is synchronized with the step of biasing the designated circuit. 制御手段は、選択制御手段を有し、前記選択制御手段は、
発光体の第１のアドレス指定回路毎に、前記アドレス指定電圧又は前記バイアス電圧の前記第１の蓄電コンデンサー及び前記第１の電流調整器の前記ゲートへの送信を、前記発光体を選択するために、選択電圧に応じて駆動する、第１の選択スイッチ、
同一の発光体の第２のアドレス指定回路毎に、前記アドレス指定電圧又は前記バイアス電圧の前記第２の蓄電コンデンサー及び前記第２の電流調整器の前記ゲートへの送信を、前記発光体を選択するために、前記選択電圧に応じて駆動する、第２の選択スイッチ、及び
前記第１及び第２の選択スイッチを駆動する手段、
を有する、前記請求項の何れか１項記載の表示画面。 The control means includes selection control means, and the selection control means includes:
In order to select the light emitter for transmission of the addressing voltage or the bias voltage to the first storage capacitor and the gate of the first current regulator for each first addressing circuit of the light emitter. A first selection switch that is driven according to the selection voltage;
For each second addressing circuit of the same light emitter, the light emitter is selected to transmit the addressing voltage or the bias voltage to the second storage capacitor and the gate of the second current regulator. A second selection switch that drives according to the selection voltage, and means for driving the first and second selection switches;
The display screen according to claim 1, comprising: 駆動手段は、
発光体の各行に、制御するためそれぞれ第１及び第２の選択スイッチに接続された第１及び第２の選択電極、及び
最初に前記選択電圧を前記第１の選択電極へ、次に前記選択電圧を前記第２の選択電極へ交互に送信する選択駆動装置、
を更に有することを特徴とする、請求項４記載の表示画面。 The driving means is
Each row of light emitters has first and second select electrodes connected to first and second select switches, respectively, for control, and first the select voltage to the first select electrode and then the select A selective driving device for alternately transmitting a voltage to the second selection electrode;
The display screen according to claim 4, further comprising: アドレス指定制御手段は、
第１及び第２の選択スイッチと接続された、発光体の各列のアドレス指定電極、及び
前記アドレス指定電圧及び前記バイアス電圧を前記アドレス指定電極へ交互に送るアドレス指定駆動装置、
を有することを特徴とする、請求項５記載の表示画面。 Addressing control means
An addressing electrode for each column of light emitters connected to the first and second selection switches; and an addressing drive for alternately sending the addressing voltage and the bias voltage to the addressing electrode;
The display screen according to claim 5, further comprising: 駆動手段は、
制御するため第１及び第２の選択スイッチと接続された、発光体の各行の選択電極、及び
前記選択電圧を第１及び第２の選択スイッチへ同時に送る選択駆動装置、
を有することを特徴とする、請求項４記載の表示画面。 The driving means is
A selection electrode connected to the first and second selection switches for control, and a selection drive for simultaneously sending the selection voltage to the first and second selection switches,
The display screen according to claim 4, further comprising: アドレス指定制御手段は、
それぞれ第１及び第２の選択スイッチと接続された、発光体の各列の第１及び第２のアドレス指定電極、及び
前記アドレス指定電圧又は前記バイアス電圧の何れかを第１の前記アドレス指定電極と前記第２のアドレス指定電極へ同時に送るアドレス指定駆動装置、
を有することを特徴とする、請求項７記載の表示画面。 Addressing control means
First and second addressing electrodes of each column of light emitters connected to first and second selection switches, respectively, and either the addressing voltage or the bias voltage as the first addressing electrode And an addressing drive for sending simultaneously to the second addressing electrode,
The display screen according to claim 7, further comprising: 表示画面のアドレス指定方法であって、
前記画像表示画面は、発光体、発光体に接続された第１の電流調整器及び第１の電流調整器のゲートに電位を蓄積する第１の蓄電コンデンサーを有する第１のアドレス指定回路、前記発光体に接続された第２の電流調整器及び第２の電流調整器のゲートに電位を蓄積する第２の蓄電コンデンサーを有する第２アドレス指定回路を有し、各電流調整器は特にゲート電極及びソース電極を有し、各電流調整器はゲート電極とソース電極の間にトリガー閾値電圧より大きい電圧が印加された場合、電流調整器を流れる電流を有し、
前記方法は、各発光体を駆動するために、
電流を発光体に供給するため第１のアドレス指定回路を起動する段階、
第２の調整器のトリガー閾値電圧を変化するため第２のアドレス指定回路をバイアスする段階、
電流を発光体に供給するため第２のアドレス指定回路を起動する段階、
第１の調整器のトリガー閾値電圧を変化するため第１のアドレス指定回路をバイアスする段階、
を有し、
第１のアドレス指定回路を起動する段階は、第２のアドレス指定回路をバイアスする段階と同期し、
及び
第２のアドレス指定回路を起動する段階は、第１のアドレス指定回路をバイアスする段階と同期する、
ことを特徴とする、アドレス指定方法。 A display screen addressing method,
The image display screen includes a first addressing circuit having a light emitter, a first current regulator connected to the light emitter, and a first storage capacitor that stores a potential in a gate of the first current regulator, A second current regulator connected to the light emitter and a second addressing circuit having a second storage capacitor for storing a potential in the gate of the second current regulator, each current regulator having a gate electrode And each current regulator has a current flowing through the current regulator when a voltage greater than the trigger threshold voltage is applied between the gate electrode and the source electrode,
The method involves driving each light emitter
Activating a first addressing circuit to supply current to the light emitter;
Biasing the second addressing circuit to change the trigger threshold voltage of the second regulator;
Activating a second addressing circuit to supply current to the light emitter;
Biasing the first addressing circuit to change the trigger threshold voltage of the first regulator;
Have
The step of activating the first addressing circuit is synchronized with the step of biasing the second addressing circuit;
And activating the second addressing circuit is synchronized with the step of biasing the first addressing circuit;
An addressing method characterized by that. 第１のアドレス指定回路を起動する１つ以上の段階の次に、第１のアドレス指定回路をバイアスする少なくとも１つの段階が続き、及び第２のアドレス指定回路を起動する１つ以上の段階の次に、第２のアドレス指定回路をバイアスする少なくとも１つ以上の段階が続く、ことを特徴とする請求項９記載のアドレス指定方法。   The one or more stages for activating the first addressing circuit are followed by at least one stage for biasing the first addressing circuit, and one or more stages for activating the second addressing circuit. 10. The addressing method of claim 9, wherein the method further comprises at least one step of biasing the second addressing circuit. 画像データを表すアドレス指定電圧を前記第１の蓄電コンデンサーに印加することによる、前記第１の蓄電コンデンサーのアドレス指定設定段階、
第１の蓄電コンデンサーにより蓄えられた電位の極性と反対の極性を有するバイアス電圧を前記第１の電流調整器に印加することによる、前記第１の調整器のバイアス設定段階、
前記バイアス電圧を前記第２の電流調整器に印加することによる、前記第２の調整器のバイアス設定段階、及び
前記アドレス指定電圧を前記第２の蓄電コンデンサーに印加することによる、前記第２の蓄電コンデンサーのアドレス指定設定段階、
を有することを特徴とする、請求項９又は１０記載のアドレス指定方法。 Addressing and setting the first storage capacitor by applying an addressing voltage representing image data to the first storage capacitor;
A bias setting step of the first regulator by applying to the first current regulator a bias voltage having a polarity opposite to the polarity of the potential stored by the first storage capacitor;
Applying the bias voltage to the second current regulator, setting a bias of the second regulator, and applying the addressing voltage to the second storage capacitor, Storage capacitor addressing setting stage,
11. The addressing method according to claim 9 or 10, characterized by comprising: 前記第１の電流調整器のバイアス設定段階の次に、第２の蓄電コンデンサーのアドレス指定設定段階が続き、及び交代に前記第２の電流調整器のバイアス設定段階の次に、第１の蓄電コンデンサーのアドレス指定設定段階が続く、ことを特徴とする、請求項１１記載のアドレス指定方法。   The bias setting stage of the first current regulator is followed by an addressing and setting stage of a second storage capacitor, and alternately, the first storage battery is followed by the bias setting stage of the second current regulator. 12. The addressing method according to claim 11, further comprising a capacitor addressing setting step. 前記第２の電流調整器の前記バイアス設定段階は、前記第１の蓄電コンデンサーの前記アドレス指定設定段階と同時であり、及び前記第１の電流調整器の前記バイアス設定段階は、前記第２の蓄電コンデンサーの前記アドレス指定設定段階と同時である、ことを特徴とする、請求項１１記載のアドレス指定方法。   The bias setting stage of the second current regulator is simultaneous with the addressing setting stage of the first storage capacitor, and the bias setting stage of the first current regulator is the second current regulator. The addressing method according to claim 11, wherein the addressing method is simultaneous with the addressing setting step of the storage capacitor.
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EP1700290B1 (en) 2019-01-16
KR20060135670A (en) 2006-12-29
WO2005073948A1 (en) 2005-08-11
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KR101205912B1 (en) 2012-11-28
JP5074769B2 (en) 2012-11-14

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