KR19990001442A - Capacitor Manufacturing Method - Google Patents

Abstract

The present invention relates to a method for manufacturing a capacitor, the method comprising: forming a sidewall on a side of a gate electrode on a semiconductor substrate on which a transistor including a gate electrode and an impurity region is formed, exposing an impurity region and covering the gate electrode including the sidewall; Forming a first insulating layer, forming a polysilicon layer to cover a first insulating layer corresponding to a portion of the gate electrode including the exposed impurity region and the sidewalls, and forming a plurality of trenches in the polysilicon layer Forming step.

Therefore, in the present invention, by forming the storage electrode in the trench structure, it is possible to increase the storage capacity stably.

Description

Capacitor Manufacturing Method

The present invention relates to a method for manufacturing a capacitor, and more particularly, to a method for manufacturing a capacitor suitable for increasing the capacitance by increasing the surface area of a storage electrode.

Many studies have been conducted to increase the storage density so that the capacitor has a constant capacitance even if the cell area is reduced due to the high integration of the semiconductor.

In order to increase the storage density, there is a method of forming a capacitor in a three-dimensional structure of a stack or a trench.

The laminated structure among the capacitors having the three-dimensional structure is a structure that is easy to manufacture and suitable for mass productivity, while increasing the storage capacity and being immune to the disturbance of charge information caused by alpha particles.

Multilayer capacitors are classified into a double stacked structure, a fin structure or a crown structure according to the storage electrode.

1A to 1D are capacitor manufacturing process steps according to the prior art, which will be described with reference to the accompanying drawings.

Referring to FIG. 1A, a field oxide layer 102 defining an active region and a field region of a device is formed on a semiconductor substrate 100.

The gate electrode 106 is formed by interposing a gate oxide layer 104 on the device region of the semiconductor substrate 100 and used as a source / drain region in an active region on both sides of the gate electrode 106. The transistor is formed by forming the impurity diffusion region 110.

In the transistor, sidewalls 108 are formed on side surfaces of the gate electrode 106.

Silicon oxide and silicon nitride are sequentially deposited on the entire surface of the above structure by CVD (Chemical Vapor Deposition) to form the first insulating layer 112 and the etch sperm layer 114.

Subsequently, after the photoresist is applied to the etch stop layer 114, the photoresist is exposed and developed to be patterned to cover the impurity region 110 to form a first mask pattern (not shown).

Next, the etching stop layer 114 and the first insulating layer 112 are etched using the first mask pattern as a mask to form contact holes 115 exposing the impurity regions 108.

Subsequently, the first mask pattern is removed.

Referring to FIG. 1B, the first polysilicon layer 116 and the second insulating layer 118 are sequentially formed on the etch stop layer 114 to fill the contact hole 115.

In this case, silicon oxide is deposited by the CVD method as the second insulating layer 118.

Subsequently, after the photoresist is coated on the second insulating layer 118, the photoresist is exposed and developed to expose the gate electrode 106 including the sidewalls 108 and the second insulating layer 118 at a portion corresponding to the impurity region 110. The second mask pattern (not shown) is formed by patterning the semiconductor layer to cover the gap.

Next, the second insulating layer 118 is etched using the second mask pattern as a mask so that the first polysilicon layer 116 of the portion corresponding to the impurity region 110 is exposed.

Next, the second mask pattern is removed.

Then, the second polysilicon layer 120 is formed to cover the first polysilicon layer 116 and the remaining second insulating layer 118 exposed on the surface.

At this time, the second polysilicon layer 120 is in contact with the exposed portion of the first polysilicon layer 116 is electrically connected.

Subsequently, after the photoresist is applied to the second polysilicon layer 120, the photoresist is exposed and developed to be patterned to cover a part of the gate electrode 106 including the impurity region 110 and the sidewall 108 to form a third mask pattern. And form 122.

Referring to FIG. 1C, the second polycrystalline silicon layer 128, the second insulating layer 118, and the first polycrystalline silicon layer 116 are dry-etched using the third mask pattern 122 as a mask. A storage electrode 130 is formed.

In this case, the second polycrystalline silicon layer 120, the second insulating layer 118, and the first polycrystalline silicon layer 116 are removed by dry etching using the third mask pattern 122 as a mask, and then the remaining second The insulating layer 118 is removed under HF solution treatment as a wet etching solution.

Next, the third mask pattern 122 is removed.

Referring to FIG. 1D, the dielectric layer 124 is formed on the surface of the storage electrode 130. The dielectric layer 124 may be formed of silicon oxide or silicon nitride / silicon oxide.

However, in the conventional capacitor manufacturing method, in order to increase the capacitor capacity, the first and second polysilicon layers must be formed thick enough to increase the sidewall height. As the height of the sidewall increases, the storage electrodes are balanced. It is unstable because it does not fit, and the process itself is complicated.

Accordingly, an object of the present invention is to provide a capacitor manufacturing method for stably forming a storage electrode and increasing the capacitance of the capacitor.

Another object of the present invention is to provide a method for producing a capacitor with a simple process.

In order to achieve the above objects, the present invention provides a method of forming a sidewall on a side surface of a gate electrode on a semiconductor substrate on which a transistor including a gate electrode and an impurity region is formed, and exposing the impurity region and covering the gate electrode including the sidewall. Forming a polysilicon layer to cover the first insulating layer corresponding to a portion of the gate electrode including the exposed impurity region and the sidewall; and forming a plurality of trenches in the polysilicon layer. Forming step.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

1A to 1D are capacitor manufacturing process diagrams according to the prior art,

2A to 2D are capacitor manufacturing process diagrams of the present invention.

* Description of the symbols for the main parts of the drawings *

100, 200. Semiconductor substrate 102, 202. Field oxide layer

104, 204. Gate oxide layer 106, 206. Gate electrode

108, 1208. Sidewalls 110, 210. Impurity regions

112, 118, 212. Insulation layer 114. Etch stop layer

122, 216. Mask patterns 130, 230. Storage electrodes

116, 120, 124, 214, 214-1. Polycrystalline Silicon Layer

2A through 2D are capacitor manufacturing process diagrams in accordance with the teachings of the present invention.

Referring to FIG. 2A, a field oxide layer 202 defining an active region and a field region of a device is formed on a semiconductor substrate 200.

The gate electrode 206 is formed by interposing the gate oxide layer 204 on the device region of the semiconductor substrate 200, and the impurity diffusion region 210 used as a source / drain region in the active region on both sides of the gate electrode 206. ) To form a transistor.

The transistor forms sidewalls 28 on the side of the gate electrode 106.

Silicon oxide is deposited on the entire surface of the structure described above by CVD to form a first insulating layer 212.

Subsequently, after the photoresist is applied on the first insulating layer 212, the first mask is exposed and developed to cover the impurity region 210 of the first insulating layer 212 and the first insulating layer 212 corresponding to the first insulating layer 212. A pattern (not shown in the figure) is formed.

Next, the first insulating layer 212 is etched using the first mask pattern as a mask to form a contact hole 213 exposing the impurity region 210.

Subsequently, the first mask pattern is removed.

Referring to FIG. 2B, the polysilicon layer 214 is formed to a sufficient thickness to cover the exposed impurity region 210 and the remaining first insulating layer 212.

Next, after the photoresist is applied to the polysilicon layer 214, it is exposed and developed to cover the polysilicon layer 214 corresponding to a part of the gate electrode 206 including the impurity region 210 and the sidewall 208. The second mask pattern 216 is formed to be formed.

Referring to FIG. 2C, after etching the polysilicon layer 214 using the second mask pattern 216 as a mask, the second mask pattern 216 is removed.

Referring to FIG. 2D, after the photoresist is applied to the remaining polysilicon layer 214, a third mask pattern (not shown) is applied to the remaining polysilicon layer 214 at a predetermined interval by exposure and development. Form.

Subsequently, the remaining polysilicon layer 214 is etched to a predetermined depth using the third mask pattern as a mask to form a storage electrode 230 having trenches.

Next, the third mask pattern is removed.

Subsequently, the dielectric layer 216 is formed to cover the storage electrode 214-1.

As described above, in the capacitor manufacturing method of the present invention, by forming the storage electrode in the trench structure, the storage capacity can be increased stably.

And the process itself has a simple advantage.

Claims (1)

Forming a sidewall on a side surface of the gate electrode on a semiconductor substrate having a transistor including a gate electrode and an impurity region; Forming a first insulating layer to expose the impurity region and cover the gate electrode including the sidewall; Forming a polysilicon layer to cover the first insulating layer corresponding to a portion of the gate electrode including the exposed impurity region and the sidewall; And forming a plurality of trenches in the polycrystalline silicon layer.