KR19980083855A - Transfer rail of handler for semiconductor chip package test - Google Patents

Abstract

The present invention relates to a transfer rail of a handler for testing a semiconductor chip package, and because the lower rail and the cover rail are not accurately aligned and fastened to the base rail, the semiconductor chip package may be caught on the transfer rail. Regardless of proficiency, the first insertion pin is installed at a predetermined interval on an upper portion of the base rail that can be fastened and fixed in a state where the lower rail and the cover rail are easily aligned with the base rail, and the lower portion corresponds to the first insertion pin. When the lower rail is fastened to the base rail by forming the first insertion hole in the rail, the lower rail is fastened to the base rail by a fastening screw with the first insertion pin inserted into the first insertion hole and the lower rail aligned to the base rail. The cover rail is installed on the lower rail before the fastening and fixing. Disclosed is a transfer rail of a handler for testing a semiconductor chip package having a structure in which a cover rail is fastened and fixed to a lower rail while the second insertion pin is inserted into and aligned with a second insertion hole formed in the lower rail corresponding to the second insertion pin. It is.

Description

Transfer rail of handler for semiconductor chip package test

The present invention relates to a transfer rail of a handler for testing a semiconductor chip package, and more particularly, a transfer rail of a handler for testing a semiconductor chip package capable of smoothly transferring a semiconductor chip package between an upper rail and a cover rail installed in a base rail. It is about.

In general, a semiconductor chip package manufactured by a semiconductor chip package manufacturing process undergoes reliability tests such as an electrical property test and a function test before shipment.

Here, a handler is used as a device for testing the manufactured semiconductor chip package and classifying the tested semiconductor chip package.

In the semiconductor chip package test handler, the semiconductor chip packages are sequentially supplied and tested, and a vertical handler which classifies each semiconductor chip package according to the progress result, and a tray containing a plurality of semiconductor chip packages are provided in the tray. The test is performed in a state where the semiconductor chip package is stored, and there is a horizontal handler that classifies the semiconductor chip package into bins from the tested tray to the new tray according to the test result.

The vertical handler includes a stacking unit in which tubes containing semiconductor chip packages are stacked in sequence, a transfer unit for sequentially transferring the loaded tubes to the supply unit one by one, a supply unit supplying the semiconductor chip package transferred to the transfer unit to the tester unit, and a semiconductor supplied from the supply unit And a head unit for transferring the chip package to the tester unit, a classifying unit for classifying the tested semiconductor chip package as a sending track, and a sending unit for sending out the semiconductor chip packages classified by the classifying unit. In the vertical handler, since the semiconductor chip package moves by free fall due to the earth's gravity, the semiconductor chip package separated from the tube loaded in the loading unit moves along the transfer rail installed in the vertical handler.

1 is a perspective view of the transfer rail of the handler for testing a semiconductor chip package according to the prior art.

FIG. 2 is a plan view illustrating a state in which a semiconductor chip package moves along a transfer rail of FIG. 1.

Referring to FIGS. 1 and 2, a transfer rail of a handler for testing a semiconductor chip package according to the prior art will be described. The transfer rail 100 includes a base rail 10 and a base rail 10 fixed to a body of the handler. It is fastened to the upper surface of the, substantially has a structure in which the lower rail 20 and the cover rail 30 through which the semiconductor chip package passes.

In more detail, the structure of the base rail 10, the lower rail 20 and the cover rail 30 constituting the transfer rail 100, the base rail 10 has a predetermined interval on the upper surface 2 Fastening holes 14 are formed.

The lower surface of the lower rail 20 is laminated and fastened to the upper surface of the base rail 10, and the fastening portion 21 to which the cover rail 30 is fastened and the rail portion 29 through which the semiconductor chip package passes. Has That is, the fastening portion 21 of the lower rail has two first fastening holes 24 formed to correspond to the position of the fastening hole 14 of the base rail, and a cover rail (between the first fastening holes 24). Two second fastening holes 25 capable of fastening 30 are formed at predetermined intervals. The rail portion 29 of the lower rail is formed at a predetermined interval with respect to one surface on which the first and second fastening holes 24 and 25 are formed, and the bottom surface 28 to which the package body of the semiconductor chip package contacts. ) And a guide 26 for preventing the semiconductor chip package from being separated are formed long on both sides at predetermined intervals along the bottom surface 28 to be stepped upward with respect to the bottom surface 28. Of course, the gap between the guides 26 has a gap through which the semiconductor chip package can pass, and when the semiconductor chip package passes, the lead of the semiconductor chip package is positioned in the guide 26.

The cover rail 30 has a fastening portion 31 fastened to the upper surface of the fastening portion 21 of the lower rail and a rail portion 39 to which the semiconductor chip package is moved. The fastening part 31 of the cover rail has a third fastening hole 35 formed to correspond to the second fastening hole 25 of the lower rail. The rail portion 39 of the cover rail is formed at a predetermined interval with respect to the fastening portion 31, and the ceiling 38 and the semiconductor chip package to be located close to the upper surface of the package body of the semiconductor chip package. Guide 36 for preventing the separation is formed long on both sides at a predetermined interval along the ceiling 38 to step down downward with respect to the ceiling (38). Of course, the spacing between the guide 36 has a spacing through which the semiconductor chip package can pass, and is formed wider than the spacing of the guide 26 of the cover rail.

When the lower rail 20 and the cover rail 30 are fastened to the base rail 10 having the structure as described above and the transfer rail 100 is installed, the fastening hole 14 and the lower rail of the base rail will be described. In the state in which the first fastening hole 24 is aligned, the lower rail 20 is fastened and fixed to the base rail 10 by using fastening means such as fastening screw 40. Fastening like the fastening screw 45 in a state in which the second fastening hole 25 of the lower rail and the third fastening hole 35 of the cover rail are aligned while the lower rail 20 is fastened to the base rail 10. The fastening part 31 of the cover rail is fastened to the fastening part 21 of the lower rail by means of fastening and fixing to complete the installation of the transfer rail 100. When the cover rail 30 is fastened to the lower rail 20, the rails 29 and 39 are spaced apart from each other by a predetermined interval so that the semiconductor chip package can pass therethrough. 2 illustrates a state in which the semiconductor chip package 50 moves along the transfer rail 100, and a cover rail is removed from the lower rail 20 to illustrate a state in which the semiconductor chip package 50 moves. The state is shown.

Since the conveying rail having such a structure has a bolt fixing method using fastening means such as fastening screw when fastening the lower rail to the base rail and the cover rail to the lower rail, the inner diameter of the fastening hole is 0.3 than the diameter of the fastening screw. It is designed as large as ~ 0.5mm. Therefore, as shown in FIG. 3, the lower rail 20 may not be accurately fastened to the base rail 10 by the tolerance a between the first fastening hole 24 and the fastening screw 40, and left and right flows may occur. As a result, the semiconductor chip package 50 may be caught by the guide 26 of the lower rail. In addition, the tolerance (a) between the fastening screw 40 and the first fastening hole 24 is a position where the lower rail 20 is installed according to the skill of the installer who installs the lower rail 20 on the base rail 10. Since the above problem occurs.

Accordingly, an object of the present invention is to provide a transfer rail of a handler for testing a semiconductor chip package that can solve a problem that a semiconductor chip package is caught by a transfer rail because the lower rail and the cover rail are not accurately aligned and fastened to the base rail.

Another object of the present invention is to provide a transfer rail of a handler for testing a semiconductor chip package that can easily fasten a lower rail and a cover rail to a base rail regardless of the skill of the installer.

1 is a perspective view of the transfer rail of the handler for testing a semiconductor chip package according to the prior art.

FIG. 2 is a plan view illustrating a state in which a semiconductor chip package moves along a transfer rail of FIG. 1. FIG.

3 is a plan view showing a state in which a semiconductor chip package is caught by a transfer rail;

Figure 4 is a perspective view of the coupling of the transfer rail of the handler for testing semiconductor chip package according to the present invention.

FIG. 5 is a plan view illustrating a state in which a semiconductor chip package moves along a transfer rail of FIG. 4. FIG.

FIG. 6 is an enlarged plan view of portion A of FIG. 5;

7 is a front view illustrating a state in which a semiconductor chip package is inserted into a transfer rail of FIG. 4.

※ Description of the main parts of the drawings ※

110: base rail 112, 127: insertion pin

114, 124, 125, 135: fastening hole 120: lower rail

121, 131: fastening portion 123, 137: insertion hole

129, 139: rail portion 130: cover rail

140, 145: fastening screw 200: feed rail

In order to achieve the above object, a base rail having a first fastening hole formed between the plurality of first insertion pins and the first insertion pins formed at predetermined intervals on one surface; The first insertion hole is formed to correspond to the first insertion pin of the base rail, and the semiconductor chip package can pass through the lower fastening portion and the lower fastening portion formed with a second fastening hole corresponding to the first fastening hole. A lower rail having a lower rail portion capable of being opened; Fastening means for fastening the lower rail to one surface of the base rail in a state in which the first fastening hole and the second fastening hole are aligned; And a cover rail fastened at predetermined intervals so as to correspond to a surface of the upper fastening portion fastened to the lower fastening portion and an upper rail portion through which the semiconductor chip package can pass outside the upper fastening portion to face the lower rail portion. It provides a transfer rail of the handler for semiconductor chip package test comprising a.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

4 is a perspective view of the transfer rail of the handler for testing a semiconductor chip package according to the present invention.

5 is a plan view illustrating a state in which a semiconductor chip package moves along a transfer rail of FIG. 4.

6 is an enlarged plan view of a portion A of FIG. 5.

7 is a front view illustrating a state in which a semiconductor chip package is inserted into a transfer rail of FIG. 4.

Referring to FIG. 4, a transfer rail of the handler for testing a semiconductor chip package according to the present invention will be described. The transfer rail 200 may include a base rail 110 fixed to a body of the handler and a semiconductor chip package substantially passing therethrough. The lower rail 120 and the cover rail 130 have a structure in which the lower rail 120 and the cover rail 130 are sequentially fastened to the upper surface of the base rail 110.

In more detail with respect to the structure of the base rail 110, the lower rail 120 and the cover rail 130 constituting the transfer rail 100, the base rail 110 has a lower rail 120 on the upper surface Two first insertion pins 112 are provided at predetermined positions at predetermined positions, and a first fastening hole 114 is formed between the first insertion pins 112.

In FIG. 4, two transfer rails 200 in which two semiconductor chip packages can pass through one base rail 110 are provided at predetermined intervals. Therefore, the above description describes a structure in which the lower rail 120 and the cover rail 130 positioned on the left side of the rails installed on the base rail 110 are fastened. 120 and the cover rail 130 will be described based on the structure fastened to the base rail (110). In addition, although FIG. 4 illustrates a transfer rail 200 provided with two rails, two or more rails may be installed on the base rail. If so, the area of the upper surface of the base rail will have to be larger.

The lower rail 120 has a lower surface fastened to the base rail 110, and an upper surface thereof has a fastening portion 121 to which the cover rail 130 is fastened and a rail portion 129 through which the semiconductor chip package passes. Here, the fastening part 121 of the lower rail is formed with a first insertion hole 123 into which the first insertion pin 112 of the base rail is to be inserted, and a second insertion pin outside the first insertion hole 123. 127 is provided. The second fastening hole 124 is formed to correspond to the first fastening hole 114 of the base rail, and the fourth fastening of the cover rail is formed between the second fastening hole 124 and the first insertion hole 123. The third fastening hole 125 is formed to correspond to the hole 135. Here, the second insertion pin 127, the first insertion hole 123, the second fastening hole 124 and the third fastening hole 125 formed in the fastening portion 121 of the lower rail are formed in a row in the present invention. The first insertion hole 123 is formed between the second insertion pins 127, and the second fastening hole 124 and the third fastening hole 125 are sequentially formed between the first insertion holes 123. Has a formed structure. In addition, since the rail part 129 of the lower rail is the same as the rail part of the lower rail according to the prior art, description thereof will be omitted.

The cover rail 130 corresponds to the fastening part 121 of the lower rail and includes a rail part 139 through which the semiconductor chip package passes at a position facing the fastening part 131 to be fastened and the rail part 129 of the lower rail. Have Here, the fastening portion 131 of the cover rail is formed with a second insertion hole 137 to correspond to the second insertion pin 127 of the lower rail, the position corresponding to the third fastening hole 125 of the lower rail Has a structure in which a fourth fastening hole 135 is formed. In addition, since the rail part 139 of the cover rail is the same as the rail part of the cover rail according to the prior art, description thereof will be omitted.

When the base rail 110, the lower rail 120 and the cover rail 130 having the structure as described above is fastened to explain the structure in which the transfer rail 200 is installed, first, the lower rail 120 on the base rail 110 ) Is installed. In more detail, the lower rail 120 is aligned and stacked on the upper surface of the base rail 110 by inserting the first insertion pin 112 into the first insertion hole 123. In addition, in the state in which the lower rail 120 is aligned and stacked on the base rail 110 as described above, the fastening screw 140 in the first fastening hole 114 and the second fastening hole 124 formed at positions corresponding to each other. Fasten and fasten with a fastening means such as.

Referring to the structure in which the cover rail 130 is installed after the lower rail 120 is installed on the base rail 110, the second rail is inserted into the second insertion hole 137 to fasten the lower rail. The fastening part 131 of the cover rail is aligned and stacked on the part 121. In addition, as the fastening screw 145 in the third fastening hole 125 and the fourth fastening hole 135 formed at positions corresponding to each other in a state in which the cover rail 130 is stacked on the lower rail 120 as described above. Installation of the transfer rail 200 is completed by fastening and fastening with the fastening means. 4 illustrates a transfer rail 200 in which a base rail and a lower rail are fastened to a cover rail in order. As shown in FIG. 7, the rail parts 129 and 139 are spaced apart at predetermined intervals so that the semiconductor chip package 150 may pass through when the cover rail 130 is fastened to the lower rail 120. The transfer rail 200 has a structure. The package body 154 of the semiconductor chip package is in contact with the bottom surface 128 of the lower rail. When the lead 152 of the semiconductor chip package is a gull wing type, one surface of the package body 54 is formed. The guide 126 of the lower rail is positioned between the lead 152 portion parallel to the bent lead 152 portion.

5 and 6 illustrate a state in which the semiconductor chip package 150 moves along the transfer rail 200. In order to illustrate a state in which the semiconductor chip package 150 moves, the cover rail includes a lower rail ( The state removed at 120 is shown.

When comparing the structure of the fastening portions 121 and 131 of the transfer rail according to the present invention and the structure of the fastening portion according to the prior art with reference to Figures 5 and 6, the fastening portion of the lower rail according to the prior art The fastening means is fixed to the base rail using only fastening means. Therefore, in the related art, if the lower rail cannot be fastened in the state where the lower rail is accurately aligned with the base rail due to the tolerance between the fastening screw and the fastening hole, as shown in FIG. A problem has occurred. However, in the present invention, the first insertion pin 112 installed in the base rail 110 is inserted into the first insertion hole 123 formed in the fastening portion 121 of the lower rail, and thus, the lower rail in the base rail 110 primarily. Since the 120 is fastened using the fastening screw 140 in an aligned state, the lower rail 120 may be fastened and fixed to the base rail 110 accurately.

More specifically, conventionally, since only the fastening screw is used to install the lower rail on the base rail, the tolerance should be 0.3 to 0.5 mm, and by repeating the operation of separating or fastening the lower rail to the base rail for repair. The tolerance becomes larger, making it difficult to fasten and fix the lower rail to the base rail accurately. In addition, the skill of the installer is required for accurate alignment and fastening.

However, in the present invention, the lower rail 120 is aligned with the base rail 110 by inserting the first insertion pin 112 of the base rail into the first insertion hole 123 of the lower rail. Then, the lower rail 120 is fastened and fixed to the base rail 110 using the fastening screw 140. Here, the tolerance (cb) between the outer diameter (b) of the first insertion pin and the inner diameter (c) of the first insertion hole can be processed smaller than the tolerance between the fastening screw and the fastening hole according to the prior art, the base rail ( When the lower rail 120 is fastened to or detached from the 110, the lower rail 120 is aligned with the base rail 110 by inserting the first insertion pin 112 into the first insertion hole 123. Therefore, the wear between the first insertion pin 112 and the first insertion hole 123 according to the insertion can be almost ignored as compared to the wear of the conventional fastening screw and the fastening hole is the base rail 110 and the lower portion according to the present invention Alignment reliability between the rails 120 can be secured, and even if the lower rail 120 is fastened and fixed to the base rail 110 with the fastening screws 140 in a state where the alignment reliability is secured, the possibility of misalignment of the aligned positions is reduced. . Of course, the tolerance e-d between the diameter d of the fastening screw according to the invention and the inner diameter of the fastening hole e is equal to the tolerance between the diameter of the fastening screw according to the prior art and the inner diameter of the fastening hole. In addition, when the cover rail 130 is fastened to the lower rail 120, the second insertion pin 127 is installed on the lower rail 120 for the same reason as described above, and the second insertion pin 127 corresponds to the second insertion pin 127. An insertion hole 137 was formed in the cover rail 130.

Therefore, according to the structure of the present invention, since the lower rail and the cover rail are fastened and fixed in a state in which the base rail is accurately aligned in order, there is an advantage in that the problem that the semiconductor chip package is caught by the transfer rail can be solved.

Further, since the lower rail and the cover rail of the transfer rail are easily aligned and fastened, there is an advantage that the transfer rail can be easily installed without being greatly influenced by the skill of the installer.

Claims (4)

A base rail having a first fastening hole formed between the plurality of first insertion pins and the first insertion pins formed at predetermined intervals on one surface thereof; The first insertion hole is formed to correspond to the first insertion pin of the base rail, and the semiconductor chip package can pass through the lower fastening portion and the lower fastening portion formed with a second fastening hole corresponding to the first fastening hole. A lower rail having a lower rail portion capable of being opened; Fastening means for fastening the lower rail to one surface of the base rail in a state in which the first fastening hole and the second fastening hole are aligned; And A cover rail fastened at predetermined intervals so as to correspond to a surface of the upper fastening portion fastened to the lower fastening portion and an upper rail portion through which the semiconductor chip package may pass outside the upper fastening portion to face the lower rail portion; Transfer rail of the handler for semiconductor chip package testing, comprising a. According to claim 1, wherein the lower fastening portion is formed with a second insertion pin at a predetermined interval on the outside of the first insertion hole, the second fastening portion is inserted into the second insertion hole is inserted into the second insertion pin Transfer rail of the handler for semiconductor chip package testing, characterized in that formed. 3. The method of claim 2, wherein a third fastening hole is formed between the second fastening hole and the first insertion hole in the lower fastening part, and a fourth fastening hole is formed in the upper fastening part to correspond to the third fastening hole. And the cover rail is fastened to the lower rail by a fastening means in a state where the third fastening hole and the fourth fastening hole are aligned with each other. The transfer rail of claim 1, wherein the fastening means is a fastening screw.