KR19980077382A - System Clock Generator of Electronic Switching System - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

System Clock Generator of Electronic Switching System

2. The technical problem to be solved by the invention

The system clock generator that is applied to the conventional all-electronic exchange consists of three circuit packs: control circuit pack, phase difference measurement circuit pack, and clock generation circuit pack. It is intended to solve the problem of irrationality in the case of 3 and a pack of three circuit packs on the board, which makes it impossible to compact because it occupies a large volume in size.

3. Summary of Solution to Invention

Select one of the phase difference comparison reference clocks (PERF) generated from the received reference clock and the internal reference clocks obtained from the second and third system clock generators 500, and compare the phase difference between the selected clock and the internal oscillation clock. A phase difference detecting unit 200 for detecting; A controller 100 for processing the phase difference detected by the phase difference detector 200 and controlling the overall operation of the system clock generator; An interprocessor communication matching unit 400 which provides an interprocessor communication path of the triplexed system clock generator under the control of the controller 100; A system clock generator 300 for generating a system clock synchronized with the received reference clock according to the phase difference processing value obtained by the controller 100; Distributing the system clock generated by the system clock generator 300 to supply to each stage of the system, receiving a reference clock transmitted from the outside and providing the reference clock to the phase difference detection unit 200 as a reference clock for phase difference comparison and system It is characterized by consisting of a clock distribution unit 600.

4. Important uses of the invention

This is applied to generate a system clock for network synchronization in an electronic switch.

Description

System Clock Generator of Electronic Switching System

In general, the system clock generator of the conventional TDX-10 all-electronic exchange consists of three circuit packs, such as a control circuit pack, a phase difference measurement circuit pack, and a clock generation circuit pack, of which the control circuit pack reads the measured phase difference. Phase Locked Loop (Phase Locked Loop) is performed, and for this purpose, a CPU, memory, a USART for RS-232c communication, and a TD-bus matching circuit for communicating with an upper processor are provided. In addition, the central processing unit reads the phase difference from the phase difference measurement circuit pack, processes the value, and communicates with the upper processor through the TD-bus matching circuit.

Next, the phase difference measurement circuit pack provides a function for measuring the phase difference between the reference clock for phase difference comparison and the system clock received from the system clock generation circuit pack, and provides a communication path between the tripled system clock generation blocks. Measurement circuits PD1 and PD2, memory for storing phase difference measurement values, and memory for communication with the triplexed system clock generation block.

The clock generation circuit pack receives a phase difference processing value from a control circuit pack and generates a clock having a corresponding frequency. The clock generation circuit pack converts a digital phase difference processing value into an analog voltage value and an analog voltage. A voltage controlled oscillator for generating a system clock of a corresponding frequency, a visualization circuit for visualizing a digital phase difference processing value, an output control circuit for controlling the output of the system clock, and a matching circuit with a control circuit pack.

Therefore, the conventional system clock generator as described above is composed of three circuit packs: control circuit pack, phase difference measurement circuit pack, and clock generation circuit pack. It is unreasonable, and furthermore, when three circuit packs are mounted on one board, it occupies a large volume in terms of size, which makes it impossible to compact.

Therefore, the present invention is proposed to solve the general problems occurring in the system clock generator of the conventional all-electronic switchboard as described above;

An object of the present invention is to integrate a control circuit pack, a phase difference measurement circuit pack, a clock generation circuit pack into one system clock generation circuit pack, and compare a phase clock from a reference clock reception and system clock distribution circuit pack (PERF: Phase locked). It is to provide a system clock generator of an electronic switch that receives a loop external reference frequency) and generates a clock synchronized with this clock.

Technical means for achieving this object are;

A phase difference detector which selects one of a phase difference comparison reference clock generated from the received reference clock and an internal reference clock obtained from another system clock generator and detects a phase difference between the selected clock and the internal oscillation clock;

A controller which processes the phase difference detected by the phase difference detector and controls the overall operation of the system clock generator;

An inter-processor communication matching unit providing an inter-processor communication path of the triplexed system clock generator under the control of the controller;

A system clock generator which generates a system clock synchronized with the received reference clock according to the phase difference processing value obtained by the controller;

The system clock generator generates a reference clock and a system clock distribution unit for distributing a system clock and supplying the system clock to each stage, receiving a reference clock transmitted from the outside, and providing the phase difference detection unit as a reference clock for phase difference comparison.

Hereinafter, the operation and effects on the preferred embodiment of the present invention will be described.

1 is a block diagram of a system clock generator of an electronic switching system according to the present invention;

2 is a detailed block diagram of the control unit of FIG. 1;

3 is a detailed block diagram of a phase difference detector of FIG. 1;

4 is a detailed block diagram of a system clock generator of FIG. 1;

5 is a detailed block diagram of the inter-processor communication matching unit of FIG. 1;

* Description of the symbols for the main parts of the drawings *

100: control unit 200: phase difference detection unit

300: system clock generator 400: communication matching unit between processors

500: second and third system clock generator

600: reference clock receiving and system clock distribution unit

1 is a block diagram of a system clock generator of an all-electronic exchange according to the present invention.

As shown therein, one of the phase difference comparison reference clock (PERF) generated from the received reference clock and the internal reference clocks obtained from the second and third system clock generators 500 are selected, and the selected clock and the internal clock are selected. A phase difference detector 200 which detects a phase difference from the oscillation clock; A controller 100 for processing the phase difference detected by the phase difference detector 200 and controlling the overall operation of the system clock generator; An interprocessor communication matching unit 400 which provides an interprocessor communication path of the triplexed system clock generator under the control of the controller 100; A system clock generator 300 generating a system clock synchronized with the received reference clock according to the phase difference processing value obtained from the controller 100; Reference clock reception and system for distributing the system clock generated by the system clock generator 300 to supply to each stage of the system and receiving a reference clock transmitted from the outside and providing the phase difference detection unit 200 as a reference clock for phase difference comparison. The clock divider 600 is configured.

As shown in FIG. 2, the control unit 100 transmits a microphase difference between the reference clock reception and the triplexed system clock obtained from the system clock distribution unit 600 to the microprocessor 110 and the microprocessor 110. Reference clock reception and system clock distribution circuit matching unit 140 for transmitting the system clock distribution control signal outputted from the reference clock reception and system clock distribution unit 600 to the reference clock reception and system clock distribution circuit. Periodically read the fine phase difference between the triplexed system clock obtained from the unit 140 and the phase difference detected by the phase difference detection unit 200 and processes the phase difference read in accordance with the program stored in the memory 120 and according to the result The microprocessor 110 that controls the clock generation and the higher level program of the exchange under the control of the microprocessor 110. An upper processor matching unit 130 for matching a TD-bus, which is a communication channel between the processor and the device, and a memory 120 in which a program used by the microprocessor 110 is stored.

In addition, as shown in FIG. 3, the phase difference detector 200 includes a phase difference comparison clock PERF obtained by the reference clock receiver and the system clock distributor 600, and the second and third system clock generators 500. A phase difference comparison clock selector 210 that selects one of the reference clocks (PIRF) obtained in FIG. 2, a clock selected by the phase difference comparison clock selector 210, and a system clock generated by the system clock generator 300. The phase difference between the first phase difference detector 220 which detects the phase difference, the reference clock for phase difference comparison generated by the reference clock reception and system clock distribution unit 600 and the system clock generated by the system clock generator 300 The second phase detector 240 detects and transfers the detected phase difference to the controller 100, and the common memory 230 stores the phase difference detected by the first phase difference detector 220.

In addition, as illustrated in FIG. 4, the system clock generator 300 includes a latch and buffer unit 310 for latching and buffering a system clock generation control value obtained from the controller 100, and the latch and buffer unit. An oscillation is generated according to the digital / analog converter 320 that converts the digital system clock generation control value buffered at 310 into an analog value corresponding thereto, and the analog system clock control value converted by the digital / analog converter 320. The high resolution oscillator 340 for generating a system clock and the system clock generated by the high accuracy oscillator 340 are divided and provided to the phase difference detection unit 200, and an internal reference clock (PIRF) is used as the system clock. The generated clock division and internal reference clock generator 330 and an output clock controller 3 for controlling the output of the high precision oscillator 340 according to the control of the controller 100. 50).

As shown in FIG. 5, the inter-processor communication matching unit 400 may include a first buffer 410 for buffering a system clock obtained from the second and third system clock generators, and the second and third buffers. To first-in, first-out of the second buffer 450 buffering the system clock transmitted to the third system clock generator and the system clock buffered by the first buffer 410, or to determine whether there is an abnormality in the controller 100. First and second first-in first-out memory 430 and 440 for first-in first-out of the transmitted data, and the data obtained from the first and second first-in first-out memory 430 and 440 are buffered to the controller 100. The third buffer 460 is provided, and the self-diagnostic unit 420 inspects whether there is a path error between the controller 100 and the first and second first-in first-out memory 430 and 440.

The operation of the system clock generator of the electronic switching system according to the present invention configured as described above will be described in detail with reference to FIGS. 1 to 5 as follows.

First, in order to generate a system clock used in the system, the reference clock reception and system clock distribution unit 600 receives a reference clock provided from the outside and performs phase difference as a phase locked loop external reference frequency (PERF). It is provided to the detection unit 200. At this time, since the present invention has been described as a triple system, the phase difference detection unit 200 also inputs another two system clocks (PIRF: Phase locked loop Internal Reference Frequency) generated from the generator 500. At the same time, a clock (16.384 MHz) bi-divided from the system clock (32.768 MHz) previously generated by the system clock generator 300 is also input. Accordingly, as shown in FIG. 3, the phase difference detecting unit 200 is configured to perform the phase difference comparison reference clock (PERF; 4 ms) in the phase difference comparison clock selection unit 210. You will choose one. That is, since all three system clock generators of the network device are operated in a master-slave manner, the master system clock generator (device according to the present invention; Fig. 1) is for comparing the phase difference described above. The clock selector 210 selects the reference clock for receiving the reference clock and the phase difference comparison reference clock (PERF) generated by the system clock distributor 600, and the slave system clock generator is provided by two other system clock generators. The reference clock for phase difference comparison of the master system clock generator is selected from the two internal reference clocks (PIRF). When the clock is selected in this way, the first phase difference detector 220 periodically detects the phase difference between the selected clock and the bisected clock (16.384 MHz) obtained by the system clock generator 300 every 250 μs, thereby detecting the common memory 230. Will be saved). In addition, the second phase difference detector 240 includes a phase difference comparison reference clock (PERF) of 4 kHz obtained by the reference clock reception and system clock distribution unit 600 and a division clock (16.384 MHz) obtained by the system clock generator 300. The phase difference is periodically detected every 1.024 sec and transmitted to the control unit 100. In addition, the common memory 230 stores a phase difference value detected by the first phase difference detector 220, and the controller 100 reads the phase difference value every time 512 stored phase difference values are stored.

On the other hand, when the phase difference value is detected as described above, the control unit 100 controls the generation of the system clock according to the phase difference value, that is, as shown in Figure 2, the microprocessor 110 in the control unit 100 The phase difference detected by the phase difference detection unit 200 is read out and processed by a program stored in the memory 120. The result of the processing is provided to the system clock generator 300 to generate a system clock. In addition, the control unit 100 communicates with the upper processor through the upper processor matching unit 130, and the fine phase difference between the system clocks of the system clock generator tripled through the reference clock receiving and system clock distribution circuit matching unit 140. Read Also, the upper processor matching unit 130 converts serial data transmitted from the upper processor into parallel data and parallel data in order to match with a TD-bus (Telephone Device-BUS), which is a communication channel between the upper processor of the switch and the device. Is converted into serial data and sent to a higher processor, and a common memory is used for easy communication with the higher processor. The reference clock reception and system clock distribution circuit matching unit 140 includes an address resolver and a buffer to provide a connection path between the reference clock reception and system clock distribution unit 600 and the microprocessor 110.

As described above, when the system clock generation control signal corresponding to the phase difference value read from the controller 110 is calculated, the system clock generation unit 300 generates the system clock based on this. In other words, as shown in FIG. 4, the system clock generator 300 latches and buffers the 16-bit digital system clock generation control signal value obtained from the controller 100 in the buffer unit 310 to convert the digital / analog converter 320. The digital-to-analog converter 320 converts the applied 16-bit digital value into an analog voltage and inputs it to the high precision oscillator 340. Then, the oscillator 340 oscillates according to the input voltage to generate a system clock of 32.768 MHz and simultaneously provide the reference clock reception and system clock distribution unit 600 and the clock division and internal reference clock generator 330 simultaneously. Do it. Accordingly, the clock divider and the internal reference clock generator 330 divide the provided system clock into two parts, transfer a clock of 16.384 MHz to the phase difference detector 300, generate a 4 kHz clock, and generate two other system clocks. It feeds back to the generator 500. And the output clock control unit 350 is composed of a buffer and an address interpreter to control the output of the system clock generated by the high precision oscillator 340 under the control of the control unit 100.

Next, the inter-processor communication matching unit 400 facilitates communication between the triplexed system clock generators, and as shown in FIG. 5, the self-diagnostic unit 420 includes the control unit 100 and the first and A function of detecting a path abnormality between the first-in, first-out memory 430 and 440 is performed, and the controller 100 transmits arbitrary data to the first buffer through the third buffer 460 and the self-diagnosis unit 420. And after reading the values in the second first-in first-out memory 430 and 440, the values are read again through the third buffer 460 to compare the values and determine whether there is an abnormality. In this case, the first and second buffers 410 and 450 are disabled, and when writing data to the counter system clock generator, the first and second first-in, first-out memory 430 receives the data through the first buffer 410. In operation 440, the recorded data is read through the third buffer 460. At this time, the self-diagnosis unit 420 and the second buffer 450 are disabled. When the controller 100 writes data to the counterpart system clock generator, data is written to the first and second first-in first-out memory 430 and 440 through the second and third buffers 450 and 460. .

As described in detail above, the present invention simplifies the configuration of the device by integrating a control circuit pack, a phase difference measurement circuit pack, and a clock generation circuit pack for generating a system clock into one system clock generation circuit pack. The compactness of the effect is possible.

In addition, the present invention receives the phase difference comparison reference clock generated from the reference clock received from the outside in the electronic device of the electronic switchboard, and generates a system clock synchronized with this clock to maintain the synchronization of each device as well as stable It is possible to provide a system clock.

In addition, the present invention can precisely maintain synchronization with other exchangers, so that it is possible to secure high reliability and stability.

The present invention relates to the generation of the system clock of the electronic switch, in particular the control circuit pack, the phase difference measurement circuit pack, the clock generation circuit pack constituting the existing system clock generator is integrated into one system clock generation circuit pack, the reference clock The present invention relates to a system clock generator of an electronic switching system which receives a phase locked loop external reference frequency (PERF) from a receiving and system clock distribution circuit pack and generates a clock synchronized with the clock.

Claims (5)

An apparatus for generating a system clock for network synchronization of an electronic switching system, Select one of the phase difference comparison reference clocks (PERF) generated from the received reference clock and the internal reference clocks obtained from the second and third system clock generators 500, and compare the phase difference between the selected clock and the internal oscillation clock. A phase difference detecting unit 200 for detecting; A controller 100 for processing the phase difference detected by the phase difference detector 200 and controlling the overall operation of the system clock generator; An interprocessor communication matching unit 400 which provides an interprocessor communication path of the triplexed system clock generator under the control of the controller 100; A system clock generator 300 for generating a system clock synchronized with the received reference clock according to the phase difference processing value obtained by the controller 100; Distributing the system clock generated by the system clock generator 300 to supply to each stage of the system, receiving a reference clock transmitted from the outside and providing the reference clock to the phase difference detection unit 200 as a reference clock for phase difference comparison and system System clock generator of the electronic switchboard, characterized in that configured to include a clock distribution unit (600). The method of claim 1, wherein the control unit 100 transmits the microphase difference between the reference clock reception and the triplexed system clock obtained from the system clock distribution unit 600 to the microprocessor 110 and outputs from the microprocessor 110. A reference clock reception and system clock distribution circuit matching unit 140 for transmitting a system clock distribution control signal to the reference clock reception and system clock distribution unit 600, and the reference clock reception and system clock distribution circuit matching unit 140. After reading the fine phase difference between the tripled system clock and the phase difference detected by the phase difference detecting unit 200 periodically and processing the phase difference read according to the program stored in the memory 120, the system clock generation according to the result The microprocessor 110 for controlling and the higher processor of the exchange under the control of the microprocessor 110. System clock of the electronic switchboard, characterized in that the upper processor matching unit 130 for matching the TD-bus communication channel between the device and the memory 120, the program used in the microprocessor 110 is stored Generator. The phase difference detecting unit 200 is a phase difference comparison clock PERF obtained by the reference clock receiving and system clock distribution unit 600 and a reference clock PIRF obtained by the other system clock generator 500. The first phase difference detecting phase difference between the clock selector 210 for selecting one and the clock selected by the phase difference comparison clock selector 210 and the system clock generated by the system clock generator 300. The controller 220 detects a phase difference between the reference clock for phase difference comparison generated by the reference clock reception and system clock distribution unit 600 and the system clock generated by the system clock generator 300 to detect the phase difference. The second phase difference detector 240 and a common memory 230 for storing the phase difference detected by the first phase difference detector 220 is transferred to the electronic switch exchange, characterized in that System clock generator. The method of claim 1, wherein the system clock generator 300 includes a latch and buffer unit 310 for latching and buffering a system clock generation control value obtained from the controller 100, and buffering in the latch and buffer unit 310. A system clock is generated by oscillating according to a digital / analog converter 320 that converts the digital system clock generation control value into an analog value corresponding to the digital system clock generation control value, and the analog system clock control value converted by the digital / analog converter 320. A clock division for dividing the system clock generated by the high precision oscillator 340 and the high accuracy oscillator 340 to the phase difference detection unit 200 and generating an internal reference clock (PIRF) using the system clock. Internal reference clock generator 330, and the output clock control unit 350 for controlling the output of the high precision oscillator 340 under the control of the control unit 100 A system clock generator of the electronic switch, characterized in that before. The method of claim 1, wherein the inter-processor communication matching unit 400 is delivered to the first buffer 410 for buffering the system clock obtained from the other system clock generator, and the second and third system clock generator A first buffer that buffers a system clock, and a first that first-in-first-outs the data transmitted to determine whether there is an abnormality or a first-in-first-out of the system clock buffered in the first buffer 410. And a third buffer 460 for buffering and transferring data obtained from the first and second first-in first-out memory 430 and 440 and the first and second first-in first-out memory 430 and 440 to the controller 100. And a self-diagnostic unit 420 for checking a path abnormality between the control unit 100 and the first and second first-in first-out memory 430 and 440. .