CN115314143A - Multi-module computing platform clock synchronization system, method, electronic device and medium - Google Patents
Multi-module computing platform clock synchronization system, method, electronic device and medium Download PDFInfo
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Abstract
The embodiment of the application provides a clock synchronization system, a clock synchronization method, electronic equipment and a medium for a multi-module computing platform, wherein the system comprises: the clock subsystem is respectively connected with the main node and each slave node through a working clock signal connecting line; the main node is respectively connected with each slave node through PPS signal connecting wires; the main node is used for operating a 1588 protocol stack to analyze the pulse per second to obtain GPS time and a PPS signal; the clock subsystem is used for respectively providing required working clocks for the main node and each slave node; and each node in the master node and each slave node is used for calibrating the accumulated error of the corresponding counter according to the PPS signal. Therefore, the slave nodes in the system do not need to support the 1588 protocol, the master node and the slave node use the same clock subsystem, and the master node and the slave node calibrate the clock counters of the master node and the slave node according to the PPS signal, so that the clock synchronization accuracy of a multi-module computing platform is improved, the engineering realization difficulty is reduced, and the development and verification cost is effectively reduced.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a clock synchronization system and method for a multi-module computing platform, electronic equipment and a medium.
Background
Due to the requirements of computing power and functional safety, a computing platform in the vehicle-mounted and industrial fields integrates a plurality of computing power chips (SOC) and a vehicle-scale MCU (micro controller Unit). Moreover, due to the requirements of computing real-time and certainty, these computing units are clocked with external sensors, including V2X sensors. At present, different computing units in a computing platform realize clock synchronization, and a common method is realized based on a 1588V2 protocol. The clock synchronization protocol 1588V2 mainly solves the clock synchronization of different computing and switching nodes in the Ethernet. The operating system is required to contain corresponding protocols, the chip physical layer can realize the corresponding protocols, the time synchronization protocol 1588V2 relates to a large number of content items, and a large amount of labor cost and long time consumption are required for perfectly realizing clock synchronization.
Disclosure of Invention
In order to solve the foregoing technical problem, embodiments of the present invention provide a system, a method, an electronic device, and a medium for clock synchronization of multiple computing platforms.
In a first aspect, an embodiment of the present invention provides a method for synchronizing clocks of multiple computing platforms, including: the multi-module computing platform clock synchronization system comprises:
the system comprises a main node, a clock subsystem and a plurality of slave nodes, wherein the main node and each slave node respectively comprise a counter;
the clock subsystem is respectively connected with the main node and each slave node through a working clock signal connecting line;
the master node is respectively connected with each slave node through a PPS signal connecting line;
the master node is used for operating a 1588 protocol stack to analyze the pulse per second to obtain GPS time and a PPS signal;
the clock subsystem is used for respectively providing required working clocks for the main node and the slave nodes;
and the master node and each node in each slave node are used for calibrating the accumulated error of the corresponding counter according to the PPS signal.
According to a specific embodiment of the present disclosure, the clock subsystem is composed of a reference clock source and a clock buffer, the reference clock source is electrically connected to the clock buffer, or the clock subsystem is composed of a reference clock source and a phase-locked loop, the reference clock source is electrically connected to the phase-locked loop;
the clock buffer or the phase-locked loop comprises a plurality of channels, and each channel is electrically connected with the main node and each slave node respectively.
According to a specific embodiment of the present disclosure, each node of the master node and each slave node is configured to obtain a clock frequency and a frequency division ratio of a corresponding channel, and calibrate an accumulated error of a corresponding counter according to the clock frequency, the frequency division ratio, and the PPS signal.
According to a specific embodiment of the present disclosure, each of the master node and the slave nodes is configured to calibrate an accumulated error of the corresponding counter once per second according to the PPS signal.
According to a specific embodiment of the present disclosure, each slave node includes a real-time processor, and a corresponding counter is set on the real-time processor.
According to a specific embodiment of the present disclosure, the master node is further configured to receive the pulse of seconds from a GPS.
In a second aspect, an embodiment of the present invention provides a multi-mode group computing platform clock synchronization method, which is applied to the multi-mode group computing platform clock synchronization system provided in the first aspect, and the method includes:
analyzing the pulse per second by operating a 1588 protocol stack by the main node to obtain GPS time and a PPS signal;
respectively providing required working clocks for the main node and each slave node through a clock subsystem;
and calibrating the accumulated error of the corresponding counter according to the PPS signal through each node in the main node and each slave node.
According to a specific embodiment of the present disclosure, the calibrating, by each node of the master node and each slave node, an accumulated error of a corresponding counter according to the PPS signal includes:
and acquiring the clock frequency and the frequency division ratio of the corresponding channel through each node in the master node and each slave node, and calibrating the accumulated error of the corresponding counter according to the clock frequency, the frequency division ratio and the PPS signal.
In a third aspect, an embodiment of the present invention provides an electronic device, which includes a memory and a processor, where the memory is used to store a computer program, and when the processor runs, the computer program performs the multi-mode group computing platform clock synchronization method provided in the second aspect.
In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium storing a computer program, which, when running on a processor, executes the multi-mode group computing platform clock synchronization method provided in the second aspect.
According to the clock synchronization system, the clock synchronization method, the electronic device and the medium of the multi-mode group computing platform, slave nodes in the multi-mode group computing platform synchronization system do not need to support a 1588 protocol, the master node and the slave nodes use the same clock subsystem, and the master node and the slave nodes calibrate clock counters of the master node and the slave nodes according to PPS signals, so that the clock synchronization accuracy of the multi-mode group computing platform is improved, the engineering implementation difficulty is reduced, and the development and verification cost is effectively reduced.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings required in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention. Like components are numbered similarly in the various figures.
Fig. 1 shows an architecture diagram of a clock synchronization system based on 1588V2 protocol in the prior art;
FIG. 2 is a schematic diagram illustrating an architecture of a multi-mode group computing platform clock synchronization system according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating another exemplary architecture of a multi-mode group computing platform clock synchronization system according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram illustrating another exemplary architecture of a multi-mode group computing platform clock synchronization system according to an embodiment of the present disclosure;
fig. 5 is a flowchart illustrating a clock synchronization method for a multi-mode group computing platform according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present invention, are only intended to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
Referring to fig. 1, the basic principle of implementing synchronization based on 1588V2 protocol is as follows: one of the computing modules (typically a vehicle-mounted MCU) receives recommended positioning information (GPRMC) and Pulse Per Second (PPS) signals from the GPS. The GPRMC message is internally provided with UTC time information which can be used as standard time. The Universal Time Coordinated (UTC) is also called Universal Time, universal Time standard, and international Coordinated Time. The vehicle-mounted controller MCU becomes a clock global master node of the whole computing platform, and other computing modules SOC are clock slave nodes. In fig. 1, the other calculation modules SOC include SOC1, SOC12, and SOCn, each having a counter 1, a counter 2, and a. The other computing modules SOC receive PPS signals and Precise Time Protocol (gPTP) signals transmitted by the vehicle regulation MCU through Ethernet (ETH) channels.
The slave node (SOC) and the master node (MCU) implement the time synchronization of CLK _ MCU, CLK _1, CLK _2, and CLK _ n through 1588V2 protocol (802.1 AS), and the counter statistics of all the master and slave nodes are consistent in nature. The clock synchronization of the whole computing platform computing module is realized, and the following 4 problems are solved: the master node of the whole clock domain confirms that the clock frequencies of all the master nodes and the slave nodes are different, the link delay between the master nodes and the slave nodes is long, and the residence time of the data message on each node is short.
It should be noted that the clock synchronization protocol 1588v2 mainly solves clock synchronization of different computation and switching nodes in an ethernet network. In a complex Ethernet, the number of nodes is large, the clock frequency precision of different nodes cannot be planned in advance, the delay on a link is different, the delay is also dynamically changed, and the residence time of data on each node cannot be predicted and planned. To implement 1588V2 time synchronization, an operating system is required to include a corresponding protocol, and a chip physical layer is required to implement the corresponding protocol. The time synchronization agreement 1588V2 involves a large number of content terms requiring engineer experience and considerable investment costs to be perfectly achieved.
Example 1
The embodiment provides a multi-mode group computing platform clock synchronization system.
Referring to FIG. 2, a multi-mode computing platform clock synchronization system 100 includes: a master node 20, a clock subsystem 10 and a plurality of slave nodes. In fig. 1, a plurality of slave nodes are denoted as slave node 1, slave node 2,.. And slave node n, respectively. The master node 20 includes a counter _ m, and the slave nodes 1 and 2 and n include a counter _1, a counter _2 and n, respectively. The clock subsystem 10 is connected to the master node 20, the slave node 1, the slave node 2, and the slave node n, respectively, by operating clock signal lines. The master node 20 is connected to the slave node 1, the slave node 2, and the slave node n through PPS signal lines.
The master node 20 is configured to operate a 1588 protocol stack to analyze the pulse per second, so as to obtain GPS time and a PPS signal; the clock subsystem 10 is configured to provide required working clocks to the master node 20, the slave node 1, the slave node 2, ·.. And the slave node n, respectively; each of the master node 20, the slave node 1, the slave node 2, the slave node n is configured to calibrate an accumulated error of a corresponding counter according to the PPS signal.
In the present embodiment, the master node 20 is configured to receive a second pulse from a Global Positioning System (GPS), wherein the second pulse includes recommended Positioning information (GPRMC) and a PPS signal. The GPRMC message is internally provided with UTC time information which can be used as standard time. It should be noted that the master node 20 supports a 1588 protocol resolution function, and the slave node 1, the slave node 2, and the slave node n do not require the 1588 protocol resolution function.
In this embodiment, to improve the accuracy of calibration, each of the master node 20, the slave node 1, the slave node 2, and the slave node n is configured to calibrate the accumulated error of the corresponding counter once per second according to the PPS signal.
Referring to fig. 3, fig. 3 is different from fig. 2 in that a specific structure example of the clock subsystem 10 is shown. In fig. 3, the clock subsystem 10 is composed of a reference clock source 101 and a clock buffer 102, where the reference clock source 101 is electrically connected to the clock buffer 102, or the clock subsystem 10 is composed of a reference clock source 101 and a phase-locked loop (not shown in fig. 3), where the reference clock source 101 is electrically connected to the phase-locked loop;
the clock buffer 102 or the phase locked loop includes a plurality of channels, each of which is electrically connected to a respective one of the master node 20, the slave node 1, the slave node 2, the slave node n.
When the clock subsystem 10 is composed of the reference clock source 101 and the clock buffer 102, the clock buffer 102 provides the same operating clock frequency to each of the master node 20, the slave node 1, the slave node 2, and the slave node n through each channel. When the clock subsystem 10 is composed of the reference clock source 101 and the phase locked loop, the phase locked loop provides the required operating clock to each of the master node 20, the slave node 1, the slave node 2, the slave node n through each channel. The frequencies of the operating clocks required by the master node and the slave nodes may be the same or different, and need to be determined according to the system requirements of the master node and the slave nodes.
Note that each of the slave node 1, the slave node 2, and the slave node n includes an R5 processor, and a corresponding counter is provided on the real-time processor.
In this embodiment, the real-time processor may be an R5 processor, or may be another type of processor, which is not limited herein.
In this embodiment, each of the master node 20, the slave node 1, the slave node 2, ·.. And the slave node n is configured to obtain a clock frequency and a frequency division ratio of a corresponding channel, and calibrate an accumulated error of a corresponding counter according to the clock frequency, the frequency division ratio and the PPS signal.
In this embodiment, the clock buffer provides the master node and all the slave nodes with the same operating clock frequency, so the counter statistics of the master node and the slave nodes are completely the same. The reference clock source 101 of the clock subsystem 10 may be a crystal or a crystal oscillator. It should be noted that, even if a phase-locked loop is required to generate operating clocks with different frequencies, the frequency division ratio may be directly input to the counter for conversion.
Since the master node and the slave nodes of the multi-mode group computing platform clock synchronization system 100 share the same reference clock source and the same clock buffer (or phase-locked loop) chip, the frequencies and the accuracies of the working clocks received by the master node and all the slave nodes are consistent, and the counting error of the master node and the slave node is extremely small at least in a short time.
The master node and all slave nodes use the PPS signal to calibrate the accumulated error of the counter once per second, and the standard value corresponding to the PPS signal can be calculated in advance. The calculation mode is that the accumulated numerical value of the PPS is determined according to the working clock comment, namely the statistical value of the counter is determined according to the working clock comment. For example, an operating clock frequency of 25MHz, the accumulated value for each PPS would be 25000000.
A specific application scenario of the multi-mode computing platform clock synchronization system is illustrated in fig. 4. In fig. 4, the vehicle-mounted computing platform 400 is composed of a vehicle-scale MCU and 4 computational power chips (System on Chip, SOC), and each computational power Chip includes an R5 real-time processor therein. In fig. 4, 4 computation force chips are SOC1, SOC2, SOC3, and SOC4, respectively. The working principle of the vehicle-mounted computing platform 400 is as follows: the vehicle-scale MCU serving as a master node can analyze a 1588 protocol and receive pulse per second from a GPS, and the SOC1, the SOC2, the SOC3 and the SOC4 serving as slave nodes do not require a 1588 protocol analysis function. The master node and the slave node are provided with calculators, and counters of 4 slave nodes are distributed on an R5 processor. The vehicle gauge grade MCU has a counter _ MCU, SOC1 has a counter _1, SOC2 has a counter _2, SOC3 has a counter _3, and SOC4 has a counter _4. On a vehicle-mounted computing platform, each node is on the same PCB single board, the number of the nodes is small, the clock frequency and the precision of different nodes can be planned in advance, the delay on a link is ns level and determined, and the data residence time on each node can be accurately counted by using an R5 processor on an SOC.
The crystal Oscillator (Oscillator) and the phase-locked loop (Clk _ PLL) form a clock subsystem of the whole platform and provide working clocks for the master node and the slave node. The clock frequency output by each channel of the phase-locked loop and the frequency division ratio of each channel are confirmed by a corresponding force calculation chip. For example, in fig. 4, the clock frequencies required by the 4 computation chips SOC1, SOC2, SOC3, and SOC4 may be different, so that the frequency division ratio of each channel is different, and SOC1, SOC2, SOC3, and SOC4 need to know the frequency division ratio of the corresponding channel, so as to correct the counter. The master and slave nodes calibrate the counter values once per second using the received PPS signal.
According to the clock synchronization system of the multi-mode group computing platform, the slave nodes in the synchronization system of the multi-mode group computing platform do not need to support 1588 protocols, the master node and the slave nodes use the same clock subsystem, and the master node and the slave nodes calibrate the clock counters of the master node and the slave nodes according to PPS signals, so that the clock synchronization accuracy of the multi-mode group computing platform is improved, the engineering implementation difficulty is reduced, and the development and verification cost is effectively reduced.
Example 2
The embodiment provides a multi-module computing platform clock synchronization method which is applied to the multi-module computing platform clock synchronization system provided by the embodiment.
Referring to fig. 5, the method for synchronizing clocks of multiple computing platforms includes:
step S501, the second pulse is analyzed by the operation of a 1588 protocol stack of the main node, and GPS time and a PPS signal are obtained;
step S502, respectively providing required working clocks for the main node and each slave node through a clock subsystem;
step S503, calibrating, by each node of the master node and each slave node, an accumulated error of a corresponding counter according to the PPS signal.
In one embodiment, step S503 includes:
and acquiring the clock frequency and the frequency division ratio of the corresponding channel through each node in the master node and each slave node, and calibrating the accumulated error of the corresponding counter according to the clock frequency, the frequency division ratio and the PPS signal.
The clock synchronization method for a multi-mode group computing platform provided in this embodiment is applied to the clock synchronization system for a multi-mode group computing platform provided in this embodiment, and has functions corresponding to the clock synchronization system for a multi-mode group computing platform, and is not described herein again to avoid repetition.
Example 3
Furthermore, an embodiment of the present disclosure provides an electronic device, including a memory and a processor, where the memory stores a computer program, and the computer program executes the multi-mode group computing platform clock synchronization method provided in embodiment 2 when running on the processor.
The electronic device provided in this embodiment may implement the method for synchronizing clocks of multiple computing platforms provided in embodiment 2, and is not described herein again to avoid repetition.
Example 4
The present application further provides a computer-readable storage medium having stored thereon a computer program that, when executed by a processor, implements the multi-mode group computing platform clock synchronization method provided in embodiment 2.
In this embodiment, the computer-readable storage medium may be a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk.
The computer-readable storage medium provided in this embodiment may implement the multi-mode group computing platform clock synchronization method provided in embodiment 1, and is not described herein again to avoid repetition.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or terminal that comprises the element.
Through the description of the foregoing embodiments, it is clear to those skilled in the art that the method of the foregoing embodiments may be implemented by software plus a necessary general hardware platform, and certainly may also be implemented by hardware, but in many cases, the former is a better implementation. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present application.
While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the present embodiments are not limited to those precise embodiments, which are intended to be illustrative rather than restrictive, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope of the appended claims.
Claims (10)
1. A multi-module computing platform clock synchronization system, the multi-module computing platform clock synchronization system comprising:
the system comprises a main node, a clock subsystem and a plurality of slave nodes, wherein the main node and each slave node respectively comprise a counter;
the clock subsystem is respectively connected with the main node and each slave node through a working clock signal connecting line;
the master node is respectively connected with each slave node through a PPS signal connecting line;
the master node is used for operating a 1588 protocol stack to analyze the pulse per second to obtain GPS time and a PPS signal;
the clock subsystem is used for respectively providing required working clocks for the main node and the slave nodes;
and the master node and each node in each slave node are used for calibrating the accumulated error of the corresponding counter according to the PPS signal.
2. The multi-module computing platform clock synchronization system of claim 1, wherein the clock subsystem is composed of a reference clock source and a clock buffer, the reference clock source is electrically connected to the clock buffer, or the clock subsystem is composed of a reference clock source and a phase-locked loop, the reference clock source is electrically connected to the phase-locked loop;
the clock buffer or the phase-locked loop comprises a plurality of channels, and each channel is electrically connected with the main node and each slave node respectively.
3. The multi-mode group computing platform clock synchronization system of claim 2, wherein each of the master node and each of the slave nodes is configured to obtain a clock frequency and a divide ratio for a corresponding channel, and calibrate an accumulated error of a corresponding counter based on the clock frequency, the divide ratio, and the PPS signal.
4. The system for multi-mode group computing platform clock synchronization of claim 1, wherein each of the master node and the slave nodes is configured to calibrate an accumulated error of the corresponding counter once per second based on the PPS signal.
5. The multi-tuple computing platform clock synchronization system of claim 1, wherein each of said slave nodes comprises a real-time processor having a corresponding counter disposed thereon.
6. The multi-mode set computing platform clock synchronization system of claim 1, wherein the master node is further configured to receive the pulse-of-seconds from a GPS.
7. A multi-mode group computing platform clock synchronization method, applied to the multi-mode group computing platform clock synchronization system of any one of claims 1 to 6, the method comprising:
analyzing the pulse per second by operating a 1588 protocol stack by the main node to obtain GPS time and a PPS signal;
respectively providing required working clocks for the main node and each slave node through a clock subsystem;
and calibrating the accumulated error of the corresponding counter according to the PPS signal through each node in the main node and each slave node.
8. The multi-mode group computing platform clock synchronization method of claim 7, wherein said calibrating, by each of said master node and each of said slave nodes, an accumulated error of a corresponding counter based on said PPS signal comprises:
and acquiring the clock frequency and the frequency division ratio of the corresponding channel through each node in the master node and each slave node, and calibrating the accumulated error of the corresponding counter according to the clock frequency, the frequency division ratio and the PPS signal.
9. An electronic device comprising a memory and a processor, the memory for storing a computer program that, when executed by the processor, performs the multi-mode group computing platform clock synchronization method of claim 7 or 8.
10. A computer-readable storage medium storing a computer program which, when run on a processor, performs the multi-mode group computing platform clock synchronization method of claim 7 or 8.
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