JPH1146184A - Bit error measuring instrument - Google Patents

Abstract

PROBLEM TO BE SOLVED: To confirm a bit error position and an error class in an input signal at a glance and to efficiently investigate an abnormality occurrence position and an abnormal cause in an object to be measured by providing an output controlling means, etc., which outputs an input signal waveform, an error occurrence position and an error class of the input signal waveform and a calculated error ratio. SOLUTION: An output controlling part 13 comprising a CPU sends a fetch signal h of data to a storing part 12 after prescribed extension time passes since establishing synchronization between an input signal a and a reference pattern signal c when a synchronous controlling part 10 inputs a synchronizing establishment signal d after power is turned on. The part 13 reads an error rate, the input signal a, an error signal e and an error class signal f which are stored in each memory 12a to 12d of the part 12 when an operating part 14 such as a keyboard inputs a display instruction and outputs and displays them on a display screen of a displaying part 15 consisting of, e.g. a CRT display in a prescribed format.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit error measuring device for measuring a bit error contained in a digital signal, and more particularly to a bit error measuring device capable of simultaneously detecting an error type.

[0002]

2. Description of the Related Art In digital communication networks,
In order to ensure the reliability of data transmitted through this digital communication network, bit errors in digital signals transmitted through this digital communication network at regular intervals at the time when this digital communication network is newly constructed or after operation Measurements need to be performed.

[0003] Generally, as a method of performing a bit error measurement of a digital signal, a reference pattern signal such as a pseudo random pattern (PRBS) signal is applied to a communication device or a transmission line to be measured using a reference signal generator. And
The bit pattern of the signal that has passed through the measurement target is measured to determine how much bit error is included in the bit pattern of the original reference pattern signal.

As a specific method of measuring the error rate,
The bit error rate of the input signal obtained from the measurement target and the reference pattern signal is calculated by counting the bit errors output from a bit error detection circuit including an exclusive OR circuit or the like.

[0005]

However, as described above, a bit error measuring device that detects a bit error of an input signal that has passed through an object to be measured and calculates a bit error rate is still another problem to be improved. was there.

A technician operating this bit error measurement device determines that some abnormality has occurred in the measurement object when the measured bit error rate exceeds an allowable value. Then, the cause of the abnormality occurrence of the measurement target is determined, and an appropriate countermeasure is executed.

However, since the bit error information obtained by the bit error measuring device is only the bit error rate, a great deal of time and effort is required to specify the location of the measurement target where the abnormality has occurred.

For example, in a mobile radio communication network, a digital signal transmitted / received between a mobile terminal and a base station as an input signal to be input to the bit error test apparatus may be used.

[0009] Information between the mobile terminal and the base station is transmitted and received in a fixed transmission frame. Each bit data constituting the transmission frame has its own meaning, and an electronic component or a software module for which the corresponding bit data is created can be uniquely specified.

Therefore, if bit errors concentrate on specific bit data in the transmission frame, it is highly likely that some abnormality has occurred in the electronic component or software module that creates the bit data.

The present invention has been made in view of such circumstances, and by simultaneously detecting an error type in addition to a bit error of an input signal, the bit error position and the error type in the input signal can be seen at a glance. It is an object of the present invention to provide a bit error measuring device that can be confirmed and can efficiently determine the position and the cause of the abnormality in the measurement target.

[0012]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a bit error measurement for measuring a bit error by receiving an output signal of a device under test which has received a digital signal having a bit pattern of a predetermined period. In the device, a reference pattern signal generator that outputs a reference pattern signal having the same bit pattern as the bit pattern of the digital signal,
An error detection unit that receives an output signal of the device under test, compares each bit of the output signal with each bit of the reference pattern signal output from the reference pattern signal generation unit, and outputs an error signal when there is a mismatch, An error rate calculator for calculating an error rate of an input signal based on an error signal output from the error detector, and an error type determination for determining an error type of an error detected by the error detector and outputting an error type signal Unit, a storage unit for storing at least the input signal, the error signal and the error type signal in time series, and reading out the input signal, the error signal and the error type signal stored in the storage unit, An output control unit is provided for outputting the error occurrence position and error type in the signal waveform, and the calculated error rate.

[0013] In the bit error measuring device configured as described above, a bit error in a digital input signal is detected by an error detector and output as an error signal. The type of the error is detected by the error type detector and output as an error type signal. The error signal and the error type signal are stored in the storage unit together with the input signal.

Then, it is read by the output control unit,
The input signal waveform, the error occurrence position and error type in the input signal waveform, and the calculated error rate are visually displayed on a display device or printed out on a printer.

Therefore, for example, when an error rate exceeds an allowable value, it is easy for an operator or a technician of the bit error measuring device to identify an electronic component or a software module in which an abnormality has occurred in a measurement target, and that an error has occurred. The cause of the abnormality can be efficiently investigated from the type.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a bit error measuring device according to an embodiment of the present invention.

For example, a digital pseudo-random pattern (PRBS) from the test signal generator for the measured object
A signal is applied, and the PRBS signal passes through the object to be measured and is output from an output terminal. Then, the signal output from the measured object is input to the input terminal 1 of the bit error measuring device according to the embodiment of the present invention as a digital input signal a. The input signal a input from the input terminal 1 is input to the error detector 2, the delay circuit 3, and the clock recovery circuit 4.

The clock recovery circuit 4 recovers a clock signal b having a frequency corresponding to the bit rate (transmission frequency) of the input signal a from the input signal a and sends it to the switching circuit 5.

On the other hand, the input signal a
Clock signal b ₁ which is used to create the is applied is inputted to the switching circuit 5. The switching circuit 5 selects one of the preset clock signals b and b ₁ and generates a new clock signal b ₂ as a reference pattern signal generator 7, an error detector 2, a synchronization controller 10, an error type The information is sent to the determination unit 8, the error rate calculation unit 9, the delay circuits 3 and 11, the storage unit 12, and the output control unit 13.

The reference pattern signal generator 7 outputs a reference pattern signal c having the same bit pattern as the pseudo random pattern (PRBS) signal applied to the object to be measured in synchronization with the input clock signal b _2. I do. As is well known, a reference pattern signal c composed of a PRBS signal
Is (2 ^N −
This is a periodic signal having the bit period of 1). The reference pattern signal c output from the reference pattern signal generator 7 is applied to the error detector 2.

The error detecting section 2 is constituted by, for example, an exclusive OR circuit, and synchronizes the bit value of the input signal a with the reference pattern signal in synchronization with the rising timing of the clock signal b ₂ applied to the trigger terminal. By comparing the bit value of the input signal a with the bit value of the reference pattern signal c, the high-level bit error signal e is converted to the error rate calculator 9, the delay circuit 11, and the synchronization controller. 10
Send to

The synchronization control unit 10 includes a reference pattern generation unit 7
And a synchronization determination function. That is, since the reference pattern generator 7 is started asynchronously with respect to the test signal generator that applies the pseudo random pattern (PRBS) signal to the measurement target, the reference pattern signal c Is not synchronized with the input signal a at all, and outputs the bit error signal e continuously from the error detection unit 2 for each clock.

Therefore, the synchronization control unit 10 bit-shifts the output timing of the reference pattern signal c with respect to the reference pattern generation unit 7 and detects the output timing at which the bit error rate is determined to be established. Then, the output timing is set in the reference pattern generator 7. When the synchronization control unit 10 confirms that the reference pattern signal c has been synchronized with the input signal a by the bit error signal e of the error detection unit 2, it sends a synchronization establishment signal d to the output control unit 13.

The delay circuits 3 and 11 are composed of, for example, D-type flip-flops. The error signal e and the error type signal f are stored in the storage unit 12 in synchronization with each bit of the input signal a and the reference pattern signal c. The input signal a and the bit error signal e are delayed by one bit (one clock) or two bits (two clocks) with respect to the error type signal f so as to be applied.

When the input signal a delayed by the delay circuit 3 and the bit error signal e delayed by the delay circuit 11 are input, the error type determination unit 8 designates an error in the input signal a at the input timing. An error type indicating the direction in which the detected bit is erroneous with respect to a correct bit value of the reference pattern signal c is detected, and an error type signal f is transmitted to the storage unit 12.

The types of bit errors are mainly [0]
Insertion Error where the correct bit value of [1] changes to the incorrect bit value of [1], and [1]
There are two types of errors: Omision Error, in which the correct bit value changes to an incorrect bit value of [0].

More specifically, the error type judging section 8 compares the bit error signal e delayed by the delay circuit 11 with the delay circuit 3.
When the data value of the input signal a at the timing of the clock signal b ₂ is the bit value of [1] when the input signal a delayed at the above is input, the error type signal f of the omission error is output, and In the case of a bit value, an error type signal f of the insertion error is output.

In the error rate calculation section 9, the clock signal b ₂
Clock counter for counting the number of clocks and an error counter for counting the number of error signals of the bit error signal e.
^When a predetermined reference number such as ⁷ to 10 ⁸ is reached, the number of error signals counted by the error number counter is read,
The error rate g is calculated by dividing the number of error signals by the reference number and sent to the next storage unit 12.

When the synchronization control signal 10 is input from the synchronization control unit 10 after the power is turned on, the output control unit 13 including the CPU establishes the synchronization between the input signal a and the reference pattern signal c. After the elapse of the grace time, the storage unit 1
Then, a data fetch signal h is sent to the device 2.

Then, the storage unit 12 stores the clock signal b ₂
In synchronization with the input signal a and the data memory 12b
To the error memory 1
2c, fetch the error type signal f, and write it to the error type memory 12d. Further, it takes in the error rate g output from the error rate calculation section 9 and writes it into the error rate memory 12a.

When a display command is input from an operation unit 14 such as a keyboard, the output control unit 13
The error rate g, the input signal a, the error signal e, and the error type signal f stored in each of the memories 12a to 12d are read out and displayed on a display screen 15a of a display unit 15 constituted by, for example, a CRT display device. Display output in the format shown in.

That is, as shown in FIG.
, The waveform of the bit error signal e and the waveform of the error type signal f are displayed in synchronization with the time axis. In the waveform of the error type signal f, the positive pulse is indicated as an insertion error (Insertion Error) in which a correct bit value of [0] changes to an incorrect bit value of [1], and the negative pulse is indicated as [Insertion Error]. Omision Error in which the correct bit value of [1] changes to the incorrect bit value of [0]
). In addition, an input signal name and an error rate g are displayed above the display screen 15a.

Therefore, on the display screen 15a, the position and type of bit error occurrence are displayed on the input signal waveform. When a print command is input from the operation unit 14, the output control unit 13 displays the waveform of the input signal a, the waveform of the bit error signal e, and the waveform of the error type signal f shown on the display screen 15a of the display unit 15 in FIG. The waveform and the error rate g are printed out using the printer 16 in the same format.

In the bit error measuring and measuring apparatus thus configured, a bit error in the digital input signal a is detected by the error detection section 2 and output as a bit error signal e. The error type of this error is detected by the error type detection unit 8 and output as an error type signal f. The error rate g of the input signal a is calculated by the error rate calculator 9. Then, the error signal e, the error type signal f, and the error rate g are stored in the storage unit 12 together with the input signal a.

The output control section 13 reads out the waveform of the input signal a, the error occurrence position and error type in the input signal waveform, and the calculated error rate g as shown in FIG. Graphic display is simultaneously performed on the display screen 15a.

The same contents are printed out by the printer 16 as necessary. Therefore, for example, when the input signal a is a bit pattern embedded in a transmission frame, when errors frequently occur at a specific bit position on the transmission frame, information is written or read at a corresponding bit position on the transmission frame. It can be considered that an abnormality has occurred in the electronic component or the software module that is running.

When bit errors frequently occur over the entire transmission frame, it can be considered that external noise has mixed in the transmission system including the radio line. In addition, insertion errors of bit errors and omission errors
When only one of the types of error types frequently occurs, it is considered that a hardware failure has occurred in one of the logic elements in the logic circuit having the symmetric characteristic.

As described above, by visually outputting the error occurrence position and error type on the input signal waveform,
It is possible to efficiently determine the location of the abnormality in the measurement object and the cause of the abnormality.

The present invention is not limited to the above embodiment. In the embodiment, as shown in FIG. 2, the input signal waveform, the bit error signal waveform, and the error type signal waveform are displayed at different positions on the display screen 15a of the display unit 15, but for example, as shown in FIG. A marker 1 that simultaneously displays the signal waveform and the data value of the input signal, and indicates the error type of the corresponding error at the error occurrence position on the input signal waveform.
7a and 17b may be overwritten.

Further, as shown in FIG. 4, the display of the data value of the input signal is deleted, and only the markers 17a and 17b indicating the error type of the corresponding error are overwritten at the error occurrence position on the input signal waveform. You may.

[0041]

As described above, in the bit error measuring apparatus of the present invention, the type of error is detected simultaneously in addition to the bit error of the input signal, and the input signal waveform, the error occurrence position on the input signal waveform, The error type is visually output simultaneously using a display or a printer.

Therefore, an operator or a technician of this bit error measuring device can check at a glance the bit error position and the error type in the input signal, and efficiently find out the abnormality occurrence position and the abnormality cause in the measurement object. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a bit error measuring device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an input signal waveform, an error position, and an error type displayed on a display unit in the bit error measurement device.

FIG. 3 is a diagram showing an input signal waveform, an error position, and an error type displayed on a display unit in a bit error measurement device according to another embodiment of the present invention.

FIG. 4 is a diagram showing an input signal waveform, an error position, and an error type displayed on a display unit in a bit error measuring device according to still another embodiment of the present invention.

[Explanation of Code] 2 ... Error detection unit 4 ... Clock recovery circuit 7 ... Reference pattern signal generation unit 8 ... Error type determination unit 9 ... Error rate calculation unit 10 ... Synchronization control unit 12 ... Storage unit 13 ... Output control unit 14 ... Operation unit 15 Display unit 16 Printer 17a. 17b ... marker

Claims (1)

[Claims] 1. A bit error measuring apparatus for measuring a bit error by receiving an output signal of a device under test which has received a digital signal having a bit pattern of a predetermined period, comprising the steps of: A reference pattern signal generator (7) for outputting a reference pattern signal having the respective signals of the output signal of the device under test, each bit of the output signal and a reference pattern signal output from the reference pattern signal generator. An error detection unit (2) that compares the bits with each other and outputs an error signal when there is a mismatch, and an error rate calculation unit that calculates an error rate of the input signal based on the error signal output from the error detection unit ( 9), an error type determination unit (8) that determines an error type of the error detected by the error detection unit and outputs an error type signal, and at least the input signal, the error signal and A storage unit (12) for storing the error type signal in time series, and reading out the input signal, the error signal and the error type signal stored in the storage unit, and obtaining an input signal waveform, an error in the input signal waveform. A bit error measuring device comprising: an output control unit (13) for outputting an occurrence position, an error type, and the calculated error rate.