JP3394944B2 - Error detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input digital
Error Detection for Detecting Bit Errors in Data Signals
Related to the device, especially the input digital data signal
Compare with the reference signal output from the reference signal generator.
Bits included in the digital data signal
The present invention relates to an error detection device that detects an error. [0002] 2. Description of the Related Art In recent years, mobile communication networks, the Internet,
In various communication networks such as a public telephone network and a satellite network,
Digital data signals are sent and received instead of traditional analog signals
It is being trusted. Therefore, digital day
Transmission lines such as cables for transmitting data signals and digital data
Relay device for relaying signals and sending and receiving digital data signals
Need to test that the transceiver
is there. [0003] One of the tests is a digital data signal.
There is a bit error measurement to measure the bit errors contained in
You. In this bit error measurement, transmission lines and relay devices
For the test (test target) such as
Output signal via this measurement target
Bit errors in digital data signals
Then, for example, an error rate or the like is calculated. FIG. 4 is a block diagram showing a schematic configuration of an error detection device.
It is a lock figure. Trial of transmission line, relay device, transceiver device, etc.
Test input from data input terminal 1 via test target
Signal a composed of digital data signals for
It is input to the circuit 2 and the auto search unit 3. [0005] The auto search unit 3 is a digital search unit shown in FIG.
High (H) level in the input signal a composed of the data signal
Signal level V_HAnd low (L) level signal level
V_LAnd the signal level V_H, V_Lin
Between the signal levels for binarizing the input signal a.
Threshold signal level V_THAsking. [0006] V_TH= (V_H+ V_L) / 2 The auto search unit 3 determines the threshold signal level V
_THTo the waveform shaping circuit 2. [0007] The waveform shaping circuit 2 outputs a digital data signal.
Is input from the auto search unit 3
Threshold signal level V_THAnd binarized as shown in FIG.
Amplitude V_SBinarized waveform signal a having₁Create the following knowledge
It is sent to another circuit 4. Further, the clock input terminal 5
The clock signal b, which is synchronized with the input signal a,
The detection signal is applied to the detection unit 6 and the reference signal generation unit 7. The identification circuit 4 is, for example, a D-type FF (flip).
・ Flop). And the waveform shaping circuit
2 is a binarized waveform signal a₁Is this D-type FF
Is applied to the D input terminal. Furthermore, the clock terminal C
The clock signal b is applied. And this D type
The FF is applied to the clock terminal C as shown in FIG.
Synchronized with the rising edge of the clock signal b
The binary waveform signal a applied to the D input terminal₁of
It takes in the signal value and outputs it from the Q output terminal. That is,
This discriminating circuit 4 uses the binary value inputted from the waveform shaping circuit 2.
Waveform signal a₁Is one clock cycle of the clock signal b.
Latched for the new digital data signal a_Two
Is input to one input terminal of the next error detection unit 6.
You. [0010] The reference signal generator 7 is provided with a
From the reference signal data writing section 9 of the control section 8
Each bit data is written. Each bit of this reference signal
The data is a digital test signal applied to the measurement target described above.
Bit data equal to each bit data of the data signal
You. Therefore, the clock applied from the reference signal generator 7 is
Clock that is read and output in synchronization with the clock of the clock signal.
The quasi-signal c is the digital data input to the error detection device.
Data signal (input signal a). Reference signal
The reference signal c output from the generator 7 enters the error detector 6.
Is forced. [0011] The error detection unit 6 detects the clock signal b.
Digital data input from the identification circuit 4 in synchronization with the
Data signal a_TwoBit data and reference signal generator included in
Each bit data included in the reference signal c output from 7
And the digital data signal a_TwoIncluded
Bit errors are detected. The error detection unit 6 has detected
The bit error d is sent to the arithmetic processing unit 10 of the control unit 8.
The arithmetic processing unit 10 uses the input bit error d to
Calculate the ratio and output it to the display unit 11, for example. [0012] In the error detection device having such a configuration,
Included in the input signal a composed of the input digital data signal.
How to detect bit errors with high accuracy depends on the waveform
In the shaping circuit 2, how precisely the input signal a
Binary waveform signal a₁Depends on how to format
You. Furthermore, in the auto search section 3,
Exactly threshold signal level V_THDepends on what you set
I have. As described above, the threshold signal level V_TH
Is a high (H) level signal level V of the input signal a.
_HAnd a low (L) level signal level V_LAnd asked from
You. Each signal level V_H, V_LMeasurement is generally
Detected by using a hold circuit. Therefore, c
A (H) level signal level V_HIs detected and the
Hold with a denser or the like. High (H) level signal level V_HThe
When held by a denser or the like, as shown in FIG.
Mark rate of signal a (high (H) level for the entire signal
Is extremely low, the discharge of the capacitor
The high (H) level signal level V_HDecrease. same
As shown in FIG. 6B, the mark ratio of the input signal a is
Is extremely high, the low (L) level signal level V_Lof
Detection accuracy decreases. As a result, the mark ratio of the input signal a
Is extremely low or extremely high,
Value signal level V_THSetting accuracy decreases. Therefore, the error detection device shown in FIG.
In addition, the mark ratio calculation unit 12 is provided in the control unit 8.
I have. This mark ratio calculation unit 12 performs a basic
The quasi-signal data writing unit 9 transmits the quasi-signal
When writing data, capture this reference signal data
Then, the mark ratio of the reference signal c is calculated by software.
The calculated mark rate is, for example, 1/8 to 7/8.
If it is out of the range, the operation stops for the auto search unit 3.
Command g to stop the operation of the auto search unit 3
You. In this case, there is an instruction to the waveform shaping circuit 2.
High signal level V_THIs set manually by the operator.
Set. [0017] However, FIG.
In the error detection device shown,
Challenges. That is, a transmission line, a relay device, and a transmission / reception device
Digital for test applied to measurement target (test target) such as
If the bit length (signal length) of the data signal is long,
Signal data for creating a digital data signal of
Also increases the amount of data. As a result, this error detection device
Before starting the test using the reference signal data writing unit 9,
The reference signal data is sent to the reference signal generator 7.
At the time of writing, the mark ratio calculation unit 10 outputs the reference signal data.
Data processing when calculating the mark ratio using
The burden of processing increases. Therefore, the mark ratio of the reference signal c is 1 /
It takes a long time to judge whether it is out of the allowable range of 8 to 7/8.
It is necessary to actually start the test using this error detection device.
There is a problem that the preparation time before starting
Work efficiency decreases. Note that transmission lines, relay devices, transmission / reception devices, etc.
When a new measurement target (test target) is constructed,
Test digital applied to this measurement target (test target)
Since it is necessary to set various conditions for the data signal,
Extremely high and extremely low
available. The present invention has been made in view of such circumstances.
Output from the reference signal generator during the test execution process.
To detect the DC average value of the reference signal
Before starting the actual measurement on the measurement target
Preparation time can be shortened with a simple circuit configuration.
An error detection device that can greatly improve the overall measurement work efficiency
The purpose is to provide. [0022] SUMMARY OF THE INVENTION The present invention provides a method for inputting data.
Bit data included in the digital data signal and the output bit data.
Outputs reference data from the reference signal generator, which can set the cut data arbitrarily
Error measurement with each bit data included in the reference signal
The digital data signal input by comparing
Applied to an error detection device that detects bit errors contained in signals
Is done. In order to solve the above problems, the present invention
In the error detection device, the input digital data
The high and low signal levels.
This digital data is output from each detected signal level.
The threshold signal level for binarizing the signal is determined and output.
Auto search section and digital data input
Signal to the threshold signal level output from the auto search unit.
Waveform shaping circuit for shaping into a binarized waveform using
Input the signal value of the binarized waveform signal output from the shaping circuit
Clock signal synchronized with the digital data signal
Synchronize with lock and capture new digital data to error measurement unit
Identification circuit that outputs as a data signal, and reference signal generator
DC average of the signal level of the reference signal output from the
Output DC average value detection circuit and DC average value detection circuit
The output DC average value is out of the predetermined allowable range
Auto search to stop the operation of the auto search section when
Unit control unit. In the error detecting device configured as described above,
Signal level of the reference signal output from the reference signal generator
DC average value detection circuit is provided to detect the DC average value of the bell.
Have been. The DC average of the signal level of the reference signal is
The mark rate of a reference signal consisting of digital data signals
Respond. In other words, when the DC average value increases, the mark rate increases.
As the DC average value decreases, the mark rate also decreases. Therefore, the control unit of the automatic search unit
The DC average value detected by the current average value detection circuit is
If the value is outside the allowable range, the operation of the auto search
Stops the waveform shaping from the auto search section.
The wrong threshold signal level is not applied to the road.
No. As described above, the reference signal is generated during the test execution process.
The DC average value of the reference signal output from the
Data processing tasks during the test preparation stage.
Dramatic simplification improves overall measurement work efficiency
Wear. [0027] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
This will be described with reference to FIG. FIG. 1 shows an error detection device according to an embodiment.
FIG. 2 is a block diagram showing a schematic configuration of the embodiment. Conventional as shown in FIG.
The same parts as in the error detection device
The detailed description of the part to be performed is omitted. Test pair of transmission line, relay device, transmission / reception device, etc.
Test input from the data input terminal 1 via the
An input signal a composed of a digital data signal is a waveform shaping circuit.
2 and to the auto search unit 3. The auto search unit 3 is a digital data signal
(H) level signal level of the input signal
Bell V_HAnd a low (L) level signal level V_LAnd inspect
Out, these signal levels V_H, V_LSignal level
And a threshold signal for binarizing the input signal a.
Issue level V_THAnd sends it to the waveform shaping circuit 2.
You. The waveform shaping circuit 2 determines whether a digital data signal
Is input from the auto search unit 3
Threshold signal level V_THAnd binarized waveform signal
a₁And sends it to the next identification circuit 4. The clock input terminal 5
The clock signal b synchronized with the input signal a is applied to the identification circuit 4.
And the frequency divider 13 divides the frequency into 1 / N.
Is done. Clock signal divided by 1 / N by divider 13
b₁Is the 1 / N demultiplexer 14 and the error detector 6
a and the reference signal generator 7a. For example, a D-type FF (flip flop)
Is input from the waveform shaping circuit 2.
Binarized waveform signal a₁Is one clock in clock signal b.
New digital data is latched for the lock cycle.
Signal a_TwoInto the next 1 / N demultiplexer 14
Power. The 1 / N demultiplexer 14 reduces the 1 / N
Divided clock signal b_TwoIn synchronization with the clock
Digital data signal a_TwoN digital days
Data signal a_ThreeAnd the error detection unit 6a₁, A_Two,
…, A_NSend to terminal. Therefore, N digital
Data signal a_ThreeOf the original digital data signal a
_TwoTo 1 / N of the frequency. The test digital signal applied to the above-described measurement object
Bit data equal to each bit data of the total data signal
Is mounted on the control section 8a. Base
The quasi-signal data acquisition unit 15 receives a test digital signal from the FD 19.
Each bit data of the reference data signal, that is, each bit data of the reference signal
Reads the bit data and sends it to reference signal data writing section 9a.
Put out. The reference signal data writing unit 9a receives the input reference
Splits each bit data of the signal into N parallel data strings
Then, the data is written into the reference signal generator 7a. The reference signal generator 7a is divided by 1 / N.
Clock signal b_TwoThe original reference signal is synchronized with the clock of
No. (digital data signal for test) by N reference signals c
₁And B of the error detection unit 6a₁, B_Two, ..., B_Nend
Send to child. Therefore, N reference signals c₁Frequency
Number is the original reference signal (digital data signal for testing) of
It drops to 1 / N of the frequency. The error detector 6a outputs a clock divided by 1 / N.
Lock signal b_Two1 / N demultiply
A from Plexa 14₁, A_Two, ..., A_NInput to the terminal
Each digital data signal a_ThreeEach bit data included in
And reference signal generator 7a to B ₁, B_Two, ..., B_NTo terminal
Each input reference signal c_ThreeEach bit data included in
By comparing each digital data signal a_ThreeIncluded
Each bit error detected is detected. The error detector 6 detects
Each bit error d₁To the arithmetic processing unit 10 of the control unit 8a.
Put out. The arithmetic processing unit 10 receives the input bit errors d
₁Is used to calculate the error rate and display it on the display unit 11, for example.
Output. The N signals output from the reference signal generator 7a
Reference signal c₁Is sent to the error detector 6a,
It is input to the DC average value detection circuit 16. This DC average value
As shown in FIG. 2, the detection circuit 16
N LPFs (low pass
Filter), and each LPF is
Each applied reference signal c₁Output the average of the signal levels of
You. Average value of N signal levels output from each LPF
Are added to the N reference signals c.₁A direct showing the overall average
Stream average value V_AIs sent to the next determination circuit 17. As shown in FIG. 2, the judgment circuit 17 comprises two
Of comparators 17a and 17b. And enter
DC average value V_AIs the (+) side end of the comparator 17a
And the ratio inputted to the (−) side terminal of the comparator 17b.
The (-) side terminal of the comparator 17a is also shown in the waveform diagram of FIG.
As described above, the mark rate 1 /
Lower limit voltage V corresponding to 8_ALIs entered. On the other hand, the ratio
The (+) side terminal of the comparator 17b is also shown in the waveform diagram of FIG.
As described above, the mark ratio of the upper limit of the predetermined allowable range 7 /
Upper limit voltage V corresponding to 8_AHIs entered. Therefore, N reference signals c₁Whole straight
Stream average value V_AIs the lower limit voltage V of the allowable range._ALWhen it is less than
Alarm e indicating out of tolerance from comparator 17a_LIs the control unit 8
A is sent to the automatic search section control section 18 of FIG. further,
N reference signals c₁DC average value V of the whole_AIs acceptable
Upper limit voltage V_AHExceeds the allowable range from the comparator 17b.
Alarm e indicating_HIs the auto search section control section 1 of the control section 8a.
8 is sent. The auto search unit control unit 18 has N reference units.
Signal c₁DC average value V of the whole_AOut of tolerance
For one of the alarms e_L, E_HWhen input is detected,
The operation stop command g is sent to the auto search unit 3 to
The operation of the port search unit 3 is stopped. In this case, an instruction to the waveform shaping circuit 2 is provided.
High signal level V_THIs set manually by the operator.
Set. In the error detecting device configured as described above,
Tester performs a new test on the test object.
Digital data for testing to be applied to the test object.
Generates a reference signal from FD19 for each bit data of data signal
It is downloaded to the unit 7a. When the download process is completed, a test is performed.
The tester actually puts the test digital data
Data signal. Then, this error detection device
The digital data signal passed through the test object is
The input signal a (a_Three) Each bit
Data and reference signal output from reference signal generating section 7a
c₁Is compared with each bit data by the error detection unit 6a.
And the input signal a (a_Three)
To detect. In this case, the error measurement processing for the input signal a is performed.
In parallel with the process, the reference output from the reference signal generator 7a
Signal c₁DC average of signal level corresponding to mark rate of
V_AIs detected by the DC average value detection circuit 16 which is a hardware circuit.
Is done. Then, the detected DC average value V_ABut
Voltage V corresponding to the range of 1/8 to 7/8 _AL
And upper limit voltage V_AHThe allowable range (V_AL~ V_AHOutside)
Then, the operation of the auto search unit 3 stops. Therefore, even if the input signal a
Even if the peak rate rises or falls extremely,
By stopping the operation of the auto search unit 3,
Erroneous threshold from auto search section 3 to waveform shaping circuit 2
Value signal level V_THIs not applied. As described above, the reference signal is generated during the test execution.
Reference signal c output from unit 7a₁DC average value V of_ATo
Since it is detected in hardware, the data in the test preparation stage
Data processing tasks can be greatly simplified.
The overall measurement work efficiency can be greatly improved. The DC average value V corresponding to the mark rate_A
DC average value detection circuit 16 for detecting
In the conventional error detection device shown in FIG.
Compared to the case of calculating the mark ratio by software
Determine whether the signal level of the signal is within the allowable range
Can be performed almost in real time. The digital data signal and the input
To quickly establish synchronization with the reference signal, the computer
From the control unit 8a comprising the reference signal to the reference signal generation unit 7a
Instead of writing the digital data signal
A writable and readable memory circuit is provided.
Write an input digital data signal for one cycle to the circuit,
Error measurement using the written signal for one cycle as a reference signal
A device has been proposed (Japanese Patent Laid-Open No. 8-149112)
Information). The automatic search in this error measuring device
Means for determining mark ratio 1/8 to 7/8 as an execution condition
As an alternative, the DC average value detection circuit 16 of FIG.
It is possible. [0050] As described above, the error detection according to the present invention is performed.
In the device, the signal is output from the reference signal generator during the test execution process.
The DC average value of the input reference signal is detected in a hardware manner,
If this DC average value is out of the allowable range, the auto search
Operation has been stopped. Therefore, the measurement target is actually measured.
Simple circuit configuration that can shorten the preparation time before starting
Greatly improves overall measurement work efficiency, including the preparation period.
Wear.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a schematic configuration of an error detection device according to an embodiment of the present invention; FIG. 2 is a block diagram showing a DC average value detection circuit incorporated in the error detection device of the embodiment; FIG. 3 is a diagram showing a decision circuit. FIG. 3 is a signal waveform diagram for explaining the operation of the error detection device of the embodiment. FIG. 4 is a block diagram showing a schematic configuration of a conventional error detection device. FIG. 6 is a waveform chart for explaining the problem of the conventional error detection apparatus. [Description of References] 1. Data input terminal 2. Waveform shaping circuit 3. Auto search unit 4. Identification circuit 5 Clock input terminals 6, 6a Error measuring units 7, 7a Reference signal generating units 8, 8a Control units 9, 9a Reference signal data writing unit 10 Arithmetic processing unit 13 Frequency divider 14 1 / N demultiplexer 16: DC average value detection Circuit 17 ... judging circuit 18 ... auto chart unit control unit 19 ... FD

Continuation of the front page (72) Inventor Hiroshi Miyamoto 2-3-1 Otemachi, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-5-7135 (JP, A) JP-A-11- 234349 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 1/00 G06F 11/00 310 H04L 1/20

Claims (1)

(57) [Claim 1] A reference signal output from a reference signal generator (7a) capable of arbitrarily setting each bit data included in an input digital data signal and output bit data. In an error detection device for detecting a bit error included in the input digital data signal by comparing each bit data included in the digital data signal with an error measuring unit (6a), a high level of the input digital data signal is provided. An auto search unit (3) for detecting each signal level of a digital signal and a low level, obtaining a threshold signal level for binarizing the digital data signal from the detected signal level, and outputting the threshold signal level; A waveform shaping circuit (2) for shaping the input digital data signal into a binary waveform using the threshold signal level output from the auto search unit; The signal value of the binarized waveform signal output from the waveform shaping circuit is captured in synchronization with the clock of the clock signal synchronized with the input digital data signal, and output as a new digital data signal to the error measurement unit. A DC average value detection circuit for detecting a DC average value of a signal level of a reference signal output from the reference signal generation unit;
And an auto search section control section (18) for stopping the operation of the auto search section when the DC average value detected by the DC average value detection circuit deviates from a predetermined allowable range. apparatus.