KR19980076329A - Contact hole and method for forming the semiconductor device - Google Patents
Contact hole and method for forming the semiconductor device Download PDFInfo
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- KR19980076329A KR19980076329A KR1019970013009A KR19970013009A KR19980076329A KR 19980076329 A KR19980076329 A KR 19980076329A KR 1019970013009 A KR1019970013009 A KR 1019970013009A KR 19970013009 A KR19970013009 A KR 19970013009A KR 19980076329 A KR19980076329 A KR 19980076329A
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- contact hole
- interlayer insulating
- etch stop
- insulating film
- film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000010410 layer Substances 0.000 claims abstract description 66
- 239000011229 interlayer Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 19
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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Abstract
본 발명은 콘택홀의 접촉 저항을 감소시킬 수 있는 반도체 장치의 콘택홀 및 그 형성 방법에 관한 것으로, 반도체 장치의 콘택홀은, 반도체 기판상에 소정의 거리를 두고 형성된 도전층 패턴들과, 상기 도전층 패턴들을 포함하여 상기 반도체 기판상에 형성된 층간절연막, 상기 층간절연막을 식각하여 서로 인접한 도전층 패턴들의 사이에 형성되어 있되, 그 저면의 크기가 상부 및 중간부 보다 상대적으로 크게 형성된 콘택홀과, 상기 콘택홀 저면의 바닥 영역과 양측벽을 제외한 상부 표면 및 콘택홀의 양측 상에 형성된 식각 저지층을 포함한다. 이와 같은 장치에 의해서, 콘택홀 저면을 콘택홀의 상부 및 중간부 보다 상대적으로 크게 형성할 수 있고, 따라서 콘택홀 바닥면의 반도체 기판과 콘택 플러그막과의 접촉 저항을 감소시킬 수 있다.The present invention relates to a contact hole of a semiconductor device capable of reducing contact resistance of a contact hole and a method of forming the contact hole. The contact hole of the semiconductor device includes conductive layer patterns formed at a predetermined distance on a semiconductor substrate, and the conductive An interlayer insulating film formed on the semiconductor substrate including layer patterns, a contact hole formed between the conductive layer patterns adjacent to each other by etching the interlayer insulating film, the bottom surface having a relatively larger size than the upper and middle portions; And an etch stop layer formed on both sides of the contact hole and the top surface except the bottom region and both side walls of the bottom of the contact hole. By such a device, the bottom of the contact hole can be formed relatively larger than the upper and middle portions of the contact hole, and thus the contact resistance between the semiconductor substrate on the bottom of the contact hole and the contact plug film can be reduced.
Description
본 발명은 반도체 장치의 콘택홀 및 그 형성 방법에 관한 것으로, 좀 더 구체적으로는, 콘택홀의 접촉 저항(contact resistance)을 감소시키는 반도체 장치의 콘택홀 및 그 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact hole of a semiconductor device and a method of forming the same. More particularly, the present invention relates to a contact hole of a semiconductor device and a method of forming the same, which reduces contact resistance of the contact hole.
반도체 장치가 점차 고집적화되어 감에 따라 반도체 장치 상에 소자를 구성하기 위한 디자인 룰의 크기(design rule size)도 점점 감소하고 있다. 이와 같은 디자인 룰 크기의 감소는 반도체 장치 상의 라인 패턴(line pattern) 및 콘택 패턴(contact pattern)의 축소로 이어진다.As semiconductor devices become increasingly integrated, design rule sizes for constituting devices on semiconductor devices are decreasing. This reduction in design rule size leads to reduction of line patterns and contact patterns on the semiconductor device.
그러나, 라인 패턴이 포토리소그라피(photolithography) 공정의 노광 기술의 발전으로 서브-쿼터 마이크론(sub-quarter micron) 크기의 패턴도 용이하게 형성할 수 있는 반면에, 콘택 패턴은 포토리소그라피 기술 및 에칭(etching) 기술이 뒷받침되어야 한다.However, while the line pattern can easily form sub-quarter micron size patterns due to the development of the exposure technology of the photolithography process, the contact pattern can be formed using photolithography technology and etching. The technology must be supported.
특히, 반도체 장치의 고집적화에 의한 단차의 증가는 높은 종횡비(aspect ratio)를 갖는 콘택홀(contact hole) 구조를 야기시키고, 이로 인해 서브-쿼터 마이크론 이하의 작은 크기를 갖는 콘택홀에서는 후속 도전막의 접촉 저항이 지나치게 높아지는 문제점이 발생된다.In particular, an increase in the level difference due to the high integration of the semiconductor device causes a contact hole structure having a high aspect ratio, which causes contact of subsequent conductive films in contact holes having a small size of sub-quarter microns or less. The problem that resistance becomes too high arises.
상술한 문제점을 해결하기 위해 제안된 본 발명은, 콘택홀의 접촉 저항을 감소시킬 수 있는 반도체 장치의 콘택홀 및 그 형성 방법을 제공하는 데 그 목적이 있다.Disclosure of Invention The present invention proposed to solve the above-mentioned problem is an object of the present invention to provide a contact hole and a method of forming the semiconductor device that can reduce the contact resistance of the contact hole.
도 1은 본 발명의 실시예에 따른 반도체 장치의 콘택홀의 구조를 개략적으로 보여주는 수직 단면도;1 is a vertical cross-sectional view schematically showing the structure of a contact hole in a semiconductor device according to an embodiment of the present invention;
도 2A 내지 도 2L은 도 1에 도시된 반도체 장치의 콘택홀 형성 방법을 순차적으로 보여주는 공정도.2A through 2L are flowcharts sequentially illustrating a method for forming contact holes in the semiconductor device of FIG. 1.
* 도면의 주요 부분에 대한 부호 설명 *Explanation of symbols on the main parts of the drawings
10 : 반도체 기판 12, 14 : 게이트 전극층10: semiconductor substrate 12, 14: gate electrode layer
16 : 고온산화막 18, 28, 32 : 실리콘 질화막16: high temperature oxide film 18, 28, 32: silicon nitride film
20 : BPSG 22, 24 : 도전막 패턴20: BPSG 22, 24: conductive film pattern
26 : PE-산화막 34 : 텅스텐 플러그막26 PE-oxide film 34 tungsten plug film
(구성)(Configuration)
상술한 바와 같은 목적을 달성하기 위한 본 발명에 의하면, 반도체 장치의 콘택홀은, 반도체 기판상에 소정의 거리를 두고 형성된 도전층 패턴들과; 상기 도전층 패턴들을 포함하여 상기 반도체 기판상에 형성된 층간절연막; 상기 층간절연막을 식각하여 서로 인접한 도전층 패턴들의 사이에 형성되어 있되, 그 저면의 크기가 상부 및 중간부 보다 상대적으로 크게 형성된 콘택홀과; 상기 콘택홀 저면의 바닥 영역과 양측벽을 제외한 상부 표면 및 콘택홀의 양측 상에 형성된 식각 저지층을 포함한다.According to the present invention for achieving the above object, the contact hole of the semiconductor device comprises: conductive layer patterns formed at a predetermined distance on the semiconductor substrate; An interlayer insulating film formed on the semiconductor substrate including the conductive layer patterns; A contact hole formed between the conductive layer patterns adjacent to each other by etching the interlayer insulating layer, the contact hole having a bottom surface relatively larger than an upper portion and a middle portion; And an etch stop layer formed on both sides of the contact hole and the top surface except the bottom region and both side walls of the bottom of the contact hole.
이 장치의 바람직한 실시예에 있어서, 상기 식각 저지층은 실리콘 질화막이다.In a preferred embodiment of the device, the etch stop layer is a silicon nitride film.
상술한 목적을 달성하기 위한 본 발명에 의하면, 반도체 장치의 콘택홀 형성 방법은, 반도체 기판상에 도전층 패턴들을 형성하는 공정과; 상기 도전층 패턴들을 포함하여 상기 반도체 기판 상에 제 1 층간절연막 및 제 1 식각 저지층, 그리고 제 2 층간절연막을 순차적으로 형성하는 공정과; 상기 제 2 층간절연막 상에 도전막 패턴을 형성하는 공정과; 상기 도전막 패턴을 포함하여 상기 제 2 층간절연막 상에 제 3 층간절연막 및 제 2 식각 저지층을 순차적으로 형성하는 공정과; 상기 도전층 패턴들 중, 서로 인접한 도전막 패턴층 사이의 상기 제 1 식각 저지층이 노출되도록 상기 제 2 식각 저지층, 제 3 층간절연막, 그리고 제 2 층간절연막을 순차적으로 식각하여 콘택홀을 형성하되, 콘택홀 양측의 상기 도전막 패턴이 콘택홀의 양측벽상으로 노출되지 않도록 형성하는 공정과; 상기 콘택홀의 양측벽 상에 제 3 식각 저지층을 형성하는 공정과; 상기 콘택홀 저면의 반도체 기판이 노출되도록 상기 콘택홀 바닥부의 제 1 식각 저지층 및 제 1 층간절연막을 식각하는 공정과; 상기 제 1 및 제 2, 그리고 제 3 식각 저지층을 마스크로 사용하고, 상기 콘택홀 바닥부 양측벽의 노출된 상기 층간절연막을 습식식각하는 공정을 포함한다.According to the present invention for achieving the above object, a method of forming a contact hole in a semiconductor device comprises the steps of forming conductive layer patterns on a semiconductor substrate; Sequentially forming a first interlayer insulating film, a first etch stop layer, and a second interlayer insulating film on the semiconductor substrate including the conductive layer patterns; Forming a conductive film pattern on the second interlayer insulating film; Sequentially forming a third interlayer insulating film and a second etch stop layer on the second interlayer insulating film including the conductive film pattern; Of the conductive layer patterns, the second etch stop layer, the third interlayer insulating film, and the second interlayer insulating film are sequentially etched to expose the first etch stop layer between adjacent conductive film pattern layers to form a contact hole. A process of forming the conductive film patterns on both sides of the contact hole so as not to be exposed on both side walls of the contact hole; Forming a third etch stop layer on both side walls of the contact hole; Etching the first etch stop layer and the first interlayer insulating layer so that the semiconductor substrate on the bottom of the contact hole is exposed; And using the first, second, and third etch stop layers as a mask, and wet etching the exposed interlayer insulating layers on both sidewalls of the bottom of the contact hole.
이 방법의 바람직한 실시예에 있어서, 상기 제 1 및 제 2, 그리고 제 3 식각 저지층은 실리콘 질화막으로 형성된다.In a preferred embodiment of this method, the first, second and third etch stop layers are formed of a silicon nitride film.
이 방법의 바람직한 실시예에 있어서, 상기 제 1 및 제 2, 그리고 제 3 식각 저지층은 각각 500Å, 1000Å, 500Å 범위내에서 형성된다.In a preferred embodiment of this method, the first, second and third etch stop layers are formed in the range of 500 kV, 1000 kV and 500 kV, respectively.
이 방법의 바람직한 실시예에 있어서, 상기 제 1 층간절연막은 고온산화막으로 형성된다.In a preferred embodiment of this method, the first interlayer insulating film is formed of a high temperature oxide film.
이 방법의 바람직한 실시예에 있어서, 상기 제 1 층간절연막은 1000 - 2000Å 범위내에서 형성된다.In a preferred embodiment of this method, the first interlayer dielectric film is formed in the range of 1000-2000 kV.
이 방법의 바람직한 실시예에 있어서, 상기 제 2 층간절연막은 USG 와 BPSG 중, 하나 이상으로 형성된다.In a preferred embodiment of this method, the second interlayer insulating film is formed of at least one of USG and BPSG.
이 방법의 바람직한 실시예에 있어서, 상기 제 3 층간절연막은 PE-산화막으로 형성된다.In a preferred embodiment of this method, the third interlayer insulating film is formed of a PE oxide film.
(작용)(Action)
이와 같은 반도체 장치의 콘택홀 형성 방법에 의해서, 콘택홀 저면을 콘택홀의 상부 및 중간부 보다 상대적으로 크게 형성할 수 있고, 따라서 콘택홀 바닥면의 반도체 기판과 콘택 플러그막과의 접촉 저항을 감소시킬 수 있다.By the contact hole forming method of the semiconductor device, the bottom of the contact hole can be formed relatively larger than the upper and middle portions of the contact hole, thereby reducing the contact resistance between the semiconductor substrate on the bottom of the contact hole and the contact plug film. Can be.
(실시예)(Example)
이하, 본 발명의 바람직한 실시예를 첨부 도면 도 1 및 도 2에 의거해서 상세히 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, preferred embodiment of this invention is described in detail based on attached drawing FIG.
도 1에는 본 발명의 실시예에 따른 반도체 장치의 콘택홀의 구조가 개략적으로 도시되어 있다.1 schematically shows a structure of a contact hole in a semiconductor device according to an embodiment of the present invention.
도 1을 참조하면, 반도체 기판(10)상에는 소정의 거리를 갖는 게이트 전극층(12, 14)들이 형성되고, 그리고, 상기 게이트 전극층(12, 14)들을 포함하여 상기 반도체 기판(10)상에는 고온산화막(16), 제 1 실리콘 질화막(18), BPSG(BoroPhophoSilicate Glass ;20), 도전막 패턴(22, 24), PE-산화막(26), 제 2 실리콘 질화막(28)이 순차적으로 형성된다.Referring to FIG. 1, gate electrode layers 12 and 14 having a predetermined distance are formed on a semiconductor substrate 10, and a high temperature oxide film is formed on the semiconductor substrate 10 including the gate electrode layers 12 and 14. (16), the first silicon nitride film 18, the BPSG (BoroPhophoSilicate Glass; 20), the conductive film patterns 22 and 24, the PE-oxide film 26, and the second silicon nitride film 28 are sequentially formed.
그리고 상기 절연막들(28, 26, 20, 18, 16)을 식각하여 상기 게이트 전극층들(12, 14) 사이의 반도체 기판(10)이 노출되도록 형성된 콘택홀(30)은 그 저면의 크기가 콘택홀(30)의 중간부 및 상부 보다 상대적으로 크게 형성되어 있다.The bottom surface of the contact hole 30 formed by etching the insulating layers 28, 26, 20, 18, and 16 so that the semiconductor substrate 10 between the gate electrode layers 12 and 14 is exposed. It is formed relatively larger than the middle part and the upper part of the hole 30.
또한, 상기 콘택홀(30)의 상부 및 중간부 보다 상대적으로 크게 형성된 저면의 양측벽을 제외한 측벽상에는 제 3 실리콘 질화막(32)이 형성되어 있다.In addition, a third silicon nitride film 32 is formed on the sidewalls of the contact hole 30 except for both sidewalls of the bottom surface formed larger than the upper and middle portions of the contact hole 30.
상술한 바와 같은 구조를 갖는 반도체 장치의 콘택홀의 형성 방법을 도 2A 내지 도 2L을 참조하여 설명하면 다음과 같다.A method of forming a contact hole in a semiconductor device having the structure described above will now be described with reference to FIGS. 2A to 2L.
먼저, 도 2A 및 도 2B를 참조하면, 반도체 기판(10)상에 이 기술 분야에서 잘 알려진 기술을 이용하여 서로 소정의 거리로 이격되도록 게이트 전극층들(12, 14)을 형성한다. 이때, 이들 게이트 전극층(12, 14)들은 각각 반도체 기판(10)상에 게이트 절연막(12a, 14a), 게이트 전극(12b, 14b), 그리고 게이트 상부막(12c, 14c)이 순차적으로 형성되고, 이들(12a, 12b, 12c), (14a, 14b, 14c)의 양측벽에는 게이트 스페이서(12d, 14d)가 형성된 구조를 갖는다.First, referring to FIGS. 2A and 2B, the gate electrode layers 12 and 14 are formed on the semiconductor substrate 10 so as to be spaced apart from each other by a predetermined distance using a technique well known in the art. In this case, the gate electrode layers 12 and 14 are sequentially formed on the semiconductor substrate 10 with the gate insulating layers 12a and 14a, the gate electrodes 12b and 14b, and the gate upper layers 12c and 14c, respectively. Gate spacers 12d and 14d are formed on both sidewalls of these 12a, 12b, 12c, and 14a, 14b, 14c.
다음, 도 2C에 있어서, 상기 게이트 전극층들(12, 14)을 포함하여 상기 반도체 기판(10)상에 고온산화막(16) 및 제 1 실리콘 질화막(18)을 형성하는데, 상기 고온산화막(16)은 약 1000 - 2000Å 범위내에서 형성하고, 제 1 실리콘 질화막(18)은 약 500Å 범위내에서 형성한다.Next, in FIG. 2C, the high temperature oxide film 16 and the first silicon nitride film 18 are formed on the semiconductor substrate 10 including the gate electrode layers 12 and 14. Is formed in the range of about 1000 to 2000 microseconds, and the first silicon nitride film 18 is formed in the range of about 500 microseconds.
이어서, 도 2D를 참조하면, 상기 제 1 실리콘 질화막(18)상에 BPSG막(20)을 형성한 후, 상기 BPSG막(20)상에 도 2E에 도시된 바와 같이 소정의 도전막 패턴(22, 24)을 형성한다. 이때, 상기 BPSG막(20)은 USG(Undoped silicate glass)막으로 형성되기도 하고 또는, 이들 두 개의 막을 함께 사용하기도 한다.Next, referring to FIG. 2D, after the BPSG film 20 is formed on the first silicon nitride film 18, a predetermined conductive film pattern 22 is formed on the BPSG film 20 as shown in FIG. 2E. , 24). In this case, the BPSG film 20 may be formed of an undoped silicate glass (USG) film, or may be used together.
그리고, 도 2F 및 도 2G를 참조하면, 상기 도전막 패턴(22, 24)을 포함하여 상기 BPSG막(20)상에 PE-산화막(Plasma Enhanced-Oxide ;26) 및 제 2 실리콘 질화막(28)을 순차적으로 형성한다. 여기에서, 상기 제 2 실리콘 질화막(28)은 약 1000Å 범위내에서 형성된다.2F and 2G, the PE-oxide (Plasma Enhanced-Oxide) 26 and the second silicon nitride layer 28 including the conductive layer patterns 22 and 24 are formed on the BPSG layer 20. To form sequentially. Here, the second silicon nitride film 28 is formed in the range of about 1000 kW.
도 2H에 있어서, 상기 게이트 전극층들(12, 14) 사이의 상기 제 1 실리콘 질화막(18)이 소정 부분 노출되도록 상기 제 2 실리콘 질화막(28), PE-산화막(26), 그리고 BPSG막(20)을 순차적으로 식각하여 콘택홀(30)을 형성한다. 이때, 상기 제 1 실리콘 질화막(18)은 상기 콘택홀(30)을 형성하기 위한 식각 공정에서 식각 저지층(etch stopper)로써 작용한다.In FIG. 2H, the second silicon nitride film 28, the PE-oxide film 26, and the BPSG film 20 are exposed so that the first silicon nitride film 18 between the gate electrode layers 12 and 14 is partially exposed. ) Is sequentially etched to form the contact hole 30. In this case, the first silicon nitride layer 18 serves as an etch stopper in an etching process for forming the contact hole 30.
이어서, 상기 콘택홀(30)의 양측벽 상에 도 2I에 도시된 바와 같이 약 500Å 범위내에서 제 3 실리콘 질화막(32)을 형성한다.Subsequently, a third silicon nitride film 32 is formed on both sidewalls of the contact hole 30 within a range of about 500 mW as shown in FIG. 2I.
다음, 도 2J를 참조하면, 상기 콘택홀(30)의 저면의 노출된 제 1 실리콘 질화막(18) 및 고온산화막(16)을 에치백(etch back) 공정으로 상기 콘택홀(30) 저면의 반도체 기판(10)이 노출되도록 식각한다.Next, referring to FIG. 2J, the semiconductor of the bottom surface of the contact hole 30 is etched back through the exposed first silicon nitride layer 18 and the high temperature oxide layer 16 of the bottom surface of the contact hole 30. The substrate 10 is etched to expose the substrate 10.
그리고, 상기 콘택홀(30) 저면의 양측벽의 노출된 고온산화막(16)을 도 2K에 도시된 바와 같이 습식식각 공정을 수행하여 소정의 두께로 식각한다. 이때, 상기 제 1 및 제 3 실리콘 질화막(18, 32)은 식각 저지층으로 작용한다.The exposed high temperature oxide film 16 on both side walls of the bottom surface of the contact hole 30 is etched to a predetermined thickness by performing a wet etching process as shown in FIG. 2K. In this case, the first and third silicon nitride layers 18 and 32 serve as an etch stop layer.
마지막으로, 상기 콘택홀(30)을 텅스텐막(34)으로 충전하면, 도 2L에 도시된 바와 같이 콘택홀(30)의 저면이 콘택홀(30)의 상부 및 중간부 보다 상대적으로 큰 크기를 갖는 반도체 장치의 콘택홀이 형성된다. 이때, 도면에는 도시되지 않았지만, 상기 콘택홀의 바닥면 및 양측벽, 그리고 상기 식각 저지층상에는 장벽 금속막(barrier metal)으로서 Ti/TiN이 형성된다.Finally, when the contact hole 30 is filled with the tungsten film 34, as shown in FIG. 2L, the bottom surface of the contact hole 30 has a larger size than the upper and middle portions of the contact hole 30. A contact hole of the semiconductor device is formed. In this case, although not shown in the drawing, Ti / TiN is formed as a barrier metal on the bottom surface, both sidewalls of the contact hole, and the etch stop layer.
상술한 바와 같은 반도체 장치의 콘택홀 형성 방법에 의해서, 콘택홀 저면을 콘택홀의 상부 및 중간부 보다 상대적으로 크게 형성할 수 있고, 따라서 콘택홀 바닥면의 반도체 기판과 콘택 플러그막과의 접촉 저항을 감소시킬 수 있다.According to the above-described method for forming a contact hole in a semiconductor device, the bottom of the contact hole can be formed relatively larger than the upper and middle portions of the contact hole, so that the contact resistance between the semiconductor substrate at the bottom of the contact hole and the contact plug film is increased. Can be reduced.
Claims (9)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019970013009A KR100254566B1 (en) | 1997-04-09 | 1997-04-09 | Method of fabricating contact hole in semiconductor device |
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| KR1019970013009A KR100254566B1 (en) | 1997-04-09 | 1997-04-09 | Method of fabricating contact hole in semiconductor device |
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