KR19980067733A - Manufacturing method of capacitor - Google Patents

Abstract

The present invention relates to a method of manufacturing a capacitor, comprising: forming an insulating layer having a contact hole for forming an impurity region of a second conductivity type on a substrate of a first conductivity type and exposing the impurity region on the substrate; Forming a plug in contact with the impurity region in the contact hole; forming a first conductive layer and a pattern in contact with the plug on the insulating film; and forming the plug on the side surface of the first conductive layer and the pattern. Forming a storage electrode and removing the pattern by forming a second conductive layer in the form of sidewalls so as to be in contact with the conductive layer; forming a photosensitive film exposing the storage electrode on the insulating film, and sputtering the surface of the storage electrode. And deforming to a saw blade shape by removing the photosensitive film, and forming a dielectric film on the storage electrode. Forming a plate electrode on the substrate; Therefore, the area of the dielectric film formed on the surface of the storage electrode is increased to increase the capacitance.

Description

Manufacturing method of capacitor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor, and more particularly, to a method of manufacturing a capacitor capable of increasing a capacitance in a highly integrated semiconductor device.

Many studies have been conducted to increase the storage density so that the capacitor has a constant storage capacity even if the cell area is reduced due to the high integration of the semiconductor device. To increase the capacitance, capacitors were stacked or formed into three-dimensional structures of trenches to increase the surface area of the dielectric.

Among the capacitors having the three-dimensional structure, the laminated structure has an easy manufacturing process and is suitable for mass production, increasing the storage capacity and being immune to the disturbance of charge information caused by alpha particles. Stacked capacitors are classified into a double stacked structure, a fin structure, or a crown structure according to storage electrodes.

1 (A) to (D) are process diagrams illustrating a method of manufacturing a capacitor according to the prior art.

Referring to FIG. 1 (A), an impurity region in which N-type impurities such as an asic (As) or phosphorus (P) is doped at a high concentration and used as a source and a drain region on a P-type semiconductor substrate 11 ( 13). Then, the insulating film 15 is formed on the semiconductor substrate 11, and a contact portion 17 exposing the impurity region 13 by removing a predetermined portion of the insulating film 15 by photolithography. Form. Polycrystalline silicon doped with impurities to fill the contact hole 17 on the insulating film 15 is deposited thickly by chemical vapor deposition (hereinafter, referred to as CVD). The polysilicon doped with impurities remains only in the contact hole 17 and is etched back to expose the insulating layer 15 to form a plug 19 in contact with the impurity region 13.

Referring to FIG. 1B, polycrystalline silicon doped with impurities on the insulating film 15 is contacted with the plug 19 by CVD, and on this polycrystalline silicon layer, BPSG (Boro Phospho Silicate Glass) or PSG. Insulating material such as (Phospho Silicate Glass) is deposited thickly. The insulating material and the polysilicon are patterned by photolithography, and the first conductive layer 21 and the pattern 23 are defined by patterning the remaining portions of the polysilicon to contact the plug 19.

Referring to FIG. 1C, polysilicon doped with impurities on the insulating film 15 is deposited to cover the surfaces of the first conductive layer 21 and the pattern 23 by the CVD method. Then, the doped polysilicon is etched back so that the surfaces of the insulating film 15 and the pattern 23 are exposed so that the second conductive layer 25 in the form of sidewalls is formed on the side surfaces of the first conductive layer 21 and the pattern 23. ). In this case, the first and second conductive layers 21 and 25 are in contact with each other and electrically connected to each other to form the storage electrode 27. Therefore, the surface area of the storage electrode 27 is increased to increase the capacitance. Then, the pattern 23 is removed.

Referring to FIG. 1D, a dielectric film 28 is formed on a surface of the storage electrode 27, and a polycrystalline silicon doped with impurities is deposited on the dielectric film 28 to form a plate electrode 29.

However, the above-described conventional capacitor manufacturing method has a problem in that it is difficult to improve the capacitance because there is a limit in increasing the surface area of the storage electrode.

Accordingly, an object of the present invention is to provide a method of manufacturing a capacitor that can increase the capacitance by increasing the surface area of the storage electrode.

1 (A) to (D) is a manufacturing process diagram of a semiconductor device according to the prior art

2A to 2E are manufacturing process diagrams of a semiconductor device according to the present invention.

* Description of the symbols for the main parts of the drawings *

31: semiconductor substrate 33: impurity region

35: insulating film 37: contact hole

39: plug 41: first conductive layer

43: Pattern 45: Fifth conductive layer

47: storage electrode 49: photosensitive film

51 dielectric layer 53 plate electrode

A method of manufacturing a capacitor according to the present invention for achieving the above object is to form an insulating film having a contact hole for forming a second conductivity type impurity region on a first conductivity type substrate and exposing the impurity region on the substrate. Forming a plug in contact with the impurity region in the contact hole; forming a first conductive layer and a pattern in contact with the plug on the insulating film; and forming a plug of the first conductive layer and the pattern. Forming a storage electrode on a side of the first conductive layer and a side surface of the pattern so as to contact the first conductive layer, and forming a storage electrode on the side thereof to form a second conductive layer having a sidewall shape and removing the pattern; And forming a photosensitive foil exposing the storage electrode on the insulating film and deforming the surface of the storage electrode into a saw blade shape by sputtering. And removing the photosensitive film to form a dielectric layer on the storage electrode includes a step of forming a plate electrode on the dielectric film.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 (A) to (E) are process diagrams illustrating a method of manufacturing a capacitor according to the present invention.

Referring to FIG. 2A, an impurity region used as a source and a drain region by being heavily doped with N-type impurities such as an asic or phosphorus (P) on a P-type semiconductor substrate 31 ( 33). An insulating film 35 is formed on the semiconductor substrate 31, and a predetermined portion of the insulating film 35 is removed by a photolithography method to form a contact hole 37 exposing the impurity region 33. Polycrystalline silicon doped with impurities to fill the contact hole 37 on the insulating film 35 is deposited by CVD. The polysilicon doped with impurities remains only in the contact hole 37 and is etched back to expose the insulating layer 35 to form a plug 39 in contact with the impurity region 33.

Referring to FIG. 2 (B), polycrystalline silicon doped with impurities on the insulating film 35 is deposited in contact with the plug 39 by a CVD method, and on this polycrystalline silicon layer, BPSG (Boro Phospho Silicate Glass) or PSG. Insulating material such as (Phospho Silicate Glass) is deposited thickly. The insulating material and the polysilicon are patterned by photolithography, and the first conductive layer 41 and the pattern 43 are defined by patterning the remaining portions of the polysilicon to contact the plug 39.

Referring to FIG. 2C, polycrystalline silicon doped with impurities on the insulating layer 35 is deposited to cover the surfaces of the first conductive layer 41 and the pattern 43 by the CVD method. The polysilicon doped with impurities is etched back to expose the surfaces of the insulating layer 35 and the pattern 43, so that the second conductive layer 45 having sidewalls is formed on the side surfaces of the first conductive layer 41 and the pattern 43. ). In this case, the first and second conductive layers 41 and 45 are in contact with each other and electrically connected to form the storage electrode 47. Then, the pattern 43 is removed.

Referring to Fig. 2D, a photosensitive film 49 is applied to the entire surface of the structure described above. Then, the photosensitive film 49 is exposed and developed to expose the first conductive layer 41. In this case, the second conductive layer 45 may be exposed such that the insulating layer 35 is not exposed. The exposed portion of the first conductive layer 41 is sputtered with argon (Ar) or the like. At this time, the surface of the exposed portion of the first conductive layer 41 is roughened and deformed into a saw blade shape. Therefore, the surface area of the first conductive layer 41 is increased, thereby increasing the surface area of the storage electrode 47. In the above, the photosensitive film 49 prevents the insulating film 35 from being damaged when sputtering the first conductive layer 41 with argon or the like.

Referring to FIG. 2E, the photosensitive film 49 is removed. A dielectric film 51 made of silicon oxide or silicon oxide / silicon nitride is formed on the surface of the storage electrode 47. Since the surface area of the storage electrode 47 is increased, the area of the dielectric film 51 is also increased to increase the capacitance. The plate electrode 53 is formed by depositing polysilicon doped with impurities on the dielectric layer 51.

As described above, in the method of manufacturing a capacitor according to the present invention, a photosensitive film is coated on a storage electrode including a first conductive layer and a second conductive layer having a sidewall shape, and then the first conductive layer is exposed by exposure and development, and the photosensitive film is exposed. In order to prevent damage to the insulating layer by using a mask, the storage electrode is sputtered with argon (Ar) or the like to deform the surface into a saw blade shape to increase the surface area.

Therefore, the present invention has an advantage of increasing the capacitance of the dielectric film formed on the surface of the storage electrode.

Claims (3)

Forming an impurity region of a second conductivity type on a substrate of a first conductivity type and forming an insulating film having contact holes for exposing the impurity region on the substrate; Forming a plug in contact with the impurity region in the contact hole; Forming a first conductive layer and a pattern in contact with the plug on the insulating film; Forming a storage electrode on the side of the first conductive layer and the pattern to form a second conductive layer having a sidewall shape to be in contact with the first conductive layer, and removing the pattern; Forming a photosensitive foil exposing the storage electrode on the insulating film and deforming the surface of the storage electrode into a saw blade shape by sputtering; Removing the photosensitive film, forming a dielectric film on the storage electrode, and forming a plate electrode on the dielectric film. The method according to claim 1, A method for manufacturing a capacitor, wherein the pattern is formed of an insulating material such as BPSG (Boro Phospho Silicate Glass) or PSG (Phospho Silicate Glass). The process of claim 1, wherein the forming of the second conductive layer is performed. Depositing polycrystalline silicon doped with impurities on the insulating film to cover the surface of the first conductive layer and the pattern by a vapor phase vapor deposition method; And etching back the polysilicon doped with the impurities to expose the surface of the insulating film and the pattern.