KR100189726B1 - Capacitor of semiconductor device and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor device and a method of manufacturing the same. A first conductive type having a gate electrode formed thereon and a diffusion region used as a source or drain region formed by doping a high concentration of impurities of a second conductivity type in a predetermined portion. An insulating film having a semiconductor substrate, a contact hole formed on said semiconductor substrate, said contact hole exposing said diffusion region, and being formed in contact with said diffusion region inside said contact hole and extending a predetermined portion in a lateral direction outside said contact hole. A first conductive layer, a second conductive layer extending in a longitudinal direction on a side surface of the first conductive layer, and formed to be in partial contact with a lower surface of the first conductive layer, and formed on surfaces of the first and second conductive layers And a third conductive layer formed on the surface of the dielectric film. Therefore, the adhesion between the first polycrystalline silicon layer constituting the lower electrode of the storage electrode and the second polycrystalline silicon layer constituting the upper electrode is improved by the adhesion of the first polycrystalline silicon layer due to the movement of the second polycrystalline silicon layer in a subsequent process. This defect and separation can be prevented to improve the reliability of the device.

Description

Capacitor of Semiconductor Device and Manufacturing Method Thereof

1 is a cross-sectional view of a capacitor according to the present invention.

2a to d is a manufacturing process of the capacitor according to the first embodiment of the present invention.

3a to d is a manufacturing process diagram of a capacitor according to a second embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11: semiconductor substrate 13: diffusion region

15: insulating layer 17: contact hole

19: first polycrystalline silicon 21: pattern layer

23: second polysilicon 25: dielectric film

27: third polysilicon 29: sacrificial layer

31: space

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor device and a manufacturing method thereof, and more particularly to a capacitor of a semiconductor device having a large capacitance and high reliability and a method of manufacturing the same.

Many studies have been conducted to increase the storage density so that the capacitor has a constant storage capacity even if the cell area is reduced due to the high integration of the semiconductor device. In order to increase the storage density, the capacitor is formed into a three-dimensional structure of a stacked or trench to increase the area of the dielectric material, or the dielectric material is made of a high dielectric material such as tantalum oxide (Ta ₂ O ₅ ). There is a way to form.

The multilayer capacitor is a structure that is easy to manufacture and is approximately suitable for production, increasing the storage capacity and being immune to the disturbance of charge information caused by alpha particles.

A method for manufacturing a capacitor having a conventional stack structure is disclosed in US Patent No. 5,219,780 (Method for fabricating a semicond uctor memory cell), which is registered with the U.S. Patent Office.

The conventional method of manufacturing a capacitor includes a first polycrystalline silicon layer forming a lower electrode connected to a source or drain electrode of a switching or pass transistor, and an upper electrode installed in a cylindrical shape to increase a storage area. The second polysilicon layer is etched back without using a photoresist mask to form a storage electrode. Therefore, the process is simplified because the first and second polysilicon layers are self-aligned to each other when forming the storage electrode.

However, since the second polysilicon layer contacts only the end face of the first polysilicon layer, the adhesion force is reduced by a small contact area, and the second polysilicon layer moves during the subsequent process such as cleaning, so that the adhesion with the first polysilicon layer is poor. There was a problem that was made or separated.

Accordingly, an object of the present invention is to increase the adhesion area between the first polycrystalline silicon layer of the lower electrode constituting the storage electrode and the second polycrystalline silicon layer constituting the cylinder to form the upper electrode, thereby improving the adhesion of the semiconductor device capacitor. In providing.

Another object of the present invention is to manufacture a capacitor of a semiconductor device which can prevent the adhesion of the first polycrystalline silicon layer of the lower electrode and the separation of the lower electrode due to the movement of the second polycrystalline silicon layer constituting the upper electrode in a subsequent process In providing a method.

In the capacitor of the semiconductor device according to the present invention for achieving the above object, a first conductive electrode having a gate electrode formed thereon and a diffusion region used as a source or drain region formed by doping a high concentration of impurities of a second conductivity type in a predetermined portion thereof. An insulating film having a semiconductor substrate, a contact hole formed on the semiconductor substrate and exposing the diffusion region, and contacting the diffusion region inside the contact hole and extending a predetermined portion in a transverse direction from the outside of the contact hole. A first conductive layer, a second conductive layer extending in a longitudinal direction on a side surface of the first conductive layer, and formed to be in partial contact with a lower surface of the first conductive layer, and on the surfaces of the first and second conductive layers. And a third conductive layer formed on the surface of the dielectric film.

According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device according to the present invention. Forming an insulating layer having a contact hole exposing the diffusion region thereon, and sequentially depositing a first conductive layer and a pattern layer having an etch selectivity with the insulating layer on the insulating layer including the inside of the contact hole; And etching the insulating layer by a predetermined thickness such that the lower portion of the first conductive layer is undercut by using the pattern layer as a mask, and filling the undercut portion under the first conductive layer. Forming a second conductive layer on side surfaces of the first conductive layer and the pattern layer, forming a dielectric film on the surfaces of the first and second conductive layers, and forming a third conductive layer on the surface of the dielectric film. A comprises a step of forming.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a capacitor according to the present invention.

The capacitor according to the present invention is diffused on a P-type semiconductor substrate 11 having a diffusion region 13 and a gate electrode (not shown) which are heavily doped with N-type impurities and used as a source or drain region. An insulating layer 15 having a contact hole 17 exposing the region 13 is formed. The insulating layer 15 is formed of an insulating material such as silicon oxide, and the remaining portions except for a predetermined portion around the contact hole 17 are etched to a depth of about 1000 to 2000 kPa. In addition, a first polysilicon layer 19 doped with impurities used as a lower electrode of the storage electrode is formed on the insulating layer 15 including the inside of the contact hole 17. The first polysilicon layer 19 is in contact with the diffusion region 13 inside the contact hole 17 and extends in the transverse direction to contact the insulating layer 15 outside the contact hole 17. The first polysilicon layer 19 has a thickness of about 1000 to 1500 kPa, and the insulating layer 15 has a depth of about 1000 to 2000 kPa so that a predetermined portion of the lower surface is exposed to the outside of the contact hole 17. It is formed to be undercut.

The second polysilicon layer 23 doped with impurities used as the upper electrode of the storage electrode is formed on the side surface of the first polysilicon layer 19 so that a predetermined portion of the lower portion contacts. The second polysilicon layer 23 has a thickness of about 1000 to 15001, and the insulating layer 15 fills the undercut portion to be in contact with the exposed portion under the first polysilicon layer 19 to be electrically connected. do. The first and second polysilicon layers 19 and 23 become storage electrodes.

The dielectric film 25 is formed on the first and second polysilicon layers 19 and 23, that is, on the surface of the storage electrode. The dielectric layer 25 is formed of a high dielectric material such as silicon oxide, silicon oxide / silicon nitride / silicon oxide (Oxide / Nitride / Oxide), or tantalum oxide (Ta ₂ O ₅ ) to have a thickness of about 50 to 100 kPa. do. A third polysilicon layer 27 doped with an impurity used as a plate electrode on the surface of the dielectric layer 25 is formed to a thickness of about 1000 to 1500 Å.

In addition, according to the present invention, the undercut portion may extend to the contact hole 17 so that the first polysilicon layer 19 may expose all of the lower surfaces of the first polysilicon layer 19 formed in addition to the contact hole 17. In this case, since the second polysilicon layer 23 is in contact with the entire exposed lower surface of the first polysilicon layer 19, the adhesion force between the first polycrystalline silicon layer 19 and the second polysilicon layer 23 This is further increased.

2a to d is a manufacturing process diagram of a capacitor according to a first embodiment of the present invention.

Referring to FIG. 2A, a gate electrode (not shown) is formed on a predetermined portion, and a diffusion region 13 used as a source or drain region is doped with N-type impurities at a high concentration under the gate electrode side. The insulating layer 15 is formed on the P-type semiconductor substrate 11 having an insulating material such as silicon oxide by chemical vapor deposition (hereinafter, referred to as CVD). Then, the contact hole 17 is formed by removing a predetermined portion of the insulating layer 15 so that the diffusion region 13 is exposed by photolithography.

Referring to FIG. 2B, a low pressure chemical vapor deposition of the first polycrystalline silicon layer 19 doped with impurities on the insulating layer 15 including the inner surface of the contact hole 17 is described below. And LPCVD) to deposit a thickness of about 1000 to 1500 mW. On the first polysilicon layer 19, impurities such as silicon nitride having an etch selectivity with respect to the silicon oxide forming the insulating film 15, phosphosilicate glass (PSG), or boro-phosphosilicate glass (BPSG), etc. The dope oxide is deposited to a thickness of about 3000 to 5000 kPa by chemical vapor deposition (hereinafter, referred to as CVD) to form a pattern layer 21. The pattern layer 21 and the first polysilicon layer 19 are sequentially patterned by photolithography to define the lower electrode of the storage electrode. Next, using the pattern layer 21 and the first polysilicon layer 19 as a mask, the insulating film 15 is about 1000 to 2000Å thick by wet etching with an etching solution containing hydrofluoric acid (HF) or by a chemical dry etching method. Etch it. At this time, the bottom portion of the first polysilicon layer 19 is undercut to a depth of about 1000 to 2000 micrometers.

Referring to FIG. 2C, the second polycrystalline silicon layer 23 doped with impurities by the LPCVD method is formed on the entire surface of the above-described structure to a thickness of about 1000 to 1500 mW. At this time, the second polysilicon layer 23 is in contact with the exposed portion of the undercut portion of the lower portion of the first polysilicon layer 19 is buried. The second polysilicon layer 23 is etched back using a method such as reactive ion etching to expose the insulating layer 15 and the pattern layer 21. Therefore, the second polysilicon layer 23 remains only on the lower surface of the first polysilicon layer 19 on the side and undercut portions of the first polysilicon layer 19 and the pattern layer 21, which is a storage electrode. Becomes the upper electrode of. In the above, the first and second polysilicon layers 19 and 23 become storage electrodes.

Referring to FIG. 2D, the pattern layer 21 is selectively etched and removed. The dielectric film 25 is formed on the first and second polysilicon layers 19 and 23, that is, on the surface of the storage electrode. The dielectric layer 25 is made of a high dielectric material such as silicon oxide, silicon oxide / silicon nitride / silicon oxide (Oxide / Nitride / Oxide), or tantalum oxide (Ta ₂ O ₅ ) so as to have a thickness of about 50 to 100Å. Is formed. Then, the third polycrystalline silicon layer 27 doped with impurities used as the plate electrode on the surface of the dielectric film 25 by the LPCVD method is formed to a thickness of about 1000 to 1500 Å.

3A to 3D are manufacturing process diagrams of a capacitor according to a second embodiment of the present invention.

Referring to FIG. 3A, a gate electrode (not shown) is formed on a predetermined portion, and a diffusion region 13 used as a source or drain region is doped with N-type impurities at a high concentration under the gate electrode side. An insulating material, such as silicon oxide, is deposited on the P-type semiconductor substrate 11 with a chemical vapor deposition (hereinafter, referred to as CVD) method to form an insulating layer 15. The sacrificial layer 29 is formed on the insulating layer 15 by depositing silicon nitride having a different etching selectivity from silicon oxide constituting the insulating layer 15 to a thickness of about 1000 to 1500 mW by the CVD method. Then, the contact hole 17 is formed by successively removing a predetermined portion of the sacrificial layer 29 and the insulating layer 15 so that the diffusion region 13 is exposed by photolithography.

Referring to FIG. 3B, the first polycrystalline silicon layer 19 doped with impurities on the sacrificial layer 29 including the inner surface of the contact hole 17 is deposited to have a thickness of about 1000 to 1500 kPa by the LPCVD method. . In addition, PSG (Bhosphour Silicate Glass) or BPSG (Boro-Phosphour Silicate Glass) having an etch selectivity with respect to the silicon oxide forming the insulating film 15 and the silicon nitride forming the sacrificial layer 29 on the first polycrystalline silicon layer 19. An oxide doped with an impurity such as) is deposited by a CVD method to a thickness of about 3000 to 5000 Å to form the pattern layer 21. The pattern layer 21 and the first polysilicon layer 19 are sequentially patterned by photolithography to define the lower electrode of the storage electrode. Next, the sacrificial layer 29 is removed by wet etching using a etching solution containing phosphoric acid (H ₃ PO ₄ ) or by etching by chemical dry etching to the contact hole 17 below the first polycrystalline silicon layer 19. An extending space 31 is formed. In this case, the insulating layer 15 and the pattern layer 21 are not removed because the etching selectivity is different from that of the sacrificial layer 29.

Referring to FIG. 3C, the second polycrystalline silicon layer 23 doped with impurities by the LPCVD method is formed on the entire surface of the above-described structure to a thickness of about 1000 to 1500 mW. At this time, the second polysilicon layer 23 fills the space 31 and contacts the lower surface of the first polysilicon layer 19, thereby increasing adhesion. The second polysilicon layer 23 is etched back using a method such as reactive ion etching to expose the insulating layer 15 and the pattern layer 21. Therefore, the second polysilicon layer 23 remains only on the lower surface of the first polysilicon layer 19 on the side and undercut portions of the first polysilicon layer 19 and the pattern layer 21, which is a storage electrode. Becomes the upper electrode of. In the above, the first and second polysilicon layers 19 and 23 become storage electrodes.

Referring to FIG. 3D, the pattern layer 21 is selectively etched and removed. The first and second polysilicon layers 19 and 23 form the dielectric film 25 on the surface of the storage electrode. The dielectric layer 25 is made of a high dielectric material such as silicon oxide, silicon oxide / silicon nitride / silicon oxide (Oxide / Nitride / Oxide), or tantalum oxide (Ta ₂ O ₅ ) to have a thickness of about 50 to 100Å. Is formed. A third polysilicon layer 27 doped with impurities used as a plate electrode by the LPCVD method is formed on the surface of the dielectric film 25 to a thickness of about 1000 to 1500 Å.

As described above, the present invention exposes the lower portion of the first polycrystalline silicon layer forming the lower electrode of the storage electrode of the capacitor connected to the diffusion region used as the source or drain region of the transistor by forming an undercut or a space, Since the second polysilicon layer is formed to undercut or fill the space, the contact area between the first polysilicon layer and the second polysilicon layer is increased to improve adhesion.

Accordingly, the present invention provides a method of improving adhesion between the first polycrystalline silicon layer forming the lower electrode of the storage electrode and the second polycrystalline silicon layer forming the upper electrode, thereby increasing the first polycrystalline silicon due to the movement of the second polycrystalline silicon layer in a subsequent process. The layer and adhesion can be prevented from defects and separation to improve the reliability of the device.

Claims (12)

A first conductive semiconductor substrate having a gate electrode formed thereon and a diffusion region used as a source or a drain region formed by doping a high concentration of impurities of a second conductivity type in a predetermined portion, and formed on the semiconductor substrate; An insulating film having a contact hole exposing a region, a first conductive layer formed to be in contact with the diffusion region inside the contact hole and to extend a predetermined portion in a transverse direction from the outside of the contact hole, and to a side surface of the first conductive layer. The second conductive layer extending in the direction and formed to be in contact with the lower surface of the first conductive layer at a predetermined portion, the dielectric film formed on the surfaces of the first and second conductive layers, and the third conductive layer formed on the surface of the dielectric film. A capacitor of a semiconductor device provided. The capacitor of claim 1, wherein the insulating layer is isotropically etched undercut so that the insulating layer does not come into contact with a predetermined portion of the end of the first conductive layer extending outside the contact hole. 3. The capacitor of claim 2, wherein the insulating layer is undercut to a depth of 1000 to 2000 microseconds. The capacitor of claim 1, wherein the upper surface of the insulating layer is not in contact with a portion extending outward of the contact hole of the first conductive layer. Forming a insulating layer having a contact hole exposing the diffusion region on a semiconductor substrate, wherein the first conductivity type having a gate electrode formed on a predetermined portion and having a diffusion region of a second conductivity type formed under the side of the gate electrode; And sequentially depositing and patterning a first conductive layer and a pattern layer having an etch selectivity with the insulating layer, including an inside of the contact hole, and using the pattern layer as a mask. Etching the insulating layer by a predetermined thickness such that a lower portion of the undercut is undercut, forming a second conductive layer on side surfaces of the first conductive layer and the pattern layer to fill the undercut portion under the first conductive layer, and And forming a dielectric film on the surfaces of the first and second conductive layers, and forming a third conductive layer on the surface of the dielectric film. The method of claim 5, wherein the pattern layer is formed of silicon nitride, phosphorus silicate glass (PSG), or boro-phosphosilicate glass (BPSG). The method of claim 5, wherein the insulating layer is etched isotropically. The method of manufacturing a capacitor of a semiconductor device according to claim 7, wherein the insulating layer is etched in a thickness of 1000 to 2000 microns. An insulating layer and a sacrificial layer having a contact hole for exposing the diffusion region are formed on the first conductive semiconductor substrate having a gate electrode formed on a predetermined portion and a diffusion region of the second conductivity type formed under the side of the gate electrode. And sequentially depositing and patterning a first conductive layer and a pattern layer having an etch selectivity with the insulating layer, including the inside of the contact hole, and removing the sacrificial layer. Forming a space exposing the lower surface of the layer, forming a second conductive layer on side surfaces of the first conductive layer and the pattern layer to fill the space under the first conductive layer, and the first and second 2. A method of manufacturing a capacitor of a semiconductor device, comprising: forming a dielectric film on the surface of the conductive layer; and forming a third conductive layer on the surface of the dielectric film. 10. The method of claim 9, wherein the sacrificial layer is formed of silicon nitride. The method of manufacturing a capacitor of a semiconductor device according to claim 10, wherein the sacrificial layer is formed to a thickness of 1000 to 1500 Å. The method of claim 9, wherein the pattern layer is formed of PSG (Phosphour Silicate Glass) or BPSG (Boro-Phosphour Silicate Glass).