KR20000046743A - Method of manufacturing capacitor of semiconductor device - Google Patents

Abstract

PURPOSE: A method of manufacturing a capacitor is to increase a capacitance per unit surface area of the capacitor by interposing a dielectric film between upper and lower electrodes of the capacitor. CONSTITUTION: An oxide film(22) is formed on a silicone substrate(20) of a P-typed semiconductor, and a portion of the oxide film is removed by a photolithography method to form a contact hole exposing a portion of a surface of an impurity diffusion region(21) formed on the substrate. The oxide film is deposited with a first polycrystalline silicon layer by a chemical vapor deposition method, and is treated by a chemical mechanical deposition method to form a contact plug(23). A doped polycrystalline layer(24) is deposited on the oxide film to form a first lower electrode layer. A first dielectric film(25) is deposited on the first lower electrode layer. A first upper electrode layer(26) is formed on the first dielectric film.

Description

Capacitor Manufacturing Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device. In particular, the lower electrode layer and the upper electrode layer are alternately stacked and interposed therebetween so as to form a lower electrode and an upper electrode of the capacitor so as to be mutually interposed therebetween. By interposing a dielectric film and then patterning to properly insulate the exposed areas, and then to connect the lower electrode and the upper electrode to separate conductive layers, the capacitor is formed to maximize the surface area of the lower electrode of the capacitor. A method of manufacturing a stacked capacitor of a semiconductor device to increase the capacitance.

Many studies have been conducted to increase the storage density so that the capacitor has a constant storage capacity even if the cell area is reduced due to the high integration of the semiconductor device. To increase the capacitance, capacitors were formed in a three-dimensional structure, stacked or trenched, to increase the surface area of the dielectric.

Among the capacitors having the three-dimensional structure, the laminated structure has an easy manufacturing process and is suitable for mass production, increasing the storage capacity and being immune to the disturbance of charge information caused by alpha particles. Stacked capacitors are classified into a double stacked layer structure, a fin structure, or a crown structure according to storage electrodes.

In the buried DRAM manufacturing process, to form a capacitor in a cell part, a transistor or the like is formed on a semiconductor substrate, and then a plurality of polysilicon layers are patterned to form a lower electrode, a dielectric film and an upper electrode to form a capacitor, and then an electrical connection between the devices. In order to perform the metal wiring process.

1 is a cross-sectional view of a capacitor of a semiconductor device manufactured according to the prior art.

Referring to FIG. 1, an impurity region 11 is formed on the P-type semiconductor substrate 10 to be heavily doped with N-type impurities such as an asic (As) or phosphorus (P) to serve as a source and a drain region. It is. Then, an insulating film 12 is placed on the semiconductor substrate as an interlayer insulating film, and there is a contact hole formed by removing a predetermined portion of the insulating film 12 by photolithography. The first polycrystalline silicon layer 13 doped with an impurity in a chemical vapor deposition (hereinafter referred to as CVD) method, and then etched back or CMP onto the first polycrystalline silicon layer 13. There is a contact plug 13 formed by carrying out the process.

The lower electrode 14, which is a fin-type storage electrode 14, is formed at a predetermined portion of the insulating layer 12 including the upper surface of the contact plug 13. The lower electrode is formed by depositing a polysilicon layer, an insulating layer, and the like for forming a storage electrode on the insulating layer 13 and patterning the same.

However, in order to connect the upper pin and the lower pin, it is necessary to form a hole therebetween to form a plug in the center portion.

There is a dielectric film 15 formed on the surface of the storage electrode 14, and a plate electrode 16, which is an upper electrode 16 for completing the capacitor in correspondence with the lower electrode, is formed on the dielectric film 15.

Capacitors of this structure are manufactured in the following manner.

First, an interlayer insulating film is formed on a P-type semiconductor substrate 10 on which an impurity region 11 used as a source and a drain region is formed by doping N-type impurities such as an asce (As) or phosphorus (P) at a high concentration. The insulating film 12 is formed.

Then, a predetermined portion of the insulating film 12 is removed by photolithography to form contact holes, and then the first polycrystalline silicon layer doped with impurities on the insulating film 12 to sufficiently fill the contact holes ( 13) is deposited by chemical vapor deposition (hereinafter referred to as CVD) method, and then subjected to an etch back or CMP process on the first polysilicon layer 13 to obtain a contact plug, 13).

The lower electrode 14, which is a fin-type storage electrode 14, is formed on a predetermined portion of the insulating layer 12 including the upper surface of the contact plug 13. The lower electrode is formed by depositing a polysilicon layer for forming a storage electrode, a buffer layer, and the like on the insulating layer 13, and then forming a plug with a conductive material on the buffer layer to electrically connect the polysilicon layers formed on different layers. It is formed by patterning.

However, the capacitor manufacturing method according to the conventional technology described above is difficult to secure the capacitance because the DRAM is increasingly integrated and the line width decreases, making it difficult to secure the margin of the cell pattern, and the height of the capacitor is increased to secure the capacitance. Steps to increase the ferri portion, and also, the pin structure is separated during the etching for forming the fin structure has a problem that the yield is reduced.

Accordingly, an object of the present invention is to alternately stack the lower electrode layer and the upper electrode layer, and to interpose the dielectric layer therebetween in order to form the lower electrode and the upper electrode of the capacitor so that the dielectric layer is interposed therebetween, and then patterning the exposed electrode. The semiconductor is designed to increase the capacitance of the capacitor per unit cell area by maximizing the surface area of the lower electrode by maximizing the surface area of the capacitor by forming a capacitor by appropriately insulating the parts and then connecting the lower electrode and the upper electrode to separate conductive layers. It is to provide a method of manufacturing a stacked capacitor of the device.

For the above-mentioned object, a method of manufacturing a capacitor of a semiconductor device according to the present invention includes a first lower electrode layer / first dielectric layer / first upper electrode layer on a semiconductor substrate having an interlayer insulating layer formed thereon and a conductive plug formed on a predetermined portion of the interlayer insulating layer. Forming a stack by sequentially forming a second dielectric layer, forming a second lower electrode layer on the second dielectric layer, removing the second lower electrode layer and a predetermined portion of the stack, and Forming a lamination pattern exposing one side of the lamination, first insulating the exposed surface of the lamination pattern having the one end surface and the upper surface exposed to a predetermined thickness, and the second lower portion Removing the first insulated portion of the electrode layer and the first lower electrode layer; Forming a pole layer, forming a third dielectric layer on the exposed surface of the third lower electrode layer and the exposed surface of the laminated pattern, forming a second upper electrode layer on the third dielectric layer, and Exposing the other side surface of the stack pattern by removing a second upper electrode layer, the third dielectric layer, and a predetermined portion of the stack pattern, and the other side of the exposed stack pattern and the surface of the exposed second top electrode layer Second insulating to a predetermined thickness, removing second insulated portions of the second to first upper electrodes, and forming a second insulating layer on the remaining surface of the stacked pattern including the second upper electrode layer. And forming an upper electrode layer.

1 is a cross-sectional view of a capacitor of a semiconductor device manufactured according to the prior art.

2A to 2F are cross-sectional views of a capacitor manufacturing process of a semiconductor device according to the present invention.

A capacitor is a device that stores or emits electric charges through a dielectric between two electrodes. The capacitance of such a device is proportional to the dielectric constant and the cross-sectional area and inversely proportional to the distance between the two electrodes. Therefore, in order to increase the capacitance, use a dielectric having a large dielectric constant or reduce the gap between two electrodes. However, the most commonly used method is to increase the corresponding area with two electrodes sandwiching the dielectric film.

Therefore, in the present invention, the lower electrode and the upper electrode are formed in the form of interlocking with each other by a method of increasing the area of the electrode, and the dielectric film is interposed therebetween. In this way, the upper and lower electrodes may be formed in plural forms in accordance with the required capacitance.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views of a capacitor manufacturing process of a semiconductor device according to the present invention.

Referring to FIG. 2A, a silicon substrate which is a P-type semiconductor substrate on which an impurity region 21 used as a source and a drain region is formed by doping N-type impurities such as an asic (As) or phosphorus (P) at a high concentration. An oxide film 22 is formed on the 20 as an interlayer insulating layer.

A predetermined portion of the interlayer insulating layer 22 is removed by photolithography to form a contact hole for exposing a part of the surface of the impurity diffusion region 21.

Then, after depositing the first polycrystalline silicon layer doped with impurities on the interlayer insulating layer 22 by the chemical vapor deposition (hereinafter referred to as CVD) method to sufficiently fill the contact hole, the first polycrystalline silicon layer An etch back or CMP process is performed to form a contact plug 23. In this case, the interlayer insulating layer 23 is used as the etch stop layer.

The first lower electrode layer 24 for forming the first panel of the lower electrode is formed by using a conductive material capable of forming an insulating film on the interlayer insulating film 22 including the upper surface of the contact plug 23 by oxidation or nitriding. The polysilicon layer 24 doped with impurities is deposited by CVD.

Next, a nitride film or a first dielectric film 25 having a high dielectric constant such as Ta ₂ O ₅ , BST, PZT, Ta ₂ O ₅ , Y ₃ O ₃ , ZrO ₂ , Nb ₂ O ₂ , or the like on the first lower electrode layer 24. E).

The first upper electrode layer 26 is formed of a conductive material capable of forming an insulating film on the first dielectric layer 25 by an oxidation process or a nitriding process. In this case, the first upper electrode layer 26 and the first lower electrode layer 24 formed are formed through oxidation or nitriding, but each insulating material has a different etching rate.

In this manner, the second dielectric layer 27, the second lower electrode layer 28, the third dielectric layer 29, the second upper electrode layer 30, and the fourth dielectric layer 31 are formed on the first upper electrode layer 26. The third lower electrode layers 32 are sequentially stacked. At this time, the third lower electrode layer 32 finally formed is deposited thickly in consideration of the thickness of the insulating layer formed through oxidation or nitriding to form a stacked pattern.

In addition, the number of stacked layers of the capacitor manufactured according to the present invention allows the lower electrode layer to be formed one more layer than the upper electrode layer to secure the necessary capacitance. In this case, the lower electrode layer formed on the uppermost layer is advantageously formed thicker than the underlying layer as described above.

Referring to FIG. 2B, after the photoresist is applied on the third lower electrode layer, which is the uppermost layer, exposure and development are performed on the photoresist to expose two adjacent sides of the pattern when the stacked pattern of the capacitor to be formed is a square pillar. A photoresist pattern (not shown) is formed.

And the third lower electrode layer / fourth dielectric film / second upper electrode layer / third dielectric film / second lower electrode layer / second dielectric film / first upper electrode layer / first dielectric film / first lower portion of the portion not protected by the photoresist pattern. The third lower electrode layer 320, the fourth dielectric layer 310, the second upper electrode layer 300, the third dielectric layer 290, the second lower electrode layer 280, and the second dielectric layer 270 that remain by sequentially removing the electrode layers ) The first stacked pattern in which only half of the stacked patterns to be formed by forming the first upper electrode layer 260 / the first dielectric layer 250 / the first lower electrode layer 240 is formed. Then, the photoresist pattern is removed.

The first oxide layer 321 is exposed on the exposed surface of the third lower electrode layer 320 by oxidizing the exposed first stacked pattern, the second oxide layer 301 is disposed on the side surface of the exposed second upper electrode layer 300. The third oxide film 281 is disposed on the exposed side surface of the second lower electrode layer 280, the fourth oxide film 261 is disposed on the side surface of the exposed first upper electrode layer 260, and the side surface of the exposed first lower electrode layer 240 is formed. A fifth oxide film 241 is formed in the trench.

In this case, the second and fourth oxide films 301 and 261 have etching rates different from those of the remaining first, third and fifth oxide films 321, 281 and 241.

Referring to FIG. 2C, first, third and fifth oxide films 321, 281 and 241 are removed by wet etching the exposed first stacked patterns. Accordingly, the side surfaces of one side of the remaining first to third lower electrode layers 320, 280 and 240 are exposed again.

Next, in order to electrically connect the remaining first to third lower electrode layers 320, 280 and 240 to each other, the same material as the lower electrode layer forming material is deposited on the entire surface of the substrate including the first stacked pattern. The fourth lower electrode layer 33 having a sidewall shape is formed on the side surface of the exposed first stacked pattern wet and etched back.

In addition, a fifth dielectric layer 34 is formed on the entire surface of the substrate including the exposed surface of the fourth lower electrode layer 33, and then, on the 34, the third upper electrode layer is made of the same material as the upper electrode forming material. 35 is formed by vapor deposition.

Referring to FIG. 2D, the photoresist is applied to the entire surface of the substrate including the third upper electrode layer 35, and then exposure and development are performed to pattern the remaining two sides of the first stacked pattern including the third upper electrode layer. A photoresist pattern (not shown) is formed.

And the third upper electrode layer / fifth dielectric film / third lower electrode layer / fourth dielectric film / second upper electrode layer / third dielectric film / second lower electrode layer / second dielectric film / first upper electrode layer of the portion not protected by the photoresist pattern. The third upper electrode layer 350, the fifth dielectric layer 340, the third lower electrode layer 321, the fourth dielectric layer 311, and the second upper electrode layer 302) / third dielectric film 291 / second lower electrode layer 281 / second dielectric film 271 / first upper electrode layer 262 / first dielectric film 251 / first lower electrode layer 241 Expose In this case, the remaining first pattern includes the third upper electrode layer 350 to form a pillar pattern having a pillar shape.

Then, an oxidation process is performed on the exposed pillar pattern surface to form sixth to eleventh oxide films 351, 322, 303, 282, 263 and 241 on exposed portions of the pillar pattern. In this case, the etch rates of the sixth, eighth, and tenth oxide films 351, 303, and 263 differ from the seventh, ninth, and eleventh oxide films. That is, the etching selectivity is formed to be large.

Referring to FIG. 2E, the sixth, eighth, and tenth oxide layers 351, 303, and 263 are wet-etched to remove the upper surface and side surfaces of the third upper electrode layer 350 and the second upper electrode layer 302. And a side surface of the first upper electrode layer 262.

Referring to FIG. 2F, the fourth upper electrode layer may be formed on the front surface of the substrate including the upper surface and side surfaces of the exposed third upper electrode layer 350 and the side surfaces of the second upper electrode layer 302 and the first upper electrode layer 262. 36) to complete the capacitor.

The internal structure of the capacitor formed as described above has an upper electrode and a lower electrode engaged with each other, and a dielectric film is interposed therebetween, and has a stacked capacitor structure having various pillar shapes such as a cylinder or a square pillar.

Therefore, the capacitor manufacturing method of the semiconductor device according to the present invention performs only two photolithography processes for forming the electrode, so that it is easy to define the shape of the electrode, and the capacitance of the capacitor per unit cell area is maximized by maximizing the surface area of the lower electrode of the capacitor. In order to increase the yield, the electrodes are firmly connected to each other to have a solid structure.

Claims (5)

Forming a stack by sequentially forming a first lower electrode layer / first dielectric film / first upper electrode layer / second dielectric film on a semiconductor substrate having an interlayer insulating layer formed thereon and a conductive plug formed on a predetermined portion of the interlayer insulating layer; Forming a second lower electrode layer on the second dielectric layer; Removing the second lower electrode layer and a predetermined portion of the stack to form a stack pattern exposing the second lower electrode layer and one side of the stack; First insulating the exposed surface of the lamination pattern having the one side surface and the upper surface exposed to have a predetermined thickness; Removing the first insulated portions of the second lower electrode layer and the first lower electrode layer; Forming a third lower electrode layer having a sidewall on an exposed side surface of the remaining stacked pattern; Forming a third dielectric layer on the exposed surface of the third lower electrode layer and the exposed surface of the stacked pattern; Forming a second upper electrode layer on the third dielectric layer; Removing the second upper electrode layer, the third dielectric layer, and predetermined portions of the stacked pattern to expose the other side surface of the stacked pattern; Insulating the other side of the exposed laminated pattern and the surface of the exposed second upper electrode layer to a second thickness with a predetermined thickness; Removing second insulated portions of the second to first upper electrodes; And forming a third upper electrode layer on a surface of the stacked pattern including the second upper electrode layer. The semiconductor of claim 1, wherein the first to third lower electrode layers and the first to second upper electrode layers are each formed of a material such that the first to second insulated portions have a large etching selectivity. Method of manufacturing the device. The method of manufacturing a capacitor of a semiconductor device according to claim 1, further comprising the step of forming a plurality of said stacks in a vertical direction. The method of claim 1, wherein the first to second insulation are performed by an oxidation or nitriding process. The method of manufacturing a capacitor of claim 4, wherein the stacked pattern in which the other side is removed is in the form of a square pillar or a circular pillar.