KR19980057023A - Gate electrode formation method of semiconductor device - Google Patents
Gate electrode formation method of semiconductor device Download PDFInfo
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- KR19980057023A KR19980057023A KR1019960076293A KR19960076293A KR19980057023A KR 19980057023 A KR19980057023 A KR 19980057023A KR 1019960076293 A KR1019960076293 A KR 1019960076293A KR 19960076293 A KR19960076293 A KR 19960076293A KR 19980057023 A KR19980057023 A KR 19980057023A
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 229920005591 polysilicon Polymers 0.000 claims abstract description 32
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 238000004140 cleaning Methods 0.000 claims abstract description 5
- 239000007789 gas Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 239000007790 solid phase Substances 0.000 claims description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 239000011259 mixed solution Substances 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 239000013078 crystal Substances 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 3
- 239000007787 solid Substances 0.000 abstract description 3
- 238000002513 implantation Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract 2
- 230000000368 destabilizing effect Effects 0.000 abstract 1
- 230000005669 field effect Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 장치 제조방법Semiconductor device manufacturing method
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
종래에는 폴리 실리콘막과 게이트 산화막의 접촉 부위에서 게이트의 특성을 열화시키는 결함이 발생하여 문턱 전압을 불안정하게 하며, 또한, 폴리 실리콘막의 높은 저항값으로 인하여 소자의 특성 및 이후 공정의 복잡화를 초래하며, 저항값을 낮추기 위해 고농도의 불순물 이온주입 후 실시하는 열공정시 발생하는 P2O5막을 제거하기 위하여 별도의 세정 공정을 필요로 하는 문제점이 있었음.Conventionally, a defect that deteriorates the characteristics of the gate occurs at a contact point between the polysilicon film and the gate oxide film, thereby destabilizing the threshold voltage. Also, the high resistance value of the polysilicon film causes complexity of device characteristics and subsequent processes. In addition, there was a problem that a separate cleaning process was required to remove the P 2 O 5 film generated during the thermal process performed after the implantation of high concentration of impurity ions to lower the resistance value.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
본 발명은 Si2H6가스를 사용하여 게이트 산화막 상부에 저온 증착된 폴리 실리콘막을 고상 성장 방식으로 성장시킴으로써 결정 입자의 크기를 크게 형성함으로써 폴리 실리콘막의 저항을 낮추고, 공정을 단순화하는 반도체 장치의 게이트 전극 형성방법을 제공하고자 함.The present invention provides a semiconductor device gate which reduces the resistance of the polysilicon film and simplifies the process by forming a large crystal grain by growing a low-temperature deposited polysilicon film on the gate oxide layer using a solid state growth method using Si 2 H 6 gas. To provide a method of forming an electrode.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 장치의 전계 효과 트랜지스터 제조에 이용됨.Used to manufacture field effect transistors in semiconductor devices.
Description
본 발명은 반도체 장치의 게이트 전극 형성방법에 관한 것이다.The present invention relates to a method for forming a gate electrode of a semiconductor device.
이하, 종래 기술 및 그 문제점을 살펴본다.Hereinafter, the prior art and its problems will be described.
우선, 종래의 게이트 전극 형성방법은 실리콘 기판 상부에 게이트 산화막을 형성하고, 그 상부에 폴리 실리콘막을 증착한 후, 불순물을 폴리 실리콘막 상에 이온주입을 실시한다.First, in the conventional gate electrode forming method, a gate oxide film is formed on a silicon substrate, a polysilicon film is deposited on the silicon oxide film, and impurities are ion implanted onto the polysilicon film.
계속하여, 전체구조 상부에 포토레지스트를 도포하고, 이를 패터닝하여 게이트 전극 형성을 위한 포토레지스트 패턴을 형성한다.Subsequently, a photoresist is applied over the entire structure and patterned to form a photoresist pattern for forming a gate electrode.
이어서, 프토레지스트 패턴을 식각 장벽으로하여 폴리 실리콘막 및 게이트 산화막을 차례로 선택적 식각하고, 포토레지스트 패턴을 제거한다.Subsequently, the polysilicon film and the gate oxide film are selectively etched sequentially, using the protoresist pattern as an etching barrier, and the photoresist pattern is removed.
상기와 같은 공정을 통해 형성된 종래의 게이트 전극은 폴리 실리콘막과 하부의 게이트 산화막의 접촉 부위에서 게이트의 특성을 열화시키는 결함이 발생하여 문턱 전압을 불안정하게 하며, 또한 폴리 실리콘막의 높은 저항값은 고집적 반도체 장치에서 금속 배선 형성을 필요로 할 뿐만 아니라, 많은 콘택의 수로 인하여 반도체 장치의 구조가 복잡해지고 있다.In the conventional gate electrode formed through the above process, a defect that deteriorates the characteristics of the gate occurs at the contact portion between the polysilicon film and the lower gate oxide film, thereby causing the threshold voltage to become unstable, and the high resistance value of the polysilicon film is highly integrated. In addition to the formation of metal wiring in the semiconductor device, the structure of the semiconductor device is complicated by the large number of contacts.
그리고, 게이트 저항을 낮추기 위해 고농도의 불순물 이온주입 후 열공정을 실시하게되는데 이때, 발생하는 P2O5막을 제거하기 위하여 별도의 세정 공정을 필요로 하는 문제점이 있었다.In addition, in order to lower the gate resistance, a thermal process is performed after the implantation of a high concentration of impurity ions. In this case, a separate cleaning process is required to remove the generated P 2 O 5 film.
본 발명은 Si2H6가스를 사용하여 게이트 산화막 상부에 저온 증착된 폴리 실리콘막을 고상 성장 방식으로 성장시킴으로써 결정 입자의 크기를 크게 형성함으로써 폴리 실리콘막의 저항을 낮추고, 공정을 단순화하는 반도체 장치의 게이트 전극 형성방법을 제공하는데 그 목적이 있다.The present invention provides a semiconductor device gate which reduces the resistance of the polysilicon film and simplifies the process by forming a large crystal grain by growing a low-temperature deposited polysilicon film on the gate oxide layer using a solid state growth method using Si 2 H 6 gas. The object is to provide a method for forming an electrode.
도 1a 내지 도 1c는 본 발명의 일실시예에 따른 반도체 장치의 게이트 전극 형성 공정 단면도.1A to 1C are cross-sectional views of a gate electrode forming process of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 실리콘 기판 11 : 게이트 산화막10 silicon substrate 11 gate oxide film
12 : 폴리 실리콘막 13 : 게이트 전극12 polysilicon film 13 gate electrode
상기와 같은 목적을 달성하기 위하여 반도체 기판 상부에 게이트 절연막을 형성하는 단계, Si2H6가스를 사용하여 저온 화학 기상 증착 방식으로 상기 게이트절연막 상부에 폴리 실리콘막을 형성하는 단계, 상기 폴리 실리콘막 상에 불순물을 이온주입하는 단계, 상기 폴리 실리콘막을 열처리하여 고상 성장시키는 단계 및 상기 게이트 전극 형성을 위한 마스크를 사용하여 상기 폴리 실리콘막 및 상기 게이트 절연막을 선택적 식각하는 단계를 포함하여 이루어진다.In order to achieve the above object, forming a gate insulating film on the semiconductor substrate, forming a polysilicon film on the gate insulating film using a low-temperature chemical vapor deposition method using a Si 2 H 6 gas, on the polysilicon film Implanting an impurity into the dopant, heat-treating the polysilicon layer to solidify growth, and selectively etching the polysilicon layer and the gate insulating layer using a mask for forming the gate electrode.
이하, 첨부된 도면 도 1a 및 도 1c를 참조하여 본 발명의 일실시예를 상술한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings, FIGS. 1A and 1C.
먼저, 도 1a에 도시된 바와 같이 실리콘 기판(10) 상부에 게이트 산화막(11)을 성장 시키고, 그 상부에 Si2H6가스를 사용하여 폴리 실리콘막(12)을 약 1000Å 내지 약 2000Å 두께로 형성한다. 이때, 약 430℃ 내지 470℃ 온도 범위에서 저온화학 기상 증착을 실시한다. 여기서, Si2H6가스를 사용하기 때문에 저온 증착이 가능하게 되며, 저온 증착에 의해 생성되는 핵의 수를 최소화할 수 있게 된다.First, as shown in FIG. 1A, the gate oxide film 11 is grown on the silicon substrate 10, and the polysilicon film 12 is about 1000 mW to about 2000 mW using Si 2 H 6 gas thereon. Form. At this time, the low temperature chemical vapor deposition is carried out in the temperature range of about 430 ℃ to 470 ℃. Here, since Si 2 H 6 gas is used, low temperature deposition is possible, and the number of nuclei generated by low temperature deposition can be minimized.
다음으로, 도 1b에 도시된 바와 같이 폴리 실리콘막(12) 상에 고농도의 인(P)을 이온주입한다. 이때, 이온주입 에너지는 약 40 내지 약 60keV, 불순물 농도는 약 1.0×1015내지 약 3.0×1015#/㎠로 하여 실시한다.Next, as shown in FIG. 1B, a high concentration of phosphorus (P) is ion-implanted on the polysilicon film 12. In this case, the ion implantation energy is about 40 to about 60 keV, and the impurity concentration is about 1.0 × 10 15 to about 3.0 × 10 15 # / cm 2.
계속하여, 폴리 실리콘막(12)의 고상 성장(solid phase groeth)을 위하여 N2가스 분위기에서 약 560℃ 내지 약 650℃ 온도 범위로 약 2시간 내지 약 5시간 정도 열처리를 실시한다. 이때, 성장되는 핵은 크게는 8.7㎛까지 자라게 되는데, 이러한 큰 크기의 결정 입자는 폴리 실리콘막의 저항값을 낮추게 된다. 왜냐하면 전하는 결정립계를 따라 흐르기 때문이다. 또한, 결정 입자의 크기가 작으면 결정입계에 결함이 쉽게 모여들고, 또 불순물 이온주입시 계면을 최소화하기 위해 결정입자의 크기가 클수록 유리하다.Subsequently, heat treatment is performed for about 2 hours to about 5 hours at a temperature range of about 560 ° C. to about 650 ° C. in a N 2 gas atmosphere for solid phase growth of the polysilicon film 12. At this time, the grown nucleus grows up to 8.7 μm, and such large crystal grains lower the resistance value of the polysilicon film. Because charge flows along grain boundaries. In addition, when the size of the crystal grains is small, defects easily gather at the grain boundaries, and the size of the crystal grains is advantageous in order to minimize the interface during impurity ion implantation.
이후, 세정 공정을 실시한다. 이때, 세정은 불산(HF), 과산화 수소(H2O2) 및 순수(deionized H2O)의 혼합 용액을 사용하여 실시한다. 종래의 경우에는 열공정에 의해 P2O5막이 형성되기 때문에 이를 제거하기 위한 세정이 필요했으나, 본 발명에서는 단순히 일반적인 세정만을 실시하면 된다.Thereafter, a washing process is performed. At this time, the washing is performed using a mixed solution of hydrofluoric acid (HF), hydrogen peroxide (H 2 O 2 ) and pure water (deionized H 2 O). In the conventional case, since a P 2 O 5 film is formed by a thermal process, cleaning is required to remove it, but in the present invention, only general cleaning may be performed.
끝으로, 도 1c에 도시된 바와 같이 전체구조 상부에 포토레지스트를 도포한 다음, 이를 패터닝하여 게이트 전극 형성을 위한 포토레지스트 패턴을 형성한 후, 포토레지스트 패턴을 식각 장벽으로하여 고상 성장된 폴리 실리콘막(12) 및 게이트 산화막(11)을 차례로 선택적 식각하고, 포토레지스트 패턴을 제거함으로씨 게이트 전극(13)을 형성한다.Finally, as shown in FIG. 1C, a photoresist is applied over the entire structure, and then patterned to form a photoresist pattern for forming a gate electrode, and then the solid silicon grown polysilicon using the photoresist pattern as an etch barrier. The seed gate electrode 13 is formed by selectively etching the film 12 and the gate oxide film 11 and removing the photoresist pattern.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기한 바와 같이 본 발명은 게이트 산화막 상부에 저온 증착된 폴리 실리콘막을 고상 성장 방식으로 성장시킴으로써 높은 온도에서 게이트 산화막이 열화되는 것을 방지하며, 결정 입자의 크기가 큰 폴리 실리콘막을 형성하여 게이트 전극의 저항을 낮춤으로써 전력 손실을 최소화 할 수 있다.As described above, the present invention prevents the gate oxide film from deteriorating at a high temperature by growing the low-temperature deposited polysilicon film on the gate oxide film in a solid phase growth method, and forms a polysilicon film having a large crystal grain size to resist the gate electrode. By lowering the power loss can be minimized.
또한 본 발명은 게이트 산화막과 폴리 실리콘막의 계면 특성을 향상시킴으로써 문턱 전압을 안정화하는 효과가 있으며, 폴리 실리콘막 내의 결함이 표면의 결정립계에서 석출되는 현상을 최소화함으로써 반도체 장치의 신뢰도 및 수율의 향상을 기대할 수 있다.In addition, the present invention has an effect of stabilizing the threshold voltage by improving the interfacial characteristics of the gate oxide film and the polysilicon film, and it is expected to improve the reliability and yield of the semiconductor device by minimizing the occurrence of defects in the polysilicon film at the grain boundary of the surface. Can be.
또한 실리콘 기판 인터페이스에서의 높은 불순물 집중도로 인하여 전류 구동력을 증가시키는등 반도체 장치의 동작 특성 및 신뢰도를 향상시키는 효과가 있다.In addition, due to the high concentration of impurities in the silicon substrate interface, there is an effect of improving the operating characteristics and reliability of the semiconductor device, such as increasing the current driving force.
Claims (7)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960076293A KR100251990B1 (en) | 1996-12-30 | 1996-12-30 | A method for forming gate electrode is semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960076293A KR100251990B1 (en) | 1996-12-30 | 1996-12-30 | A method for forming gate electrode is semiconductor device |
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| Publication Number | Publication Date |
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| KR19980057023A true KR19980057023A (en) | 1998-09-25 |
| KR100251990B1 KR100251990B1 (en) | 2000-05-01 |
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| KR1019960076293A KR100251990B1 (en) | 1996-12-30 | 1996-12-30 | A method for forming gate electrode is semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100293053B1 (en) * | 1999-06-08 | 2001-06-15 | 황인길 | Gate electrode manufacturing method of semiconductor devices |
| KR100446431B1 (en) * | 2002-10-09 | 2004-08-30 | 아남반도체 주식회사 | Method for manufacturing gate of semiconductor device |
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1996
- 1996-12-30 KR KR1019960076293A patent/KR100251990B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100293053B1 (en) * | 1999-06-08 | 2001-06-15 | 황인길 | Gate electrode manufacturing method of semiconductor devices |
| KR100446431B1 (en) * | 2002-10-09 | 2004-08-30 | 아남반도체 주식회사 | Method for manufacturing gate of semiconductor device |
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| Publication number | Publication date |
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| KR100251990B1 (en) | 2000-05-01 |
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