KR19980055713A - Contact hole formation method of semiconductor device - Google Patents

Contact hole formation method of semiconductor device Download PDF

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KR19980055713A
KR19980055713A KR1019960074949A KR19960074949A KR19980055713A KR 19980055713 A KR19980055713 A KR 19980055713A KR 1019960074949 A KR1019960074949 A KR 1019960074949A KR 19960074949 A KR19960074949 A KR 19960074949A KR 19980055713 A KR19980055713 A KR 19980055713A
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contact hole
insulating film
semiconductor device
film
forming
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KR1019960074949A
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KR100227635B1 (en
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백현철
김광철
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김영환
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 콘택홀 내부의 단차를 감소시키기 위하여 습식 식각된 부분과 건식 식각된 부분의 경계부에 형성된 돌출부를 제거하므로써 금속의 매립이 양호하게 이루어져 소자의 전기적 특성 및 수율이 향상될 수 있는 반도체 소자의 콘택홀 형성 방법에 관한 것이다.The present invention relates to a method of forming a contact hole in a semiconductor device, and in order to reduce the step in the contact hole, the metal is well buried by removing the protrusions formed at the boundary between the wet-etched part and the dry-etched part. The present invention relates to a method for forming a contact hole in a semiconductor device capable of improving characteristics and yield.

Description

반도체 소자의 콘택홀 형성 방법Contact hole formation method of semiconductor device

본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 특히 콘택홀 내부의 단차를 감소시킬 수 있도록 한 반도체 소자의 콘택홀 형성 방법에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device to reduce a step in the contact hole.

일반적으로 반도체 소자의 제조 공정에서 접합부와 도전층 또는 도전층간에는 절연막이 형성되며 접합부와 도전층 또는 도전층간의 접속은 절연막에 형성되는 콘택홀을 통해 이루어진다. 그런데 반도체 소자의 고집적화에 따른 콘택홀의 크기 감소 및 절연막의 두께 증가로 인하여 콘택홀 내부의 단차는 더욱 증가되는데, 이로인해 콘택홀내에 금속을 매립시키는 공정에 많은 어려움이 따른다. 그러면 종래 반도체 소자의 콘택홀 형성 방법을 도 1A 및 도 1B를 통해 설명하면 다음과 같다.In general, an insulating film is formed between the junction and the conductive layer or the conductive layer in the manufacturing process of the semiconductor device, and the connection between the junction and the conductive layer or the conductive layer is made through a contact hole formed in the insulating film. However, the step height inside the contact hole is further increased due to the decrease in the size of the contact hole and the increase in the thickness of the insulating layer due to the high integration of the semiconductor device, which causes a lot of difficulties in the process of embedding the metal in the contact hole. A method of forming a contact hole of a conventional semiconductor device will now be described with reference to FIGS. 1A and 1B.

종래에는 도 1A 에 도시된 바와 같이 접합부(2)가 형성된 실리콘 기판(1)상에 절연막(3) 및 감광막(4)을 순차적으로 형성한 후 콘택 마스크를 이용하여 상기 감광막(4)을 패터닝한다. 그리고 패터닝된 상기 감광막(4)을 마스크로 이용하여 상기 절연막(3)을 소정 두께 습식 식각한 후 나머지 두께의 상기 절연막(3)을 건식식각하여 도 1B 에 도시된 바와 같이 상기 접합부(2)가 노출되도록 콘택홀(5)을 형성하고 잔류된 상기 감광막(4)을 제거한다.Conventionally, as shown in FIG. 1A, the insulating film 3 and the photoresist film 4 are sequentially formed on the silicon substrate 1 on which the junction part 2 is formed, and then the photoresist film 4 is patterned using a contact mask. . Then, the wetted insulating film 3 is wet-etched by a predetermined thickness using the patterned photosensitive film 4 as a mask, followed by dry etching the insulating film 3 having the remaining thickness. The contact hole 5 is formed to be exposed and the remaining photosensitive film 4 is removed.

상기와 같은 방법을 이용하는 경우 등방성 식각 특성을 갖는 상기 습식 식각에 의해 상기 콘택홀(5)의 입구부가 둥글게 형성되어 상기 콘택홀(5) 상부의 단차는 감소되지만, 습식 식각된 부분과 건식 식각된 부분의 경계부에 돌출부(A)가 형성되어 상기 콘택홀(5) 내부의 단차가 증가된다. 그러므로 상기와 같은 단차의 증가에 의해 후속 금속층 형성시 금속의 층덮힘이 열악해져 상기 콘택홀(5)내에 금속이 완전히 매립되지 않게 되고, 이에 의해 소자의 전기적 특성 및 수율이 저하된다. 그래서 상기 돌출부(A)를 제거하기 위하여 상기 건식 식각 공정후 블랜켓(Blanket) 식각을 실시하여 상기 돌출부(A)를 제거하였으나, 이 경우 상기 절연막(3)의 손실이 발생되어 콘택홀간의 이격 거리가 감소되거나 금속배선간의 접촉이 발생된다.When the above method is used, the inlet portion of the contact hole 5 is rounded by the wet etching having the isotropic etching characteristic, so that the level difference of the upper portion of the contact hole 5 is reduced, but the wet etched portion and the dry etching A protrusion A is formed at the boundary of the portion, so that the step in the contact hole 5 is increased. Therefore, due to the increase of the step, the layer covering of the metal is poor when the subsequent metal layer is formed, so that the metal is not completely embedded in the contact hole 5, thereby lowering the electrical characteristics and yield of the device. Therefore, in order to remove the protrusion A, a blanket etching was performed after the dry etching process to remove the protrusion A, but in this case, loss of the insulating layer 3 occurred, so that a distance between contact holes was caused. Is reduced or contact between metal lines is generated.

따라서 본 발명은 콘택홀을 형성한 후 습식 식각된 부분과 건식 식각된 부분의 경계부에 형성된 돌출부를 제거하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 콘택홀 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a contact hole in a semiconductor device which can solve the above-mentioned disadvantages by removing the protrusions formed at the boundary between the wet etched portion and the dry etched portion after forming the contact hole.

상기한 목적을 달성하기 위한 본 발명은 접합부가 형성된 실리콘 기판상에 절연막 및 감광막을 순차적으로 형성한 후 상기 감광막을 패터닝사는 제 1 단계와, 상기 제 1 단계로부터 패터닝된 상기 감광막을 마스크로 이용하여 상기 절연막을 소정 두께 습식 식각한 후 나머지 두께의 상기 절연막을 건식 식각하여 상기 접합부가 노출되도록 콘택홀을 형서하는 제 2 단계와, 상기 제 2 단계로부터 상기 절연막보다 상기 감광막에 대한 식각 선택비가 높은 건식 식각 공정을 실시하여 상기 습식 식각된 부분과 건식 식각된 부분의 경계부에 형성된 돌출부(A)를 제거하는 제 3 단계와, 상기 제 3 단계로부터 잔류된 상기 감광막을 제거하는 제 4 단계로 이루어지는 것을 특징으로 하며, 상기 제 3 단계의 건식 식각 공정시 상기 절연막과 상기 감광막의 식각 선택비는 1 : 3 내지 10인 것을 특징으로 한다.The present invention for achieving the above object is formed by sequentially forming an insulating film and a photoresist film on the silicon substrate on which the junction is formed by using the photosensitive film patterned by the first step and the photosensitive film patterned from the first step as a mask A second step of wet etching the insulating film to a predetermined thickness and then dry etching the insulating film of the remaining thickness to form a contact hole so that the junction is exposed; and a dry etching rate higher than that of the insulating film from the second step. And a third step of removing the protrusion A formed at the boundary between the wet etched part and the dry etched part by performing an etching process, and a fourth step of removing the photoresist film remaining from the third step. The etching selectivity ratio of the insulating film and the photosensitive film in the dry etching process of the third step Is 1: 3 to 10 characterized in that.

도 1A 및 도 1B는 종래 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a method for forming a contact hole in a conventional semiconductor device.

도 2A 내지 도 2C 는 본 발명에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 소자의 단면도.2A to 2C are cross-sectional views of a device for explaining a method for forming a contact hole in a semiconductor device according to the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

1 및 11 : 실리콘 기판2 및 12 : 접합부1 and 11: silicon substrate 2 and 12: junction

3 및 13 : 절연막4 및 14 : 감광막3 and 13: insulating film 4 and 14 photosensitive film

5 및 15 : 콘택홀5 and 15: contact hole

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2A 및 도 2C 는 본 발명에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 소자의 단면도로서, 도 2A는 접합부(12)가 형성된 실리콘 기판(11)상에 절연막(13) 및 감광막(14)을 순차적으로 형성한 후 콘택 마스크를 이용하여 상기 감광막(14)을 패터닝한 상태의 단면도로서, 상기 절연막(13)은 산화막으로 형성된다.2A and 2C are cross-sectional views of a device for explaining a method of forming a contact hole in a semiconductor device according to the present invention, and FIG. 2A is an insulating film 13 and a photosensitive film 14 on a silicon substrate 11 having a junction portion 12 formed therein. ) Is a cross-sectional view of the photoresist layer 14 patterned using a contact mask after being sequentially formed, and the insulating layer 13 is formed of an oxide layer.

도 2B 는 패터닝된 상기 감광막(14)을 마스크로 이용하여 상기 절연막(13)을 소정 두께 습식 식각한 후 나머지 두께의 상기 절연막(13)을 건식 식각하여 상기 접합부(12)가 노출되도록 콘택홀(15)을 형성한 상태의 단면도인데, 등방성 식각 특성을 갖는 상기 습식 식각에 의해 상기 콘택홀(15)의 입구부가 둥글게 형성되어 상기 콘택홀(15) 상부의 단차는 감소되지만, 습식 식각된 부분과 건식 식각된 부분의 경계부에 돌출부(A)가 형성되어 상기 콘택홀(15)내부의 단차가 증가된다.FIG. 2B illustrates a contact hole in which the insulating layer 13 is wet-etched by a predetermined thickness using the patterned photoresist layer 14 as a mask and then dry-etched the insulating layer 13 having the remaining thickness to expose the junction 12. 15) is a cross-sectional view of the state in which the inlet portion of the contact hole 15 is rounded by the wet etching having the isotropic etching characteristic, the step of the upper portion of the contact hole 15 is reduced, but the wet etched portion A protrusion A is formed at the boundary of the dry etched portion to increase the level of the inside of the contact hole 15.

도 2C 는 상기 절연막(13)보다 상기 감광막(14)에 대한 식각 선택비가 높은 건식 식각 공정을 실시하여 상기 돌출부(A)를 제거한 상태의 단면도로서, 이후 잔류된 상기 감광막(14)을 제거한다.FIG. 2C is a cross-sectional view of a state in which the protruding portion A is removed by performing a dry etching process having a higher etching selectivity with respect to the photosensitive film 14 than the insulating film 13, and then removing the remaining photosensitive film 14.

여기서 상기 돌출부(A)를 제거하기 위한 식각 공정시 상기 절연막(13)과 상기 감광막(14)의 식각 선택비는 1 : 3 내지 10이 되도록 하고 상기 절연막(13)은 500 내지 2000Å 정도 식각되도록 한다. 그러면 상기 감광막(14)의 식각 선택비가 상기 절연막(13)보다 높기 때문에 상기 감광막(14)이 식각됨에 따라 상기 절연막(13)이 노출되는 면적이 증가되고, 이에 의해 상기 돌출부(A)가 노출되어 식각되는데, 상기 절연막(13)의 식각 선택비가 매우 낮기 때문에 상기 절연막(13)의 식각정도는 최소화된다.The etching selectivity of the insulating film 13 and the photosensitive film 14 during the etching process for removing the protrusion A may be 1: 3 to 10 and the insulating film 13 may be etched at about 500 to 2000Å. . Then, since the etching selectivity of the photosensitive film 14 is higher than that of the insulating film 13, as the photosensitive film 14 is etched, an area where the insulating film 13 is exposed increases, thereby exposing the protrusion A. Although the etching selectivity of the insulating layer 13 is very low, the etching degree of the insulating layer 13 is minimized.

참고적으로, 미국의 CAMAT 회사가 제작한 C-5300(ICP형) 장비에 소오스 전력(Source Power) 및 바이어스 전력(Bias Power)을 각각 2800 와트(W) 및 30 와트(W)로 공급하고 C2F6, Ar O 가스를 이용하여 30초 동안 건식 식각을 실시한 결과 상기 절연막(13)의 손실이 최소화되며 상기 돌출부(A)가 제거되었으며, 이에 따라 상기 콘택홀(15)내에 금속이 양호하게 매립될 수 있었다.For reference, source power and bias power are supplied at 2800 Watts (W) and 30 Watts (W) to C-5300 (ICP) equipment manufactured by CAMAT, USA. As a result of performing dry etching for 30 seconds using 2 F 6 and Ar O gas, the loss of the insulating layer 13 is minimized and the protrusion A is removed. Thus, the metal in the contact hole 15 is well formed. Could be reclaimed.

상술한 바와 같이 본 발명에 의하면 콘택홀을 형성한 후 식각 마스크로 이용된 감광막과 절연막의 식각 선택비를 조절하여 습식 식각된 부분과 건식 식각된 부분의 경계부에 형성된 돌출부를 제거하므로써 절연막의 손실을 최소화시키며 콘택홀 내부의 단차를 감소시킬 수 있다. 그러므로 콘택홀내에 금속의 매립이 양호하게 이루어져 소자의 수율 및 신뢰성이 향상될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, after the contact hole is formed, the loss of the insulating film is reduced by controlling the etching selectivity of the photoresist film and the insulating film used as the etch mask to remove the protrusions formed at the boundary between the wet and dry etched portions. Minimize and reduce the step height inside the contact hole. Therefore, the filling of the metal in the contact hole is good, there is an excellent effect that can improve the yield and reliability of the device.

Claims (2)

반도체 소장의 콘택홀 형성 방법에 있어서,In the method of forming a contact hole in a semiconductor small intestine, 접합부가 형성된 실리콘 기판상에 절연막 및 감광막을 순차적으로 형성한 후 상기 감강괌긍 패터닝하는 제 1 단계와,A first step of sequentially forming an insulating film and a photoresist film on the silicon substrate on which the junction part is formed, and then patterning the reduced Guam; 상기 제 1 단계로부터 패터닝된 상기 감광막을 마스크로 이용하여 상기 절연막을 소정 두께 습식 식각한 후 나머지 두께의 상기 절연막을 건식 식각하여 상기 접합부가 노출되도록 콘택홀을 형서하는 제 2 단계와,A second step of forming a contact hole so that the junction is exposed by wet etching the insulating film by a predetermined thickness using the photosensitive film patterned from the first step as a mask and then dry etching the insulating film having the remaining thickness; 상기 제 2 단계로부터 상기 절연막보다 상기 감광막에 대한 식각 선택비가 높은 건식 식각 공정을 실시하여 상기 습식 식각된 부분과 건식 식각된 부분의 경계부에 형성된 돌출부(A)를 제거하는 제 3 단계와,Performing a dry etching process having a higher etching selectivity with respect to the photoresist film than the insulating film from the second step to remove the protrusion A formed at the boundary between the wet etched portion and the dry etched portion; 상기 제 3 단계로부터 잔류된 상기 감광막을 제거하는 제 4 단계로 이루어진 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.And a fourth step of removing the photoresist film remaining from the third step. 제 1 항에 있어서,The method of claim 1, 상기 제 3 단계의 건식 식각 공정시 상기 절연막과 상기 감광막의 식각 선택비는 1 : 3 내지 10인 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.The etching selectivity of the insulating film and the photosensitive film during the dry etching process of the third step is a contact hole forming method of the semiconductor device, characterized in that 1: 3 to 10.
KR1019960074949A 1996-12-28 1996-12-28 Method of forming contact hole in semiconductor device KR100227635B1 (en)

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