KR19980083136A - Wiring formation method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method for simplifying the process and suppressing disconnection and short circuit of the metal wiring to increase the reliability of the wiring.

In the wiring forming method of the present invention, forming a transistor having an impurity region in a substrate, forming a first insulating film having a contact hole on the impurity region, and forming a plug in the contact hole; Forming a second insulating film on the first insulating film including a second insulating film, selectively removing a second insulating film at a portion of the portion where the metal wiring is to be formed, and a second portion at the portion where the second insulating film is removed. And forming a wiring with the same thickness as the insulating film.

Description

Wiring formation method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method, and more particularly, to a wiring forming method having a simple process and high reliability for wiring.

In the conventional wiring forming method, as shown in FIG. 1A, an initial oxide film, a first nitride film, and a first photosensitive film are sequentially formed on a semiconductor substrate 11 having a p-type, active region, and isolation region, and then the first photosensitive film. Is selectively exposed and developed to remove only the upper portion of the isolation region, and then selectively etches the first nitride film and the initial oxide film using the selectively exposed and developed first photoresist film as a mask to remove the first photoresist film. Subsequently, the first nitride film is used as a mask to form a field oxide film 12 in the isolation region by a thermal oxidation process on the entire surface, and then the first nitride film and the initial oxide film are removed.

Subsequently, the gate oxide film 13 is formed on the semiconductor substrate 11 by a thermal oxidation process, and then first polycrystalline silicon and a second photoresist film are sequentially formed on the entire surface of the semiconductor substrate 11, and the second photoresist film is selectively selected so that only a portion where the gate is to be formed remains. After exposing and developing with light, the first polycrystalline silicon is selectively etched using the selectively exposed and developed second photoresist film to form a gate electrode 14, and the second photoresist film is removed.

The impurity region 15 is formed in the semiconductor substrate 11 on both sides of the gate electrode 14 by implanting and driving in the n-type impurity ions on the entire surface of the gate electrode 14 using a mask.

As shown in FIG. 1B, a contact hole for sequentially forming a first oxide film 16 and a third photoresist film on the entire surface including the gate electrode 14 and connecting the third photoresist film to the impurity region 15 is connected to a wiring. Selectively exposing and developing the portions to be formed, and then selectively etching the first oxide layer 16 and the gate oxide layer 13 using the selectively exposed and developed third photoresist layer as a mask to form two contact holes. After the formation, the third photosensitive film is removed. In this case, the first oxide layer 16 is formed thick so that the entire surface thereof is flat.

A tungsten layer is formed on the first oxide layer 16 including the two contact holes, and the tungsten layer is etched back to form a tungsten plug 17 filling the two contact holes.

As shown in FIG. 1C, a metal layer 18 and a fourth photosensitive layer 19 are sequentially formed on the first oxide layer 16 including the tungsten plug 17, and the fourth photosensitive layer 19 is formed by two contact holes. And selectively expose and develop only a portion of the upper portion of the first oxide film 16 around the first oxide film 16, and then selectively etch the metal layer using the selectively exposed and developed fourth photoresist film 19 to form a wiring layer. .

As shown in FIG. 1D, the fourth photoresist film 19 is removed and a second oxide film is formed on the first oxide film 16 including the metal layer 18.

The conventional wiring forming method has the following problems by forming a wiring layer by patterning a metal layer.

First, when patterning the metal layer, short circuits between metal wires frequently occur due to debris of the photoresist film.

Second, during patterning of the metal layer, notching occurs frequently due to a step or halation of the metal layer, resulting in disconnection of the metal wiring.

Third, since the wiring layer protrudes, a surface planarization process using an oxide film is required in a later step.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method for forming a wiring having high reliability for wiring by simplifying the process and suppressing disconnection and short circuit of the metal wiring.

1A to 1D are cross-sectional views illustrating a conventional wiring forming method.

2A to 2D are cross-sectional views illustrating a wiring forming method according to an embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 field oxide film

33: gate oxide film 34: gate electrode

35 source / drain region 36 first oxide film

37: tungsten plug 38: second oxide film

39: fourth photosensitive film 40: metal layer

In the wiring forming method of the present invention, forming a transistor having an impurity region in a substrate, forming a first insulating film having a contact hole on the impurity region, and forming a plug in the contact hole; Forming a second insulating film on the first insulating film including a second insulating film, selectively removing a second insulating film at a portion of the portion where the metal wiring is to be formed, and a second portion at the portion where the second insulating film is removed. And forming a wiring with the same thickness as the insulating film.

When described in detail with reference to the accompanying drawings a preferred embodiment of the wiring forming method according to the present invention as follows.

In the wiring forming method according to the embodiment of the present invention, as illustrated in FIG. And selectively exposing and developing the first photoresist film so as to remove only the upper portion of the isolation region, and selectively etching the first nitride film and the initial oxide film using the selectively exposed and developed first photoresist film as a mask. 1 The photoresist film is removed. Next, the first nitride film is used as a mask to form a field oxide film 32 in the isolation region by thermal oxidation on the entire surface thereof, and then the first nitride film and the initial oxide film are removed.

Subsequently, the gate oxide film 33 is formed on the semiconductor substrate 31 by a thermal oxidation process, and then, first polycrystalline silicon and a second photoresist film are sequentially formed on the entire surface, and the second photoresist film is selectively selected so that only the portion where the gate is to be formed remains. After exposing and developing with light, the first polycrystalline silicon is selectively etched using the selectively exposed and developed second photoresist film to form a gate electrode 34, and the second photoresist film is removed.

The impurity region 35 is formed in the semiconductor substrate 31 on both sides of the gate electrode 34 by implanting and driving in the n-type impurity ions on the entire surface of the gate electrode 34 using a mask.

As shown in FIG. 2B, a contact hole for sequentially forming a first oxide film 36 and a third photoresist film on the entire surface including the gate electrode 34 and connecting the third photoresist film to the impurity region 35 is connected to a wiring. Selectively exposing and developing the portions to be formed, and then selectively etching the first oxide layer 36 and the gate oxide layer 33 using the selectively exposed and developed third photoresist layer as a mask to form two contact holes. After the formation, the third photosensitive film is removed. The first oxide layer 36 is formed to be thick so that the entire surface thereof is flat.

A tungsten layer is formed on the first oxide layer 36 including the two contact holes, and the tungsten layer is etched back to form a tungsten plug 37 filling the two contact holes.

As shown in FIG. 2C, a second oxide film 38 and a fourth photosensitive film 39 are sequentially formed on the first oxide film 36 including the tungsten plug 37, and the fourth photosensitive film 39 is formed in two. After selectively exposing and developing only a portion of the upper portion of the first oxide layer 36 around the contact holes, the second oxide layer 38 may be formed using the selectively exposed and developed fourth photoresist layer 39 as a mask. Etch selectively.

As shown in FIG. 2D, the fourth photoresist film 39 is removed, the metal layer 40 is formed on the entire surface including the second oxide film 38, and then the metal layer 40 is etched back to form a wiring layer. .

In the wiring forming method of the present invention, after the insulating film is patterned, the metal layer is deposited and then etched back to form the wiring layer so that the entire surface is flat, so that the planarization step is not performed in the subsequent step. Since the disconnection and short circuit of the metal wiring which generate | occur | produced are suppressed, there exists an effect that reliability of a wiring layer is high.

Claims (2)

Forming a transistor having an impurity region in the substrate; Forming a first insulating film having a contact hole on the impurity region over the entire surface; Forming a plug in the contact hole; Forming a second insulating film on the first insulating film including the plug; Selectively removing a second insulating film of a portion where a metal wiring is to be formed around the plug; And forming a wiring in the same thickness as that of the second insulating film in a portion where the second insulating film is removed. The method of claim 1, And the wiring layer is formed by depositing a conductive layer on the first and second insulating films and etching back so that only the portion of the second insulating film is removed at the height of the second insulating film.