KR19980046264A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices and manufacturing methods, and more particularly, to semiconductor devices and manufacturing methods that are highly integrated and low resistance.

The semiconductor device and the manufacturing method of the present invention for this purpose is to form an isolation layer in the isolation region of the first conductivity type substrate in which the active region and the isolation region are defined, and a gate insulating film on a predetermined portion of the active region of the first conductivity type substrate A gate electrode provided, a second conductive first impurity region is formed in a first conductive substrate on both sides of the gate electrode, an insulating film sidewall is formed on the first conductive substrate on both sides of the gate, Forming a second insulating film, and removing the second insulating film and the isolation layer in the second conductive first impurity region to be wider than a distance between the insulating film sidewall and the isolation layer to form a contact hole, and insulating in the contact hole. A first conductive layer is formed inside the contact hole to form a second conductivity type second impurity region on the substrate from which the layer is removed, and is connected to the first conductive layer in the contact hole. Which it is characterized by configured by comprising a second conductive layer having a low resistance.

Description

Semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices and manufacturing methods, and more particularly, to semiconductor devices and manufacturing methods that are highly integrated and low resistance.

Hereinafter, a semiconductor device according to the related art will be described with reference to the accompanying drawings.

1 is a structural cross-sectional view of a general semiconductor device.

As shown in FIG. 1, a general semiconductor device includes a p-type semiconductor substrate in which an active region and an isolation region are defined, a field oxide film formed on a surface of the semiconductor region of the isolation region, and a gate oxide film in a predetermined region on the semiconductor substrate of the active region. And a first electrode, a second n-type impurity region formed in the semiconductor substrate on both sides of the gate electrode, and a nitride film sidewall formed on the semiconductor substrate on both sides of the gate electrode.

2 is a structural cross-sectional view of a semiconductor device according to a first embodiment of the prior art.

As shown in FIG. 2, the semiconductor device according to the first embodiment of the related art having a contact margin when wiring is formed in the provisional part of FIG. 1 is a p-type semiconductor substrate 11 having an active region and an isolation region, and the isolation region. Field oxide film 12 formed on the surface of semiconductor substrate 11 of the substrate, gate electrode 14 formed with gate oxide film 13 in a predetermined region on semiconductor substrate 11 of the active region, and gate electrode 14 A second n-type impurity region 16 formed in the semiconductor substrate 11 on both sides, a nitride film sidewall 17 formed on the semiconductor substrate 11 on both sides of the gate electrode 14, and the nitride film sidewall 17. And a contact hole between the field oxide film 12 and the oxide film 18 formed on the entire surface, and the second n-type impurity region 16 and the oxide film 18 exposed by the contact hole. a metal layer 19 electrically connected to the n-type impurity region 16. .

3 is a structural cross-sectional view of a semiconductor device according to a second embodiment of the prior art.

As shown in FIG. 3, the semiconductor device according to the second embodiment of the related art having no contact margin when wiring is formed in the provisional part of FIG. 1 is a p-type semiconductor substrate 11 having an active region and an isolation region, and the isolation region. Field oxide film 12 formed on the surface of semiconductor substrate 11 of the substrate, gate electrode 14 formed with gate oxide film 13 in a predetermined region on semiconductor substrate 11 of the active region, and gate electrode 14 ) The second n-type impurity region 16 formed in the semiconductor substrate 11 on both sides, the nitride film sidewall 17 formed on the semiconductor substrate 11 on both sides of the gate electrode 14, and no contact margin. It is formed on the sidewall 17 and the oxide film 18 having a contact hole in a predetermined portion on the field oxide film 12 and formed on the entire surface, the second impurity region 16 and the oxide film 18 exposed by the contact hole. Is electrically connected to the second n-type impurity region 16. A n-type impurity diffused by the n-type impurity doped by the polycrystalline silicon 20 doped with the n-type impurity and the polycrystalline silicon 20 doped with the n-type impurity in the semiconductor substrate 11 exposed when the contact hole is formed. It consists of 3 n-type impurity regions 21.

The conventional semiconductor device has the following problems.

First, when there is a contact margin, since the space between the active region and the contact must be secured for the contact margin, the area is increased, which is not suitable for high integration of the device.

Second, when there is no contact margin, there is a need for leakage current due to the semiconductor substrate exposed when forming the contact hole, and thus the resistance of the device increases because the contact hole is filled with high-resistance polycrystalline silicon instead of the low-resistance metal layer.

The present invention has been made to solve the above problems, and the object of the present invention is to provide a highly integrated and low resistance semiconductor device and a manufacturing method by filling contact holes with polycrystalline silicon on the bottom and a metal layer on the top.

1 is a structural cross-sectional view of a general semiconductor device

2 is a structural cross-sectional view of a semiconductor device according to a first embodiment of the prior art

3 is a structural cross-sectional view of a semiconductor device according to a first embodiment of the prior art;

4 is a structural cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.

5A through 5E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

31: semiconductor substrate 32: field oxide film

33: gate oxide film 34: gate

35: first n-type impurity region 36: second n-type impurity region

37: insulating film sidewall 38: oxide film

40: polycrystalline silicon 41: metal layer

35: third n-type impurity region

The semiconductor device of the present invention includes a first conductive substrate having an active region and an isolation region defined therein, an isolation layer formed in an isolation region of the first conductive substrate, and a gate insulating film at a predetermined portion of the active region of the first conductive substrate. A gate electrode formed on the substrate, a second conductive first impurity region formed in the first conductive substrate on both sides of the gate electrode, an insulating film sidewall formed on the first conductive substrate on both sides of the gate, and formed on the front surface A contact hole formed by removing the second insulating film and the isolation layer in the second insulating film and the second conductive first impurity region to be wider than a distance between the sidewall of the insulating film and the isolation layer, and the isolation layer in the contact hole is removed. A second conductive type impurity region formed in a substrate, a first conductive layer formed in the contact hole so as to be connected to the second conductive type first and second impurity regions, and the contact And a second resistance layer having a low resistance formed to be connected to the first conductive layer in the hole.

The method of manufacturing a semiconductor device of the present invention includes forming an isolation layer in an isolation region of a first conductivity type substrate, and forming a gate electrode having a gate insulating layer on a predetermined portion of an active region of the first conductivity type substrate. Forming a second conductive impurity region in the first conductive substrate on both sides of the gate, forming an insulating film sidewall on the first conductive substrate on both sides of the gate, forming a second insulating film on the entire surface, and Forming a contact hole by patterning a second insulating film wider than an interval between the insulating film sidewall and the isolation layer, and dispersing a second conductive impurity in a portion where the first conductive substrate is exposed below the contact hole. Forming a first conductive layer into which a second conductivity type impurity is implanted so as to generate an impurity region, and forming a low resistance second conductive layer in a contact hole on the first conductive layer Including the step of: characterized by true.

When described in detail with reference to the accompanying drawings a preferred embodiment of the semiconductor device and the manufacturing method according to the present invention as follows.

4 is a cross-sectional view illustrating a structure of a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 4, the semiconductor device according to the embodiment of the present invention, which has no contact margin when wiring is formed in the provisional part of FIG. 1, has a p-type semiconductor substrate 31 and an active region and an isolation region. The field oxide film 32 formed on the surface of the substrate 31, the gate electrode 34 formed with the gate oxide film 33 in a predetermined region on the semiconductor substrate 31 of the active region, and both sides of the gate electrode 34. A second n-type impurity region 36 formed in the semiconductor substrate 31, a nitride film sidewall 37 formed on the semiconductor substrate 31 on both sides of the gate electrode 34, and no contact margin, so that the nitride film sidewall ( 37) and an oxide film 38 having a contact hole in a predetermined portion on the field oxide film 32, and formed on a lower surface of the contact oxide, and formed only in the lower portion of the contact hole, and electrically connected to the second n-type impurity region 36. Doped polycrystalline silicon (40 N-type impurities are formed on the low-resistance metal layer 41 having low contact resistance and electrically connected to the polycrystalline silicon 40 in the contact hole and the semiconductor substrate 31 exposed when the contact hole is formed. The third n-type impurity region 42 is formed by diffusion of n-type impurities by the doped polycrystalline silicon 40.

5A through 5E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 5A, a first oxide film, a first nitride film, and a first photosensitive film are sequentially formed on the semiconductor substrate 31 on which the isolation region is defined, and then the first photoresist film is selectively exposed to be removed only above the isolation region. And after the development, the first nitride film and the first oxide film are selectively etched using the selectively exposed and developed first photoresist film as a mask, and the first photoresist film is removed.

Since the first nitride film is used as a mask, heat is applied to the entire surface, so that the field oxide film 32 is grown on the surface of the semiconductor substrate 31 in the isolation region, and then the first oxide film formed on the semiconductor substrate 31. And the first nitride film is removed.

As shown in FIG. 5B, a second oxide film, a first polycrystalline silicon, and a second photosensitive film are sequentially formed on the entire surface including the field oxide film 32, and then the exposure and the second photosensitive film are selectively exposed so that only the portion where the gate is to be formed is left. After the development, the gate oxide film 33 and the gate electrode 34 are formed by etching the first polycrystalline silicon and the second oxide film using the selectively exposed and developed second photoresist film as a mask, and the second photoresist film is formed. Remove

As shown in FIG. 5C, first and second n-type impurity regions 35 and 36 are formed by implanting and driving-in diffusion of n-type impurity ions on the front surface using the gate electrode 34 as a mask and then on the front surface. After the second nitride film is formed, the nitride film sidewalls 37 are formed on both sides of the gate electrode 34 by etching.

As shown in FIG. 5D, an oxide film 38 and a third photoresist film are sequentially formed on the entire surface, and then the third photoresist film is selectively removed so that only a portion where a contact hole is to be formed on the second n-type impurity region 36 is removed. After exposure and development, the contact layer is formed on the second n-type impurity region 36 by etching the oxide film 38 using the selectively exposed and developed third photoresist film as a mask, and the third photoresist film is formed. Remove Since the gap between the nitride film sidewall 37 and the field oxide film 32 is narrow, there is no contact margin, and thus the semiconductor substrate 31 is exposed because the field oxide film 32 is selectively etched during the contact hole forming process.

As shown in FIG. 5E, polycrystalline silicon 40 doped with n-type impurities is formed on the entire surface and etched back. Therefore, only the lower portion of the contact hole exists in the polycrystalline silicon 40. Here, the n-type impurity is diffused into the semiconductor substrate 31 exposed when the contact hole is formed by the polycrystalline silicon 40 into which the n-type impurity is implanted to form a third n-type impurity region 42. Then, a low resistance metal layer 41 having a low contact resistance is formed on the front surface and etched back so as to exist only in the contact hole on the polycrystalline silicon 40.

The semiconductor device of the present invention and the method of manufacturing the same have a large effect on the high integration and high characteristics of the device because the contact area is filled with polycrystalline silicon at the bottom, and a metal layer at the top to reduce the area and resistance of the device.

Claims (2)

A first conductivity type substrate having an active region and an isolation region defined therein; An isolation layer formed in the isolation region of the first conductivity type substrate; A gate electrode formed with a gate insulating film on a predetermined portion of an active region of the first conductivity type substrate; A second conductivity type first impurity region formed in the first conductivity type substrate on both sides of the gate electrode; An insulating film sidewall formed on the first conductive substrate on both sides of the gate; A second insulating film formed on the entire surface; A contact hole formed in the second conductivity type first impurity region by removing the second insulating film and the isolation layer so that a distance between the insulating film sidewall and the isolation layer is wider than a gap; A second conductivity type second impurity region formed in the substrate from which the isolation layer in the contact hole is removed; A first conductive layer formed inside the contact hole to be connected to the second conductive first and second impurity regions; And a low resistance second conductive layer formed to be connected to the first conductive layer in the contact hole. Forming an isolation layer in an isolation region of the first conductivity type substrate; Forming a gate electrode having a gate insulating film on a predetermined portion of an active region of the first conductivity type substrate; Forming a second conductivity type first impurity region in the first conductivity type substrate on both sides of the gate; Forming sidewalls of an insulating film on the first conductive substrate on both sides of the gate; Forming a second insulating film over the entire surface, and patterning the second insulating film to be wider than an interval between the insulating film sidewall and the isolation layer to form a contact hole exposing the first conductive substrate; Forming a first conductive layer in which a second conductive impurity is implanted so that a second impurity region is formed by diffusing a second conductive impurity in a portion where the first conductive substrate is exposed under the contact hole; And forming a low resistance second conductive layer in the contact hole on the first conductive layer.