KR19980036132A - Separator Formation Method - Google Patents
Separator Formation Method Download PDFInfo
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- KR19980036132A KR19980036132A KR1019960054629A KR19960054629A KR19980036132A KR 19980036132 A KR19980036132 A KR 19980036132A KR 1019960054629 A KR1019960054629 A KR 1019960054629A KR 19960054629 A KR19960054629 A KR 19960054629A KR 19980036132 A KR19980036132 A KR 19980036132A
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- trench
- forming
- film
- insulating film
- separator
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 17
- 239000001301 oxygen Substances 0.000 claims abstract description 17
- 238000002955 isolation Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- -1 oxygen ions Chemical class 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims abstract 2
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 230000005684 electric field Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Element Separation (AREA)
Abstract
본 발명은 격리막 형성 방법에 관한 것으로, 특히 고집적 소자를 효율적으로 소자 분리하는 격리막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a separator, and more particularly, to a method of forming a separator for efficiently separating a highly integrated device.
이를 위한 본 발명의 격리막 형성 방법은 기판상에 제1절연막을 증착하고 소자 격리영역의 상기 제1절연막 및 상기 기판을 소정 깊이로 식각하여 트렌치를 형성하는 단계, 상기 트렌치에 산소 이온을 틸트 이온 주입하는 단계, 상기 트렌치 내에 상기 제2절연막을 형성하는 단계, 상기 제2절연막을 열처리하여 격리층을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The isolation layer forming method according to the present invention comprises depositing a first insulating layer on a substrate and etching the first insulating layer and the substrate in a device isolation region to a predetermined depth to form a trench, and implanting oxygen ions into the trench. And forming a second insulating layer in the trench, and heat-treating the second insulating layer to form an isolation layer.
Description
본 발명은 격리막 형성 방법에 관한 것으로, 특히 고집적 소자를 효율적으로 소자 분리하는 격리막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a separator, and more particularly, to a method of forming a separator for efficiently separating a highly integrated device.
반도체가 점점 고집적화 되면서 디자인 룰(Design rule)이 감소하고 이에 따라 소자격리를 위한 격리 영역도 감소하게 된다. 따라서 기존의 격리막 형성 방법으로 로코스(LOCOS)는 작은 영역에서도 소자 격리를 할 수 있는 트렌치 격리막(Trench Isolation) 형성 방법으로 변해가고 있다.As semiconductors become increasingly integrated, design rules are reduced, thus reducing isolation for device isolation. Therefore, LOCOS is changing to a trench isolation method that can isolate a device even in a small area.
이하 첨부된 도면을 참고하여 종래의 격리막 형성 방법을 설명하면 다음과 같다.Hereinafter, a method of forming a conventional separator with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래 기술에 따라 격리막 형성 방법을 나타낸 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a separator according to the prior art.
도 1a에서와 같이, 격리 영역이 정의된 반도체 기판(11)상에 제1산화막(12)과 제1감광막(13)을 차례로 형성한 다음, 상기 제1감광막(13)을 상기 격리영역 상측에만 제거되도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제1감광막(13)을 마스크로 이용하여 상기 제1산화막(12)과 반도체 기판(11)을 선택적으로 비등방성 식각하여서 트렌치(Trench)를 형성한다. 그리고 상기 제1감광막(13)을 마스크로 이용하여 전면에 열을 가하므로 상기 트렌치 내벽에 상기 제1산화막(12)보다 두껍게 제2산화막(14)을 성장 시킨 다음, 상기 제1감광막(13)을 제거한다.As shown in FIG. 1A, the first oxide film 12 and the first photoresist film 13 are sequentially formed on the semiconductor substrate 11 on which the isolation region is defined, and then the first photoresist film 13 is formed only above the isolation region. After selectively exposing and developing to be removed, the first oxide film 12 and the semiconductor substrate 11 are selectively anisotropically etched using the selectively exposed and developed first photosensitive film 13 as a mask to form a trench ( Trench). Since the first photoresist layer 13 is used as a mask, heat is applied to the entire surface, so that the second oxide layer 14 is grown on the inner wall of the trench thicker than the first oxide layer 12, and then the first photoresist layer 13 is formed. Remove it.
도 1b에서와 같이, 전면에 질화막(15)과 다결정 실리콘(16)을 형성한 다음, 상기 다결정 실리콘(16)을 에치백한다.As shown in FIG. 1B, the nitride film 15 and the polycrystalline silicon 16 are formed on the entire surface, and then the polycrystalline silicon 16 is etched back.
여기서 상기 다결정 실리콘(16)은 에치백 공정으로 상기 트렌치 내의 중간부위에만 존재하게 된다.Here, the polycrystalline silicon 16 is present only in the middle portion of the trench by an etch back process.
도 1c에서와 같이, 상기 다결정 실리콘(16)을 포함한 질화막(15) 상에 BPSG(Boron Phosphosilicate Glass)층(17)을 형성하고 에치백 한다. 여기서 상기 BPSG층(17)은 에치백 공정으로 상기 트렌치내에만 존재하여 트렌치를 메꾼다. 그리고 상기 BPSG 층(17)을 포함한 질화막(15)상에 제3산화막(18)을 형성한다.As shown in FIG. 1C, a boron phosphosilicate glass (BPSG) layer 17 is formed and etched back on the nitride film 15 including the polycrystalline silicon 16. Here, the BPSG layer 17 exists only in the trench in an etch back process to fill the trench. A third oxide film 18 is formed on the nitride film 15 including the BPSG layer 17.
종래의 격리막 형성 방법은 2차에 걸친 트렌치 필링(Trench Filling) 공정을 실시했으나 고집적화에 따라 트렌치 깊이가 깊어져 보이드(Void) 문제가 심하고, 트렌치 바닥이 평평하여 트렌치의 모서리 부분에 전기장이 집중되는 문제가 있었다.Conventional isolation film formation process has been carried out two-step trench filling process, but due to the high integration, deep trench depth, void problems (Void), flat trench bottom, electric field is concentrated in the corner of the trench There was a problem.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 트렌치에 산소 이온을 틸트 이온 주입시키고 필링 물질을 산화시킴으로 보이드를 억제하고 하부 부분이 라운딩(Rounding)된 트렌치로 전기장이 감소되는 격리막 형성 방법을 제공하는게 그 목적이 있다.The present invention has been made to solve the above problems to provide an isolation film formation method of suppressing the voids by injecting oxygen ions into the trenches and oxidizing the filling material to suppress the voids and to reduce the electric field to the rounded trench. The purpose is to do that.
도 1a 내지 도 1c는 종래 기술에 따른 격리막 형성 방법을 나타낸 공정 단면도1A to 1C are cross-sectional views illustrating a method of forming a separator according to the prior art.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 격리막 형성 방법을 나타낸 공정 단면도.2A to 2E are cross-sectional views illustrating a method of forming a separator according to an embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
31:반도체 기판32:제1산화막31: semiconductor substrate 32: first oxide film
33:질화막35:산소 이온 영역33: nitride film 35: oxygen ion region
36:제2산화막37:필드 산화막36: second oxide film 37: field oxide film
본 발명의 격리막 형성 방법은 기판상에 콘택홀을 갖는 제1절연막을 형성하는 단계, 상기 콘택홀하에 트렌치가 형성되도록 기판을 패터닝하는 단계, 전면에 산소 이온을 틸트 이온 주입하는 단계, 전면에 제2절연막을 형성하고, 상기 트렌치내에만 남도록 상기 제2절연막을 패터닝하는 단계와 상기 제2절연막을 열처리하여 격리층을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In the method for forming a separator of the present invention, the method includes forming a first insulating layer having a contact hole on a substrate, patterning the substrate so that a trench is formed under the contact hole, implanting oxygen ions into a front surface, and applying a tilt ion to the front surface. And forming a second insulating film, patterning the second insulating film so as to remain only in the trench, and heat-treating the second insulating film to form an isolation layer.
상기와 같은 본 발명에 따른 격리만 형성 방법의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.If described in detail with reference to the accompanying drawings, a preferred embodiment of the isolation forming method according to the present invention as follows.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 격리막 형성 방법을 나타낸 공정 단면도이다.2A to 2E are cross-sectional views illustrating a method of forming a separator according to an embodiment of the present invention.
도 2a에서와 같이, 격리 영역이 정의된 반도체 기판(31) 상에 제1산화막(32), 질화막(33), 제1감광막(34)을 차례로 형성한 다음, 상기 제1감광막(34)을 상기 격리 영역 상측에만 제거되도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제1감광막(34)을 마스크로 이용하여 상기 질화막(33)을 등방성 식각으로 또 상기 제1산화막(32)을 이방성 식각함으로 콘택홀을 형성하고 상기 제1감광막(34)을 제거한다.As shown in FIG. 2A, the first oxide film 32, the nitride film 33, and the first photoresist film 34 are sequentially formed on the semiconductor substrate 31 on which the isolation region is defined, and then the first photoresist film 34 is formed. After selectively exposing and developing to be removed only above the isolation region, the nitride film 33 is isotropically etched using the selectively exposed and developed first photosensitive film 34 as a mask and the first oxide film 32 is removed. The contact hole is formed by anisotropic etching to remove the first photoresist layer 34.
도 2b에서와 같이, 상기 질화막(33)을 마스크로 이용하여 상기 반도체 기판(31)을 일정 깊이 만큼 식각함으로 트렌치를 형성한다.As shown in FIG. 2B, the trench is formed by etching the semiconductor substrate 31 by a predetermined depth using the nitride film 33 as a mask.
도 2c에서와 같이, 상기 질화막(33)을 마스크로 이용하여 상기 트렌치 상부에 산소 이온틀 틸트(Tilt) 이온 주입하여 산소 이온 주입 영역(35)을 형성한다.As illustrated in FIG. 2C, the oxygen ion implantation region 35 is formed by implanting oxygen ion tilt in the upper portion of the trench by using the nitride film 33 as a mask.
여기서 상기 산소 이온의 틸트(Tilt) 이온 주입으로 산소 이온이 상기 트렌치 상부의 양측에 주입되어 제1산소 이온 영역을 형성하고, 일부분이 반사되어 상기 트렌치 중간 부분의 양측에 주입되어 제2산소 이온 영역을 형성하며, 일부분이 상기 트렌치 바바닥에 주입되어 제3산소 이온 영역을 형성한다.Here, oxygen ions are injected to both sides of the trench to form first oxygen ion regions by tilt ion implantation of the oxygen ions, and portions of the oxygen ions are reflected to be injected to both sides of the middle portion of the trench to inject the second oxygen ion regions. And a portion is implanted into the bottom of the trench to form a third oxygen ion region.
도 2d에서와 같이, 전면에 제2산화막(36)을 CVD방법으로 형성하고, 에치백한다. 여기서 상기 제2산화막(36)은 상기 에치백 공정으로 상기 트렌치 내에만 잔류하게 된다.As shown in Fig. 2D, a second oxide film 36 is formed on the entire surface by a CVD method and etched back. Here, the second oxide layer 36 remains only in the trench by the etch back process.
그리고 도 2e에서와 같이, 상기 에치백 공정을 실시한 제2산화막(36)을 포함한 전면에 열을 가하여 상기 제2산화막(36)과 반도체 기판(11)을 반응시켜 필드 산화막(37)을 형성한 다음, 상기 질화막(33)과 제1산화막(32)을 제거한다. 여기서 필드 산화막(37)은 다른 부위보다 상기 산소 이온 주입 영역(35) 부위에 두껍게 형성하므로 즉 산소 이온이 많이 주입된 상기 트렌치 상부는 두꺼운 산화막이 자라고, 하부에는 조금 자라게 된다.As shown in FIG. 2E, the field oxide film 37 is formed by reacting the second oxide film 36 with the semiconductor substrate 11 by applying heat to the entire surface including the second oxide film 36 subjected to the etch back process. Next, the nitride film 33 and the first oxide film 32 are removed. In this case, the field oxide film 37 is formed thicker in the oxygen ion implantation region 35 than in other regions. That is, the upper portion of the trench in which much oxygen ions are implanted grows in a thick oxide film and slightly grows in the lower portion.
상기와 같은 본 발명의 격리막 형성 방법은 불순물 영역을 형성하는 후 공정시 상부가 두꺼운 필드 산화막에 의해 수직적으로 확산하여 채널이 길어지게 된다.In the isolation film forming method of the present invention as described above, during the process of forming the impurity region, the channel is lengthened by vertical diffusion by the thick field oxide film at the top.
더불어 상기 트렌치 바닥 형태가 둥글기 때문기 측벽 반전(Side-wall Inversion) 현상을 개선하며 전기장이 감소되고, 또한 산소의 산화과정에서 발생하는 부피 증가로 인해 보이드가 없어진다.In addition, since the trench bottom shape is round, the side wall inversion is improved, the electric field is reduced, and the void is eliminated due to the volume increase generated during the oxidation of oxygen.
그리고 상기 필드 산화막이 활성 영역에 비해 높이 위치하기 때문에 험프(Hump)현상이 개선된다.In addition, since the field oxide layer is positioned higher than the active region, the hump phenomenon is improved.
본 발명의 격리막 형성 방법은 트렌치에 산소 이온을 틸트 이온 주입 시키고 필링 물질을 산화시킴으로 보이드가 없어지고, 전기장이 감소되는 효과가 있다.According to the method of forming a separator of the present invention, voids are eliminated and electric fields are reduced by injecting oxygen ions into the trenches and oxidizing the filling material.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960054629A KR100232191B1 (en) | 1996-11-16 | 1996-11-16 | Method of forming a device isolation film of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960054629A KR100232191B1 (en) | 1996-11-16 | 1996-11-16 | Method of forming a device isolation film of semiconductor device |
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| KR19980036132A true KR19980036132A (en) | 1998-08-05 |
| KR100232191B1 KR100232191B1 (en) | 1999-12-01 |
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| KR (1) | KR100232191B1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010060988A (en) * | 1999-12-28 | 2001-07-07 | 박종섭 | Manufacturing method for isolation in semiconductor device |
| KR20030086853A (en) * | 2002-05-07 | 2003-11-12 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device |
| KR100710191B1 (en) * | 2005-12-28 | 2007-04-20 | 동부일렉트로닉스 주식회사 | Method for fabricating semiconductor device |
| KR100873355B1 (en) * | 2002-07-04 | 2008-12-10 | 매그나칩 반도체 유한회사 | Method for forming the Isolation Layer of Semiconductor Device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR930008843B1 (en) * | 1990-09-13 | 1993-09-16 | 금성일렉트론 주식회사 | Trench isolating region forming method |
| JPH08213382A (en) * | 1995-02-02 | 1996-08-20 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
-
1996
- 1996-11-16 KR KR1019960054629A patent/KR100232191B1/en not_active IP Right Cessation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010060988A (en) * | 1999-12-28 | 2001-07-07 | 박종섭 | Manufacturing method for isolation in semiconductor device |
| KR20030086853A (en) * | 2002-05-07 | 2003-11-12 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device |
| KR100873355B1 (en) * | 2002-07-04 | 2008-12-10 | 매그나칩 반도체 유한회사 | Method for forming the Isolation Layer of Semiconductor Device |
| KR100710191B1 (en) * | 2005-12-28 | 2007-04-20 | 동부일렉트로닉스 주식회사 | Method for fabricating semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100232191B1 (en) | 1999-12-01 |
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