KR102608142B1 - Semiconductor device and lighting module having thereof - Google Patents

Abstract

The embodiment relates to a semiconductor device.
The semiconductor device disclosed in the embodiment includes a first superlattice layer having a first layer and a second layer; a second superlattice layer having a third and fourth layer on the first superlattice layer; a first semiconductor layer between the first and second superlattice layers; a first conductive semiconductor layer on the second superlattice layer; an active layer on the first conductive semiconductor layer; and a second conductive semiconductor layer on the active layer, wherein the number of pairs of the first and second layers of the first superlattice layer is smaller than the number of pairs of the third and fourth layers of the second superlattice layer, and the number of pairs of the first and second layers of the first superlattice layer is smaller than the number of pairs of the third and fourth layers of the second superlattice layer. The layer includes a binary semiconductor with aluminum, the third layer includes a ternary semiconductor with aluminum, the second and fourth layers include a binary semiconductor with gallium, and the second layer includes the ternary semiconductor with aluminum. It has a thickness greater than the thickness of the first layer, the fourth layer has a thickness greater than the thickness of the third layer, and the first semiconductor layer and the first conductive semiconductor layer are ternary semiconductors having the same aluminum composition. It includes, and the first semiconductor layer has a thickness smaller than the thickness of the first conductive semiconductor layer.

Description

Semiconductor device and light source module equipped with the same {SEMICONDUCTOR DEVICE AND LIGHTING MODULE HAVING THEREOF}

The embodiment relates to a semiconductor device.

The embodiment relates to an ultraviolet semiconductor device.

The embodiment relates to a semiconductor device package having an ultraviolet semiconductor device.

In general, nitride semiconductor materials containing a group V source such as nitrogen (N) and a group III source such as gallium (Ga), aluminum (Al), or indium (In) have excellent thermal stability and provide direct transition energy. Because it has a band structure, it is widely used as a material for nitride-based semiconductor devices, such as nitride-based semiconductor light-emitting devices in the ultraviolet region and solar cells.

Nitride-based materials have a wide energy band gap of 0.7 eV to 6.2 eV and are widely used as materials for solar cell devices due to their characteristics matching the solar spectrum region. In particular, ultraviolet light-emitting devices are used in various industrial fields such as curing devices, medical analyzers, treatment devices, sterilization, water purification, and purification systems, and are attracting attention as a material that can be used in general lighting as a semiconductor lighting light source in the future.

The embodiment provides a semiconductor device having a plurality of superlattice layers below the first conductive semiconductor layer.

The embodiment provides a semiconductor device capable of reducing defects by disposing a plurality of superlattice layers between the first conductive semiconductor layer and the substrate.

An embodiment provides a semiconductor device in which a plurality of superlattice layers have different aluminum compositions.

The embodiment provides a semiconductor device in which buffer layers are disposed on different superlattice layers.

An embodiment provides a semiconductor device that emits ultraviolet wavelengths, such as UV (Ultraviolet) wavelengths.

Embodiments provide a semiconductor device package having a semiconductor device that emits ultraviolet light.

A semiconductor device according to an embodiment includes a first superlattice layer having a first layer and a second layer; a second superlattice layer having a third and fourth layer on the first superlattice layer; a first semiconductor layer between the first and second superlattice layers; a first conductive semiconductor layer on the second superlattice layer; an active layer on the first conductive semiconductor layer; and a second conductive semiconductor layer on the active layer, wherein the number of pairs of the first and second layers of the first superlattice layer is smaller than the number of pairs of the third and fourth layers of the second superlattice layer, and the number of pairs of the first and second layers of the first superlattice layer is smaller than the number of pairs of the third and fourth layers of the second superlattice layer. The layer includes a binary semiconductor with aluminum, the third layer includes a ternary semiconductor with aluminum, the second and fourth layers include a binary semiconductor with gallium, and the second layer includes the ternary semiconductor with aluminum. It has a thickness greater than the thickness of the first layer, the fourth layer has a thickness greater than the thickness of the third layer, and the first semiconductor layer and the first conductive semiconductor layer are ternary semiconductors having the same aluminum composition. and the first semiconductor layer has a thickness smaller than the thickness of the first conductive semiconductor layer.

A light source module according to an embodiment includes a body having a cavity; a semiconductor device disposed within the cavity; a transparent window on the cavity; and a moisture-proof film disposed on the transparent window and the body, wherein the semiconductor device includes: a first superlattice layer having a first layer and a second layer; a second superlattice layer having a third and fourth layer on the first superlattice layer; a first semiconductor layer between the first and second superlattice layers; a first conductive semiconductor layer on the second superlattice layer; an active layer on the first conductive semiconductor layer; and a second conductive semiconductor layer on the active layer; a first electrode connected to the first conductive semiconductor layer; It includes a second electrode connected to the second conductive semiconductor layer, wherein the number of pairs of the first and second layers of the first superlattice layer is smaller than the number of pairs of the third and fourth layers of the second superlattice layer, The first layer contains a binary semiconductor containing aluminum, the third layer contains a ternary semiconductor containing aluminum, the second and fourth layers contain a binary semiconductor containing gallium, and the second layer contains a binary semiconductor containing gallium. has a thickness greater than the thickness of the first layer, the fourth layer has a thickness greater than the thickness of the third layer, and the first semiconductor layer and the first conductive semiconductor layer are ternary systems having the same aluminum composition. It includes a semiconductor, and the first semiconductor layer may have a thickness smaller than the thickness of the first conductive semiconductor layer.

According to an embodiment, the first semiconductor layer may have the same aluminum composition as the aluminum composition of the third layer.

According to an embodiment, the stress difference between the first and second layers may be greater than the stress difference between the third and fourth layers.

According to an embodiment, the first and second layers include an unintentional doping layer or an undoped layer, and the third and fourth layers include an unintentional doping layer. It includes a doping layer or an undoped layer, and the first semiconductor layer may include an unintentional doping layer or an undoped layer.

According to an embodiment, the ratio difference between the thicknesses of the first semiconductor layer and the first conductive semiconductor layer may be smaller than the ratio difference between the thicknesses of the first and second layers.

According to an embodiment, the thickness ratio of the first semiconductor layer and the first conductive semiconductor layer may be 1:2 to 3, and the thickness ratio of the first and second layers may be 1:3 to 4.

According to an embodiment, the method of claim 4 includes a substrate and a nitride semiconductor layer on the substrate, and the first superlattice layer may be disposed between the nitride semiconductor layer and the substrate. The nitride semiconductor layer may include a GaN template.

According to an embodiment, the first semiconductor layer, the third layer of the second superlattice layer, and the first conductive semiconductor layer may contain 15% to 20% of aluminum.

According to an embodiment, the active layer may emit ultraviolet rays with a wavelength of 330 nm to 350 nm.

In an embodiment, stress can be reduced by disposing a plurality of superlattice layers under the first conductive semiconductor layer.

The embodiment has the effect of absorbing and removing defects by arranging a thick single-layer semiconductor layer between a plurality of superlattice layers.

According to the semiconductor device according to the embodiment, defects transmitted to the active layer can be removed.

According to the semiconductor device according to the embodiment, internal quantum efficiency can be improved.

The embodiment can improve the reliability of ultraviolet semiconductor devices for sterilization.

Embodiments may provide a semiconductor device package or an ultraviolet lamp having an ultraviolet semiconductor device.

1 is a diagram showing a semiconductor device according to an embodiment.
FIG. 2 is a diagram for explaining a plurality of superlattice layers and a plurality of buffer layers of FIG. 1.
Figure 3 is another example of the semiconductor device of Figure 1.
Figure 4 is an example of electrode placement in the semiconductor device of Figure 1.
Figure 5 is another example of electrode placement in the semiconductor device of Figure 1.
Figure 6 is another example of electrode placement in the semiconductor device of Figure 1.
7 is a cross-sectional view showing a semiconductor device package including a semiconductor device according to an embodiment.
Figure 8 is a diagram showing an example of a light source module having a semiconductor device according to an embodiment.
Figure 9 is a diagram comparing peak wavelengths according to Examples and Comparative Examples.
Figure 10 is a diagram comparing the surfaces of semiconductor devices according to Examples (C and D) and Comparative Examples (A and B).

The present embodiments may be modified in other forms or various embodiments may be combined with each other, and the scope of the present invention is not limited to each embodiment described below.

Even if matters described in a specific embodiment are not explained in other embodiments, they may be understood as descriptions related to other embodiments, as long as there is no explanation contrary to or contradictory to the matter in the other embodiments.

For example, if a feature for configuration A is described in a specific embodiment and a feature for configuration B is described in another embodiment, the description is contrary or contradictory even if an embodiment in which configuration A and configuration B are combined is not explicitly described. Unless otherwise stated, it should be understood as falling within the scope of the rights of the present invention.

Hereinafter, embodiments of the present invention that can specifically realize the above object will be described with reference to the attached drawings.

In the description of the embodiment according to the present invention, in the case where each element is described as being formed "on or under", (or under) includes both elements that are in direct contact with each other or one or more other elements that are formed (indirectly) between the two elements. Additionally, when expressed as "on or under," it can include not only the upward direction but also the downward direction based on one element.

Semiconductor devices may include various electronic devices such as light-emitting devices, light-receiving devices, light modulators, and gas sensors. Although the embodiment describes a gas sensor as an example, it is not limited to this and can be applied to various fields of electrical devices.

<Semiconductor device>

FIG. 1 is a cross-sectional view of a light emitting device according to an embodiment, and FIG. 2 is a detailed configuration diagram of a superlattice layer and a buffer layer of the semiconductor device of FIG. 1.

1 and 2, the semiconductor device according to the embodiment includes a plurality of superlattice layers 31 and 35, a first semiconductor layer 33, a first conductive semiconductor layer 41, an active layer 51, and a first conductive semiconductor layer 51. It may include a two-conducting semiconductor layer (71).

The semiconductor device may include a substrate 21 and a nitride semiconductor layer 25. The nitride semiconductor layer 25 may be disposed on the substrate 21 . The nitride semiconductor layer 25 may be disposed between the substrate 21 and the plurality of superlattice layers 31 and 35. The plurality of superlattice layers 31 and 35 include first and second superlattice layers 31 and 35 disposed in different regions, and the first semiconductor layer 33 includes first and second superlattice layers. It can be placed between (31,35). In the semiconductor device according to the embodiment, the nitride-based semiconductor layers 25-71 stacked on the substrate 21 may include at least two types of nitride semiconductors.

The semiconductor device emits light of ultraviolet wavelength. The semiconductor device may emit light below a wavelength of 400 nm, for example, in the range of 320 nm to 400 nm or in the range of 330 nm to 350 nm. The semiconductor device may be a device that emits UV-A wavelength. The semiconductor device having the UV-A wavelength is used for industrial UV curing, printing ink curing or exposure equipment, is a counterfeit detection or counterfeit detection lamp, is a lamp for purification, water purification, sterilization, or special lighting used in aquariums or agriculture. It can be applied selectively among the same lamps.

<Substrate (21)>

The substrate 21 may be, for example, a light-transmitting, conductive, or insulating substrate. For example, the substrate 21 is AlN, Al ₂ O ₃ , SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, and Ga ₂ O ₃ It may include at least one of: The substrate 21 may be, for example, an AlN template. A plurality of protrusions (not shown) may be formed on the upper and/or lower surface of the substrate 21, and each of the plurality of protrusions has a side cross-section that includes at least one of a hemispherical shape, a polygonal shape, and an elliptical shape, and has a stripe shape. It can be arranged in a shape or matrix form. The protrusion can improve light extraction efficiency. The sapphire is a crystal with hexa-Rhombo R3c symmetry, with lattice constants in the c- and a-axis directions of 13.001 Å and 4.758 Å, and C (0001) plane, A (1120) plane, and R (1102). ) side, etc. In this case, the C surface is mainly used as a substrate for the growth of nitride semiconductors because it is relatively easy to grow a nitride thin film and is stable at high temperatures.

The substrate 21 may have a thickness of 500 μm or less, for example, in the range of 30 μm to 500 μm, and may be formed of a material with a refractive index of 2.4 or less, for example, 2 or less. The length of adjacent sides of the substrate 21 may be the same or different from each other, and the length of at least one side may be 0.3 mm x 0.3 mm or more, or it may be provided in a large size, for example, 1 mm x 1 mm or more. . When viewed from above, the substrate 20 may be formed in a polygonal shape such as a square or hexagon, but is not limited thereto.

A plurality of compound semiconductor layers may be grown on the substrate 21, and equipment for growing the plurality of compound semiconductor layers includes an electron beam evaporator, physical vapor deposition (PVD), chemical vapor deposition (CVD), and plasma laser deposition (PLD). , dual-type thermal evaporator, sputtering, MOCVD (metal organic chemical vapor deposition), etc., but is not limited thereto.

<Nitride semiconductor layer (25)>

For example, the nitride semiconductor layer 25 may include at least one of group II-VI and group III-V compound semiconductors. The nitride semiconductor layer 25 may include a nitride-based template, for example, a GaN template or an AlN-based template. The thickness of the nitride semiconductor layer 25 may be thicker than the thickness of the first conductive semiconductor layer 41. The nitride semiconductor layer 25 may be formed to have a thickness of 3 ㎛ or more, for example, in the range of 3 ㎛ to 5 ㎛. The nitride semiconductor layer 25 may include an unintentional doping layer or an undoped layer.

By disposing the nitride semiconductor layer 25, which is a GaN template, on the substrate 21, the occurrence of cracks between the substrate 21 and the first conductive semiconductor layer 41 containing aluminum can be suppressed. By forming the nitride semiconductor layer 25 to the above thickness on the substrate 21, the propagation of defects due to a difference in lattice constant with the substrate 21 can be reduced. The substrate 21 and the nitride semiconductor layer 25 may be removed. In order to separate the nitride semiconductor layer 25, the first layer (11 in FIG. 2) of the first superlattice layer 31 in contact with the nitride semiconductor layer 25 is connected to the nitride semiconductor layer 25. It can be formed of a material with a large difference in lattice constant or band gap. When a laser is irradiated to the interface between the nitride semiconductor layer 25 and the first layer 11, the nitride semiconductor layer 25 may be separated from the first layer 11 due to a difference in lattice constants.

<Superlattice layer (31,35)>

The plurality of superlattice layers 31 and 35 may include at least two superlattice layers or more superlattice layers. Each of the plurality of superlattice layers 31 and 35 may include at least two different layers as one pair and may include a plurality of pairs. One layer of each pair of the plurality of superlattice layers 31 and 35 may be implemented as, for example, a group II-VI or group III-V compound semiconductor, and the other layer may be implemented as a group II-VI compound semiconductor, for example. It can be implemented as a group or group III-V compound semiconductor.

At least one first semiconductor layer 33 may be disposed between the plurality of superlattice layers 31 and 35. The first semiconductor layer 33 may be implemented as a group II-VI or group III-V compound semiconductor, and may have the same aluminum composition as any one of the layers of the superlattice layers 31 and 35. .

The superlattice layers 31 and 35 may be disposed on the substrate 21 or the nitride semiconductor layer 25. The superlattice layers 31 and 35 may have at least two types of superlattice structures arranged at different positions. The superlattice layers 31 and 35 may include a first superlattice layer 31 on the nitride semiconductor layer 25 and a second superlattice layer 35 on the first superlattice layer 31. . The first and second superlattice layers 31 and 35 may be spaced apart from each other or may not contact each other.

Referring to FIG. 2, the first superlattice layer 31 includes a first layer 11 and a second layer 12, and a pair of the first layer 11 and the second layer 12 ( pair) may be periodically repeated with 5 pairs or less, for example, 2 to 4 pairs. The first and second layers 11 and 12 may be formed of different binary or higher semiconductors, for example, different binary semiconductors. The first superlattice layer 31 may alternately repeat different nitride-based semiconductor layers. The first layer 11 may be formed of a nitride semiconductor containing aluminum, for example, an AlN-based semiconductor, such as an AlN semiconductor. The first layer 11 may be formed of a semiconductor that does not contain In or Ga elements. The second layer 12 is disposed on the first layer 11 and may be formed of a GaN-based semiconductor or a GaN semiconductor. The first layer 11 disposed on the nitride semiconductor layer 25 in the first superlattice layer 31 may be formed of a material having a large difference in lattice constant from the nitride semiconductor layer 25. Accordingly, compressive stress may be applied when the first layer 11 is grown, and tensile stress may be applied when the second layer 12 is grown on the first layer 11. do. By periodically repeating the first layer 11 and the second layer 12, the opposing stresses have the effect of canceling out the compressive stress and the extensional stress. The first superlattice layer 31 can offset the stress propagated through the substrate 21/nitride semiconductor layer 25 through the compressive stress and the tensile stress, and can reduce the occurrence of cracks.

The first and second layers 11 and 12 may be formed as unintentional layers or undoped layers that are not doped with a dopant of the first conductivity type. By not doping the first superlattice layer 31 with a dopant, quality defects due to dopant back diffusion into the nitride semiconductor layer 25 can be eliminated.

In the first superlattice layer 31, the first layer 11/second layer 12 has AlN/GaN pairs, and for example, the number of pairs may include 2 to 4 pairs.

In the first superlattice layer 31, the first layer 11 has a first thickness T1, and the second layer 12 has a second thickness T2 thicker than the first thickness T1. You can. The first thickness (T1) may be smaller than the second thickness (T2) and may be 10 nm or less for a superlattice function. The first thickness T1 of the first layer 11 is thinner than the second thickness T2 of the second layer 12, so that the first layer 11 disposed on the nitride semiconductor layer 25 Compressive stress caused by the material can be effectively applied. The ratio of the first thickness (T1) and the second thickness (T2) may be a ratio of 1:3 to 1:4, and if the ratio of the first and second thicknesses (T1:T2) is less than the above range, the stress The suppression of is slight and if it is greater than the above ratio, it may not perform its function as a superlattice. The first thickness T1 of the first layer 11 may be 8 nm or less, for example, in the range of 4 nm to 8 nm. The second thickness T2 of the second layer 12 may be 20 nm or less, for example, in the range of 10 nm to 20 nm.

In the first superlattice layer 31, the pairs of the first and second layers 11 and 12 are arranged higher than the number of stacked pairs of the second superlattice layer 35, so that defects rising toward the substrate It can reduce stress. Here, the number of pairs of the first superlattice layer 31 may be one pair or more than the number of pairs of the second superlattice layer 35. The thickness of the first superlattice layer 31 may be thicker than the thickness of the second superlattice layer 35.

The first superlattice layer 31 may be disposed between the first semiconductor layer 33 and the nitride semiconductor layer 25 or the substrate 21. The first superlattice layer 31 may be disposed closer to the substrate 21 than the second superlattice layer 35.

The second superlattice layer 35 may be disposed closer to the active layer 51 than the first superlattice layer 31. The second superlattice layer 35 may be disposed between the first semiconductor layer 33 and the first conductive semiconductor layer 41.

The second superlattice layer 35 includes a third layer 13 and a fourth layer 14, and the number of pairs of the third layer 13 and the fourth layer 14 is 5 pairs or less, for example, 2 pairs. It can be repeated periodically with up to 3 pairs. The third and fourth layers 13 and 14 may include different binary or more semiconductors. The third layer 13 may be formed of a ternary semiconductor, and the fourth layer 14 may be formed of a binary semiconductor. The third and fourth layers 13 and 14 may be formed of a nitride semiconductor. The third and fourth layers 13 and 14 may be formed as an unintentionally doped layer or an undoped layer without dopant for crystal quality. Since the third and fourth layers 13 and 14 are not doped with dopants, it is possible to prevent them from affecting the crystal quality of the first buffer layer or the crystal quality of the first conductive semiconductor layer 41.

The third layer 13 may be formed of a semiconductor different from the first layer 11 of the first superlattice layer 31. The third layer 13 may have a lower aluminum composition than the aluminum composition of the first layer 11. The third layer 13 may be formed of a ternary semiconductor containing aluminum, for example, AlGaN. For example, the third layer 13 may be a semiconductor having a composition formula of Al _x Ga _{1 -x} N (0.15≤x≤0.2). The third layer 13 may be formed of the same semiconductor as the first semiconductor layer 33 and the first conductive semiconductor layer 41. Since the aluminum content of the third layer 13, the first semiconductor layer 33, and the first conductive semiconductor layer 41 is the same, the absorption loss for light emitted from the active layer 51, such as ultraviolet light, is reduced. It can be reduced. The third layer 13 may have a composition of aluminum that is 50% or more lower than that of the first layer 11. Since the aluminum composition of the third layer 13 is lower than that of the first layer 11, the surface crystal quality of the nitride semiconductor can be improved.

Since the third layer 13 is formed of the same semiconductor as the first semiconductor layer 33, the difference in lattice constant with the first semiconductor layer 33 can be eliminated and the occurrence of cracks can be reduced.

The fourth layer 14 may include a GaN-based semiconductor or a GaN semiconductor. The fourth layer 14 may be formed of a binary semiconductor different from the third layer 13. The fourth layer 14 may be formed of a semiconductor that does not contain aluminum or indium. The third layer 13 may include an AlGaN semiconductor, and the fourth layer 14 may include a GaN semiconductor. After forming the third layer 13, tensile stress is applied when the fourth layer 14 is grown, and after the growth of the fourth layer 14, compressive stress is applied when the third layer 13 is grown ( compressive stress occurs. Accordingly, as the third and fourth layers 13 and 14 are periodically and repeatedly grown, the opposing compressive stress and stretching stress cancel each other out, thereby canceling out the stress coming from the substrate direction and reducing the occurrence of cracks. I can give it.

In the second superlattice layer 35, the number of pairs of the third and fourth layers 13 and 14 may be 5 pairs or less. The pairs of the third layer 13 and the fourth layer 14 may include 2 or more pairs, for example, 2 to 3 pairs. Since the number of stacked pairs of the second superlattice layer 35 is arranged less than the number of stacked pairs of the first superlattice layer 31, remaining stress or cracks can be removed. Here, the pair of the second superlattice layer 35 may be one pair or more smaller than the pair of the first superlattice layer 31. The thickness of the second superlattice layer 35 may be thinner than the thickness of the first superlattice layer 31. _The second superlattice layer 35 includes the third layer 13/ _fourth layer ₁₄ having _Al may include 2 to 3 pairs.

In the second superlattice layer 35, the third layer 13 has a third thickness T3, and the fourth layer 14 has a fourth thickness T4 thicker than the third thickness T3. You can. The third thickness T3 may be smaller than the fourth thickness T4 and may be 10 nm or less for a superlattice function. The third layer 13 is disposed on the first semiconductor layer 33 by making the third thickness T3 of the third layer 13 thinner than the fourth thickness T4 of the fourth layer 14. /The stress caused by the fourth layer 14 can be effectively applied. The ratio (T3:T4) of the third thickness (T3) and the fourth thickness (T4) may be a ratio of 1:3 to 1:4, and the ratio of the third and fourth thicknesses (T3:T4) may be If it is smaller than the range, suppression of stress is minimal, and if it is larger than the above ratio, it may not perform its function as a superlattice. The third thickness T3 of the third layer 13 may be 10 nm or less, for example, in the range of 5 nm to 10 nm. The fourth thickness T4 of the fourth layer 14 may be 20 nm or less, for example, in the range of 10 nm to 20 nm. The third thickness T3 of the third layer 13 may be equal to or thicker than the first thickness T1 of the first layer 11.

Here, the stress difference between the first and second layers (11, 12) of the first superlattice layer (31) is the stress difference between the third and fourth layers (13, 14) of the second superlattice layer (35). It can be bigger than This is because the first superlattice layer 31 located in a direction close to the substrate 21 has a large stress difference between layers, and thus stress coming from the substrate direction can be effectively removed.

<First semiconductor layer (33)>

The first semiconductor layer 33 may be disposed between different superlattice layers 31 and 35. The first semiconductor layer 33 may be disposed between the first and second superlattice layers 31 and 35. The first semiconductor layer 33 may be in contact with the upper surface of the first superlattice layer 31 and the lower surface of the second superlattice layer 35. The first semiconductor layer 33 may be in contact with the upper surface of the second layer 12 of the first superlattice layer 31 and the lower surface of the third layer 13 of the second superlattice layer 35. The first semiconductor layer 33 has a large thickness T5 between the first and second superlattice layers 31 and 35 and can serve as a first buffer that absorbs and removes defects. This is done by first removing stress from the first superlattice layer 31, then forming the first semiconductor layer 33 to a predetermined thickness (T5), improving the semiconductor crystal quality, and then forming the second superlattice layer 35. This can provide a structure that eliminates secondary stress.

The first semiconductor layer 33 may have a thickness T5 greater than the thickness of the first superlattice layer 31. The thickness T5 of the first semiconductor layer 33 may be 20 times or more, for example, 20 to 30 times thicker than the thickness of the first superlattice layer 31. Since the thickness T5 of the first semiconductor layer 33 is disposed within the above range, a semiconductor with reduced cracks and defects can be provided. The first semiconductor layer 33 may be formed to have a thickness (T5) of 450 nm or more, for example, 450 nm to 550 nm. The first semiconductor layer 33 may be formed thinner than the thickness T6 of the first conductive semiconductor layer 41, and may be 0.5 times or less than the thickness T6 of the first conductive semiconductor layer 41. .

The difference in the thickness ratio (T5/T6) of the first semiconductor layer 33 and the first conductive semiconductor layer 41 is the difference in the thickness ratio (T1/T2) between the first and second layers 11 and 12. ) and may be smaller than the ratio difference (T3/T4) of the thicknesses of the third and fourth layers 13 and 14.

The first semiconductor layer 33 may include a ternary or higher nitride semiconductor. The first semiconductor layer 33 may be formed of a semiconductor different from the second layer 12 of the first superlattice layer 31. The first semiconductor layer 33 may have an aluminum composition lower than that of the first layer 11 . The first semiconductor layer 33 may be formed of a ternary semiconductor containing aluminum, for example, AlGaN. For example, the first semiconductor layer 33 may be a semiconductor having a composition formula of Al _x Ga _{1 - x} N (0.15≤x≤0.2). The first semiconductor layer 33 may be formed of the same semiconductor as the third layer 13 of the second superlattice layer 35 and the first conductive semiconductor layer 41. Since the first semiconductor layer 33 has the same aluminum content as the third layer 13 and the first conductive semiconductor layer 41, there is an absorption loss for light emitted from the active layer 51, such as ultraviolet light. can reduce. The first semiconductor layer 33 may have a composition of aluminum that is 50% or more lower than that of the first layer 11. Since the first semiconductor layer 33 has a lower aluminum composition and a thicker thickness (T5) than the first layer 11, the surface crystal quality of the nitride semiconductor can be improved.

The first semiconductor layer 33 may be formed as an unintentionally doped layer or an undoped layer without dopant. Here, the first superlattice layer 31, the first semiconductor layer 33, and the second superlattice layer 35 may be implemented as layers that are not doped with n-type dopant or p-type dopant. Since the first semiconductor layer 33 is not doped with a dopant, the surface quality can be improved, and the crystal quality of the first superlattice layer 31 and the first conductive semiconductor layer 41 can be improved.

<First conductive semiconductor layer (41)>

The first conductive semiconductor layer 41 may be disposed on a plurality of superlattice layers 31 and 35. The first conductive semiconductor layer 41 may be disposed between the plurality of superlattice layers 31 and 35 and the active layer 51. The first conductive semiconductor layer 41 may be in contact with the upper surface of the second superlattice layer 35. The first conductive semiconductor layer 41 may be in contact with the upper surface of the fourth layer 14 of the second superlattice layer 35. When the active layer 51 is disposed on the first conductive semiconductor layer 41, the first conductive semiconductor layer 41 may be in contact with the active layer 51.

The first conductive semiconductor layer 41 may function as a second buffer disposed between the second superlattice layer 35 and the active layer 51. This means that the first conductive semiconductor layer 41 is provided with a large thickness (T6) to remove stress from the first and second superlattice layers (31, 35) and to reduce defects that can propagate to the thickness (T6). By removing and improving the semiconductor crystal quality, the internal quantum efficiency of the active layer 51 can be improved.

The first conductive semiconductor layer 41 may have a thickness T6 greater than the thickness of the second superlattice layer 35. The thickness T6 of the first conductive semiconductor layer 41 may be at least 40 times thicker than the thickness of the second superlattice layer 35, for example, 40 to 60 times thicker. Since the first conductive semiconductor layer 41 is disposed thick within the above range, a semiconductor with reduced cracks and defects can be provided. The first conductive semiconductor layer 41 may be formed to have a thickness (T6) of 900 nm or more, for example, 900 nm to 1500 nm. The thickness ratio (T6:T5) of the first conductive semiconductor layer 41 and the first semiconductor layer 33 may be 2 to 3:1. The T6 may be 2 to 3 times thicker than T5.

The first conductive semiconductor layer 41 may include a ternary or higher nitride semiconductor. The first conductive semiconductor layer 41 may be formed of a semiconductor different from the fourth layer 14 of the second superlattice layer 35. The first conductive semiconductor layer 41 may have an aluminum composition lower than that of the first layer 11. The first conductive semiconductor layer 41 may be formed of a ternary semiconductor containing aluminum, for example, AlGaN. For example, the first conductive semiconductor layer 41 may be a semiconductor with a composition formula of Al _x Ga _{1 - x} N (0.15≤x≤0.2). The first conductive semiconductor layer 41 may be formed of the same semiconductor as the third layer 13 of the second superlattice layer 35. Since the first conductive semiconductor layer 41 is disposed to have the same aluminum content as the third layer 13 and the first semiconductor layer 33, it absorbs light emitted from the active layer 51, such as ultraviolet light. It can reduce losses. Here, ultraviolet light may include a wavelength of 330 nm to 350 nm. The first conductive semiconductor layer 41 may have a composition of aluminum that is 50% or more lower than that of the first layer 11. Since the first conductive semiconductor layer 41 has a lower aluminum composition and a thicker thickness (T6) than the first layer 11, the surface crystal quality of the nitride semiconductor can be improved.

The first conductive semiconductor layer 41 may include a dopant. The dopant may include a first conductivity type dopant, such as an n-type dopant such as Si, Ge, Sn, Se, or Te. The first conductive semiconductor layer 41 may be formed as a single layer or multilayer, but is not limited thereto. The first conductive semiconductor layer 41 may be a layer in contact with an electrode. By providing the aluminum of the first conductive semiconductor layer 41 thick with a composition difference of more than 50% from the aluminum composition of AlN, polarization phenomenon and defects transmitted to the active layer 51 can be reduced.

<Active layer (51)>

The active layer 51 may be disposed on the first conductive semiconductor layer 41 . The active layer 51 may generate ultraviolet rays. The active layer 51 may generate UV-A or a wavelength of 330 nm to 350 nm.

The active layer 51 may be formed of at least one of a single well, a single quantum well, a multi-well, a multi quantum well (MQW) structure, a quantum wire structure, or a quantum dot structure. You can. The active layer 51 is formed when electrons (or holes) injected through the first conductive semiconductor layer 41 and holes (or electrons) injected through the second conductive semiconductor layer 71 meet each other, and the active layer ( 51) It is a layer that emits light due to the difference in the band gap of the energy band depending on the forming material. The active layer 51 may be implemented as a compound semiconductor. For example, the active layer 51 may be implemented with at least one of group II-VI and group III-V compound semiconductors.

When the active layer 51 is implemented as a multi-well structure, the active layer 51 includes a plurality of well layers (not shown) and a plurality of barrier layers (not shown). In the active layer 51, well layers and barrier layers are alternately arranged. Pairs of the well layer and the barrier layer may be formed in 2 to 30 cycles. For example, the well layer may be made of a semiconductor material having a composition of In _x Al _y Ga _{1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the barrier layer may be formed of a semiconductor material having a composition of In _x Al _y Ga _1-xy N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). The period of the well layer/barrier layer is, for example, InGaN/GaN, GaN/AlGaN, AlGaN/AlGaN, InGaN/AlGaN, InGaN/InGaN, AlGaAs/GaAs, InGaAs/GaAs, InGaP/GaP, AlInGaP/InGaP, InP /Contains at least one pair of GaAs.

The well layer of the active layer 51 according to the embodiment may be implemented with AlGaN, and the barrier layer may be implemented with AlGaN. The active layer 51 may emit ultraviolet wavelengths, for example, in the range of 330 nm to 350 nm. The aluminum composition of the barrier layer has a higher composition than the aluminum composition of the well layer.

Another semiconductor layer may be disposed above and/or below the active layer 51, for example, an AlN-based or AlGaN-based semiconductor.

<Second conductive semiconductor layer (71)>

The second conductive semiconductor layer 71 is disposed on the active layer 51. The second conductive semiconductor layer 71 may include an AlGaN-based semiconductor. The second conductive semiconductor layer 71 may be a p-type semiconductor layer having a second conductivity type dopant, for example, a p-type dopant. As another example, the second conductive semiconductor layer 71 may include at least one of GaN, AlN, InAlGaN, AlInN, AlGaAs, or AlGaInP, and may include a p-type dopant such as Mg, Zn, Ca, Sr, or Ba. It can be included. This second conductive semiconductor layer 71 may be formed of an AlGaN-based semiconductor to prevent absorption of ultraviolet wavelengths. The second conductive semiconductor layer 71 may be multilayered, but is not limited thereto.

In the embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, as another example, the first conductivity type may be p-type and the second conductivity type may be n-type. Alternatively, the semiconductor device may include any one of an n-p junction structure, a p-n junction structure, an n-p-n junction structure, and a p-n-p junction structure.

In the embodiment, the first superlattice layer 31 is disposed between the nitride semiconductor layer 25, which is a nitride-based template, and the first conductive semiconductor layer 41, thereby minimizing lattice mismatch and defects due to composition differences. . Additionally, by increasing the stress difference between the first layer 11 and the second layer 12 of the first superlattice layer 31, stress coming from the substrate direction can be reduced.

In the embodiment, the first semiconductor layer 33 is provided as an unintentional doping layer or undoped layer with a large thickness (T) between the first and second superlattice layers 31 and 35, thereby preventing defects coming from the substrate direction. Can be absorbed and removed.

The second superlattice layer 35 according to the embodiment is a single-layer first semiconductor layer (T5, T6) between the first semiconductor layer 33 and the first conductive semiconductor layer 41. 33) and the first conductive semiconductor layer 41.

The second superlattice layer 35 according to the embodiment is provided as an unintentional doping layer or undoped layer, thereby minimizing the effect on the crystal quality of the first conductive semiconductor layer 41 and preventing the propagation of cracks or defects. can be blocked.

In the embodiment, the first semiconductor layer 33, the first layer 11 of the second superlattice layer 35, and the first conductive semiconductor layer 41 are Al _x Ga _{1 - x} N (0.15≤x≤0.2 ) By being formed of a semiconductor with a composition formula, it can transmit light of a UV-A wavelength or a wavelength of 330 nm to 350 nm and suppress the occurrence of defects. By providing 5 pairs or less of the first and second superlattice layers 31 and 35, the transmittance to ultraviolet ray wavelengths can be improved.

In the embodiment, by disposing a plurality of superlattice layers 31 and 35 on the substrate 21, defects (dislocations) can be effectively blocked compared to the case of disposing a single n-type semiconductor layer on the substrate 21. , quality degradation due to differences in lattice constants can be prevented.

Reference will be made to FIGS. 9 and 10 for light intensity and crystal quality in the semiconductor device according to the embodiment. Figure 9 is a diagram comparing luminous intensity according to examples and comparative examples. Here, in a comparative example, the semiconductor layer and the second superlattice layer are removed from the semiconductor device of FIG. 1, the first and second layers of the first superlattice layer have 5 pairs, and the first conductive semiconductor layer is formed at 1500 nm. It is a structure. When comparing the peak wavelength of this comparative example with the peak wavelength of the example, it can be seen that there is a difference in luminance in the range of 330 nm to 350 nm. It can be seen that the luminous intensity of ultraviolet wavelengths in the semiconductor device of the example is high.

FIG. 10 is a view showing cracks on the surface as measured using optical microscopes (OM) on the surface of the semiconductor devices of the comparative examples and examples above. 10 (A) and (B) are the surface of the semiconductor device of the comparative example, and (C, D) are images taken by magnifying the surface of the semiconductor device of the example by the same multiple, showing the surface of the semiconductor device of the example compared to the comparative example. It can be seen that the cracks are significantly small. In other words, it can be seen that the long valley-shaped defect shown in the image of the comparative example is removed.

FIG. 3 is another example of the semiconductor device of FIG. 1, and the description of FIG. 1 will be referred to for parts identical to those of FIG. 1.

Referring to FIG. 3, in the semiconductor device, an electron blocking layer 61 may be disposed between the active layer 51 and the second conductive semiconductor layer 71. The electron blocking layer 61 may be disposed on the active layer 51. The electron blocking layer 61 may be made of an AlGaN semiconductor and may have a higher aluminum composition than the barrier layer of the active layer 51. The aluminum composition of the electron blocking layer 61 may be 15% or more. The electron blocking layer 61 is made of a material with a band gap wider than that of the active layer 51, and may be formed as a single layer or multilayer. The multilayer electron blocking layer 61 may include semiconductor layers having different aluminum compositions.

FIG. 4 shows an example of electrode placement in the semiconductor device of FIG. 1. In describing FIG. 3, the description of the embodiment disclosed above will be referred to for parts identical to the configuration disclosed above.

Referring to FIG. 4 , the semiconductor device 101 includes a first electrode 91 and a second electrode 95. The first electrode 91 may be electrically connected to the first conductive semiconductor layer 41, and the second electrode 95 may be electrically connected to the second conductive semiconductor layer 71.

The first electrode 91 may be disposed on the first conductive semiconductor layer 41, and the second electrode 95 may be disposed on the second conductive semiconductor layer 71 or/and the electrode layer 77. You can. At least one or both of the first electrode 91 and the second electrode 95 may further have a current diffusion pattern of an arm structure or a finger structure. The first electrode 91 and the second electrode 95 may be made of a non-transmissive metal having the characteristics of ohmic contact, adhesive layer, and bonding layer, but are not limited thereto. The first electrode 93 and the second electrode 95 are Ti, Ru, Rh, Ir, Mg, Zn, Al, In, Ta, Pd, Co, Ni, Si, Ge, Ag and Au, and a selection thereof. It can be selected from among suitable alloys.

An electrode layer 77 may be disposed between the second electrode 95 and the second conductive semiconductor layer 71, and the electrode layer 77 is a light-transmissive material that transmits more than 50% of light or transmits more than 70% of light. It may be formed of a material with reflective properties, for example, a metal or a metal oxide. The electrode layer is made of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), and AZO. (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), ZnO, IrOx, RuOx, NiO, Al, Ag, Pd, Rh, Pt, and Ir. The electrode layer 77 may have a stacked structure of a light-transmissive layer/reflective metal layer.

The substrate 21 may be provided with a thickness of 20 μm or less in order to reduce absorption of ultraviolet wavelengths. Additionally, the substrate 21 may be separated from the semiconductor device, but this is not limited. The semiconductor device 101 according to the embodiment may emit ultraviolet ray wavelengths, for example, UV-A wavelength or 330 nm to 350 nm.

FIG. 5 is an example of the semiconductor device of FIG. 3 arranged in a flip chip structure.

Referring to FIG. 5, the semiconductor device includes a substrate 21, a plurality of superlattice layers 31 and 35 according to an embodiment, a first semiconductor layer 33, a first conductive semiconductor layer 41, and an active layer 51. , and includes a second conductive semiconductor layer 71.

The substrate 21 may be provided with a thickness of 20 μm or less to minimize light absorption and improve light transmittance. Additionally, a light extraction structure 21A such as roughness may be disposed on the upper surface of the substrate 21. A portion of the light extraction structure 21A may have a polygonal shape, such as a triangle, or a hemispherical shape. The substrate 21 may be a bulk AlN substrate or a sapphire substrate for the growth of AlGaN.

The semiconductor device includes a first electrode 91 and a second electrode 95, where the first electrode 91 may be disposed below the first conductive semiconductor layer 41, and the second electrode ( 95) may be disposed under the second conductive semiconductor layer 71 or/and the electrode layer 77.

The electrode layer 77 includes a contact layer and/or a reflective layer, and the contact layer includes indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), ZnO, IrOx, RuOx, NiO, Al, Ag, Pd , Rh, Pt, Ir, or a plurality of mixed materials, and the reflective layer may include at least one of Al, Ag, Pd, Rh, Pt, and Ir.

This semiconductor device 103 is arranged in a flip structure, so that light can be extracted toward the substrate.

FIG. 6 is a diagram showing an example of a vertical semiconductor device using the semiconductor device of FIG. 1. In describing FIG. 6 , the description of the embodiment disclosed above will be referred to for parts identical to the configuration disclosed above.

Referring to FIG. 6, the semiconductor device 102 includes a plurality of superlattice layers 31 and 35, a first semiconductor layer 33 between the plurality of superlattice layers 31 and 35, and a first electrode 91. The first conductive semiconductor layer 41, the active layer 51, and the second conductive semiconductor layer 71 are disposed. A recess 32 is disposed in the superlattice layers 31 and 35 and the second semiconductor layer 35, and the first electrode 91 may be disposed in the recess 32. The depth of the recess 32 may be a depth at which a portion of the upper surface of the first conductive semiconductor layer 41 is exposed.

A roughness 31A is disposed on the first superlattice layer 31 among the plurality of superlattice layers 31 and 35, and the roughness 31A serves as a light extraction structure and can improve light extraction efficiency. . The roughness 31A is a concavo-convex structure, and the depth of the concavo-convex structure may be a depth at which a portion of the first semiconductor layer 33 is exposed or a depth at which the first semiconductor layer 33 is not exposed.

A second electrode having a plurality of conductive layers 96, 97, 98, and 99 may be disposed under the second conductive semiconductor layer 71. The second electrode may be electrically connected to the second conductive semiconductor layer 71. The second electrode is disposed below the second conductive semiconductor layer 71 and includes a contact layer 96, a reflective layer 97, a bonding layer 98, and a support member 99. The contact layer 96 is in contact with a semiconductor layer, for example, the second conductive semiconductor layer 71. The contact layer 96 may be a low-conductivity material such as ITO, IZO, IZTO, IAZO, IGZO, IGTO, AZO, ATO, or a metal such as Ni or Ag. A reflective layer 97 is disposed below the contact layer 96, and the reflective layer 97 is made of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf, and combinations thereof. It can be formed into a structure comprising at least one layer made of a material selected from the group. The reflective layer 97 may be in contact with the second conductive semiconductor layer 71, but is not limited thereto.

A bonding layer 98 is disposed under the reflective layer 97. The bonding layer 98 may be used as a barrier metal or a bonding metal, and the material may be, for example, Ti, Au, Sn, Ni, Cr, It may include at least one of Ga, In, Bi, Cu, Ag, Ta and optional alloys.

A channel layer 83 and a current blocking layer 85 are disposed between the second conductive semiconductor layer 71 and the second electrode.

The channel layer 83 is formed along the bottom edge of the second conductive semiconductor layer 71 and may be formed in a ring shape, loop shape, or frame shape. The channel layer 83 includes a transparent conductive material or an insulating material, such as ITO, IZO, IZTO, IAZO, IGZO, IGTO, AZO, ATO, SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , It may include at least one of Al ₂ O ₃ and TiO ₂ . The inner portion of the channel layer 163 is disposed below the second conductive semiconductor layer 71, and the outer portion is disposed further outside the side surface of the light emitting structure.

The current blocking layer 85 may be disposed between the second conductive semiconductor layer 71 and the contact layer 96 or the reflective layer 97. The current blocking layer 85 includes an insulating material, such as SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ It may include at least one of them. As another example, the current blocking layer 85 may also be formed of metal for Schottky contact.

The current blocking layer 85 is disposed to correspond to the first electrode 91 in a vertical direction. The current blocking layer 85 can block the current supplied from the second electrode and spread it to other paths. The current blocking layer 85 may be disposed one or more times, and at least a portion or the entire area may overlap the first electrode 91 in a direction perpendicular to the current blocking layer 85 .

A support member 99 is formed under the bonding layer 98. The support member 99 may be made of a conductive member, and the material may be copper (Cu-copper), gold (Au-gold), or nickel. It can be formed of conductive materials such as (Ni-nickel), molybdenum (Mo), copper-tungsten (Cu-W), and carrier wafers (e.g. Si, Ge, GaAs, ZnO, SiC, etc.). As another example, the support member 99 may be implemented as a conductive sheet.

Here, in order to provide the vertical semiconductor device, the substrate 21 of FIG. 1 is removed. As shown in FIG. 5, the method of removing the growth substrate involves irradiating a laser (e.g., KrF) with a predetermined wavelength (248 nm) onto the surface of the substrate 21, and the The interface between the first layer 11 of the first superlattice layer 31 and the nitride semiconductor layer 23 is melted, and the substrate 21 and the nitride semiconductor layer 23 are formed by the melted interface. Can be lifted off. At this time, the wavelength of the laser may not be transmitted by the first superlattice layer 31, thereby protecting the active layer 51.

Then, isolation etching is performed in the direction in which the substrate 21 was removed, and parts of the first superlattice layer 31, the first semiconductor layer 33, and the second superlattice layer 35 are removed. The recess 32 is formed and the first electrode 91 can be formed and separated into individual chips. Accordingly, a semiconductor device 102 having a vertical electrode structure having a first electrode 91 above the light emitting structures 41, 51, and 71 and a support member 99 below can be manufactured. The semiconductor device 102 according to the embodiment may emit ultraviolet wavelengths, for example, UV-A wavelengths.

<Semiconductor device package>

FIG. 7 is a diagram showing a semiconductor device package including the semiconductor device of FIG. 5.

Referring to FIG. 7, the semiconductor device package includes a support member 110, a reflective member 111 having a cavity 112 above the support member 110, and above the support member 110 and within the cavity 112. It includes a semiconductor device 103 according to an embodiment, and a transparent window 115 on the cavity 112.

The support member 110 is a resin-based printed circuit board (PCB), silicon-based such as silicon or silicon carbide (SiC), ceramic-based such as aluminum nitride (AlN), and polyphthalic. It may be formed of at least one of a resin series such as amide (polyphthalamide: PPA), a polymer liquid crystal polymer, or a PCB (MCPCB: Metal core PCB) with a metal layer on the bottom, but is not limited to these materials.

The support member 110 includes a first metal layer 131, a second metal layer 133, a first connection member 138, a second connection member 139, a first electrode layer 135, and a second electrode layer 137. Includes. The first metal layer 131 and the second metal layer 132 are disposed at the bottom of the support member 110 to be spaced apart from each other. The first electrode layer 135 and the second electrode layer 137 are arranged to be spaced apart from each other on the upper surface of the support member 110. The first connection member 138 may be disposed inside or on the first side of the support member 110, and connects the first metal layer 131 and the first electrode layer 135 to each other. The second connection member 139 may be disposed inside or on the second side of the support member 110, and connects the second metal layer 133 and the second electrode layer 137 to each other.

The first metal layer 131, the second metal layer 133, the first electrode layer 135, and the second electrode layer 137 are made of a metal material, for example, titanium (Ti), copper (Cu), and nickel (Ni). , it may be formed of at least one of gold (Au), chromium (Cr), tantalum (Ta), platinum (Pt), tin (Sn), silver (Ag), phosphorus (P), or a selective alloy thereof, It may be formed of a single metal layer or multiple metal layers. The first connection member 138 and the second connection member 139 include at least one of a via, a via hole, and a through hole.

The reflective member 111 is disposed around the cavity 112 on the support member 110 and can reflect ultraviolet light emitted from the semiconductor device 101.

The reflective member 111 is a resin-based printed circuit board (PCB), silicon-based such as silicon or silicon carbide (SiC), ceramic-based such as aluminum nitride (AlN), and polyphthalamide. It may be formed of at least one of a resin series such as (polyphthalamide: PPA) or a polymer liquid crystal polymer, but is not limited to these materials. The support member 110 and the reflective member 111 may include a ceramic-based material, and this ceramic-based material has a higher heat dissipation efficiency than a resin material.

The semiconductor device 103 may be disposed on the first and second electrode layers 135 and 137, on the second electrode layer 137, or on the support member 110. The semiconductor device 103 may be bonded to the first and second electrode layers 135 and 137 using a flip chip method. The semiconductor device 103 is electrically connected to the first electrode layer 135 and the second electrode layer 137. When the semiconductor device 103 has the structure of FIG. 4, it may be connected with a wire. The semiconductor device 101 may emit ultraviolet wavelengths, or when a phosphor layer is disposed on the semiconductor device 101, it may emit light of other wavelengths.

The transparent window 115 is disposed on the cavity 112 and emits the peak wavelength emitted from the semiconductor device 101. This transparent window 115 may include glass, ceramic, or light-transmitting resin. An optical lens or a phosphor layer may be further disposed on the cavity 112, but the present invention is not limited thereto. A semiconductor device or semiconductor device package according to an embodiment may be applied to a light unit. The light unit is an assembly having one or more semiconductor devices or semiconductor device packages, and may include an ultraviolet lamp.

FIG. 8 may provide a light source module having a semiconductor device or a semiconductor device package according to an embodiment. A light source module according to an embodiment may be a light unit.

Referring to FIG. 8, the light source module according to the embodiment includes a semiconductor device package 201 having the semiconductor device 103 disclosed in the embodiment, a circuit board 301 on which the semiconductor device package 201 is disposed, and the semiconductor device. It includes a device package 201 and a moisture-proof film 275 covering the circuit board 301.

The semiconductor device package 201 includes a body 210 having a cavity 211, a plurality of electrodes 221 and 225 disposed in the cavity 211, and a semiconductor device disposed on at least one of the plurality of electrodes 221 and 225. (103), including a transparent window 261 disposed on the cavity 211.

The semiconductor device 103 may include a selective peak wavelength within the range from ultraviolet wavelengths to visible light wavelengths. The semiconductor device 103 may emit, for example, UV-A wavelength, that is, an ultraviolet wavelength in the range of 330nm-350nm.

The body 210 includes an insulating material, such as a ceramic material. The ceramic material includes co-fired low temperature co-fired ceramic (LTCC) or high temperature co-fired ceramic (HTCC). The material of the body 210 may be, for example, AlN, or it may be made of metal nitride with a thermal conductivity of 140 W/mK or more.

The upper circumference of the body 210 includes a step structure 215. The stepped structure 215 is an area lower than the upper surface of the body 210 and is disposed around the upper portion of the cavity 211. The depth of the step structure 215 is the depth from the top surface of the body 210, and may be formed deeper than the thickness of the transparent window 261, but is not limited thereto.

The cavity 211 is an area in which a portion of the upper area of the body 210 is open and may be formed at a predetermined depth from the upper surface of the body 210.

The electrodes 221 and 225 in the cavity 211 and the body 210 may be electrically connected to the electrode pads 241 and 245 disposed on the lower surface of the body 210. The materials of these electrodes 221,225 and electrode pads 241,245 are metals such as platinum (Pt), titanium (Ti), copper (Cu), nickel (Ni), gold (Au), tantalum (Ta), aluminum ( Al) may be optionally included.

The semiconductor device 103 may be mounted on the electrodes 221 and 225 within the cavity 211 using a flip chip method without separate wires. The semiconductor device 103 is an ultraviolet light-emitting diode according to an embodiment having the configuration shown in FIGS. 1 to 3, and may be an ultraviolet semiconductor device having a wavelength in the range of 330 nm to 350 nm.

The transparent window 261 is disposed on the cavity 211. The transparent window 261 includes a glass material, such as quartz glass. Accordingly, the transparent window 261 can be defined as a material that can transmit light emitted from the semiconductor device 103, for example, by ultraviolet wavelengths, without damage such as destruction of bonds between molecules.

The outer circumference of the transparent window 261 is coupled to the stepped structure 215 of the body 210. An adhesive layer 263 is disposed between the transparent window 261 and the step structure 215 of the body 210, and the adhesive layer 263 includes a resin material such as silicone or epoxy.

The transparent window 261 may be spaced apart from the semiconductor device 103. By being spaced apart from the semiconductor device 103, the transparent window 261 can be prevented from expanding due to heat generated by the semiconductor device 103.

The circuit board 301 includes a plurality of bonding pads 304 and 305, and the plurality of bonding pads 304 and 305 may be electrically connected to pads 241 and 245 disposed on the lower surface of the body 210.

The circuit board 301 can be connected to signal cables 311 and 313 through external connection terminals 307 and 308, and the signal cables 311 and 313 supply power from the outside.

The moisture-proof film 275 is disposed on the top and side surfaces of the semiconductor device package 201 and the top surface of the circuit board 301. The moisture-proof film 275 is disposed on the top surface of the transparent window 261 of the semiconductor device package 201 and the top surface and side surface of the body 210. The extension portion 271 of the moisture-proof film 275 is disposed to extend from the side surface of the body 210 to the top surface of the circuit board 301.

The moisture-proof film 275 is a fluororesin-based material, and can transmit light emitted from the semiconductor device 103 without being destroyed by the light. This moisture-proof film 275 may be used as at least one of PCTFE (Polychlorotrifluoroethylene), ETFE (Ethylene + Tetrafluoroethylene), FEP (Fluorinated ethylene propylene copoly-mer), and PFA (Perfluoroalkoxy).

The moisture-proof film 275 can block not only moisture or moisture penetrating into the circuit board 301, but also moisture or moisture penetrating through the side and top surfaces of the semiconductor device package 201. The thickness of the moisture-proof film 275 may be formed in the range of 0.5㎛-10㎛, and if the thickness of the moisture-proof film 275 exceeds the above range, the light transmittance is significantly reduced, and if it is less than the above range, the light transmittance decreases significantly. Habit is poor.

The moisture-proof film 275 may be spaced apart from the bonding area of the external connection terminals 307 and 308 and the signal cables 311 and 313. As another example, the moisture-proof film 275 may cover the external connection terminals 307 and 308. In this case, the moisture-proof film 275 can prevent moisture or moisture from penetrating through the external connection terminals 307 and 308.

The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. illustrated in each embodiment can be combined or modified and implemented in other embodiments by a person with ordinary knowledge in the field to which the embodiments belong. Therefore, contents related to such combinations and modifications should be construed as being included in the scope of the present invention.

In addition, although the above description has been made focusing on the examples, this is only an example and does not limit the present invention, and those skilled in the art will understand the above examples without departing from the essential characteristics of the present embodiment. You will be able to see that various modifications and applications are possible. For example, each component specifically shown in the examples can be modified and implemented. And these variations and differences in application should be construed as being included in the scope of the present invention as defined in the appended claims.

21: substrate
25: Nitride semiconductor layer
31: First superlattice layer
33: First semiconductor layer
35: Second superlattice layer
41; First conductive semiconductor layer
51: active layer
61: Electronic blocking layer
71: Second conductive semiconductor layer

Claims (13)

a first superlattice layer having at least one first layer and at least one second layer;
a second superlattice layer having at least one third layer and at least one fourth layer on the first superlattice layer;
a first semiconductor layer between the first and second superlattice layers;
a first conductive semiconductor layer on the second superlattice layer;
an active layer on the first conductive semiconductor layer; and
It includes a second conductive semiconductor layer on the active layer,
The number of pairs of the first and second layers of the first superlattice layer is smaller than the number of pairs of the third and fourth layers of the second superlattice layer,
The first layer includes a binary semiconductor containing aluminum,
The third layer includes a ternary semiconductor containing aluminum,
The second and fourth layers include a binary semiconductor containing gallium,
The second layer has a thickness greater than the thickness of the first layer,
The fourth layer has a thickness greater than the thickness of the third layer,
The first semiconductor layer and the first conductive semiconductor layer include a ternary semiconductor having the same aluminum composition,
A semiconductor device wherein the first semiconductor layer has a thickness smaller than the thickness of the first conductive semiconductor layer. The semiconductor device of claim 1, wherein the first semiconductor layer has the same aluminum composition as the aluminum composition of the third layer. The semiconductor device of claim 2, wherein a stress difference between the first and second layers is greater than a stress difference between the third and fourth layers. The semiconductor device according to any one of claims 1 to 3, wherein the first layer and the second layer include an unintentional doping layer or an undoped layer. The semiconductor device of claim 4, wherein the third and fourth layers include an unintentional doping layer or an undoped layer. The semiconductor device of claim 5, wherein the first semiconductor layer includes an unintentional doping layer or an undoped layer. The semiconductor device of claim 4, wherein a ratio difference between the thicknesses of the first semiconductor layer and the first conductive semiconductor layer is smaller than a ratio difference between the thicknesses of the first and second layers. The method of claim 4, wherein the thickness ratio of the first semiconductor layer and the first conductive semiconductor layer is 1:2 to 3,
A semiconductor device having a thickness ratio of the first and second layers of 1:3 to 4. The semiconductor device of claim 4, comprising a substrate and a nitride semiconductor layer on the substrate, wherein the nitride semiconductor layer is disposed between the first superlattice layer and the substrate. The semiconductor device of claim 9, wherein the nitride semiconductor layer includes a GaN template. The semiconductor device of claim 4, wherein the first semiconductor layer, the third layer of the second superlattice layer, and the first conductive semiconductor layer contain 15% to 20% aluminum. The semiconductor device of claim 4, wherein the active layer emits ultraviolet rays with a wavelength of 330 nm to 350 nm. a body having a cavity;
a semiconductor device disposed within the cavity;
a transparent window on the cavity; and
It has a moisture-proof film disposed on the transparent window and the body,
The semiconductor device includes a first superlattice layer having at least one first layer and at least one second layer;
a second superlattice layer having at least one third layer and at least one fourth layer on the first superlattice layer;
a first semiconductor layer between the first and second superlattice layers;
a first conductive semiconductor layer on the second superlattice layer;
an active layer on the first conductive semiconductor layer; and
a second conductive semiconductor layer on the active layer;
a first electrode connected to the first conductive semiconductor layer;
It includes a second electrode connected to the second conductive semiconductor layer,
The number of pairs of the first and second layers of the first superlattice layer is smaller than the number of pairs of the third and fourth layers of the second superlattice layer,
The first layer includes a binary semiconductor containing aluminum,
The third layer includes a ternary semiconductor containing aluminum,
The second and fourth layers include a binary semiconductor containing gallium,
The second layer has a thickness greater than the thickness of the first layer,
The fourth layer has a thickness greater than the thickness of the third layer,
The first semiconductor layer and the first conductive semiconductor layer include a ternary semiconductor having the same aluminum composition,
The light source module wherein the first semiconductor layer has a thickness smaller than the thickness of the first conductive semiconductor layer.

Images