KR102137743B1 - Semiconductor device - Google Patents

Abstract

The semiconductor device of the embodiment includes a substrate, a nitride semiconductor layer disposed on the substrate, and a device portion disposed on the nitride semiconductor layer, and the nitride semiconductor layer is disposed on the substrate, and Al _X Ga _{1 -X} N (0≤X<0.3) /Al _Y Ga _{1 -Y} N (0.8<Y≤1) A first superlattice layer portion having a structure in which a superlattice layer pair is overlapped at least once, and at least a GaN or AlGaN layer disposed on the first superlattice layer portion Al _I Ga _{1 -I} N (0.8<I≤1)/Al _J Ga _{1 -J} N(0≤J<0.3) superlattice layer pairs are overlapped at least once. And a second superlattice layer portion having a structure.

Description

Semiconductor device {Semiconductor device}

Embodiments relate to semiconductor devices.

Group III-V compound semiconductors such as gallium nitride (GaN) are widely used in the field of optoelectronics due to many advantages such as having a wide and easily adjustable bandgap energy.

In addition, since GaN has a wide energy bandgap characteristic, it has characteristics suitable for power semiconductor devices such as power switches, such as excellent forward characteristics, high breakdown voltage, and low intrinsic carrier density. As a power semiconductor device, there are a Schottky barrier diode, a metal semiconductor field effect transistor, and a High Electron Mobility Transistor (HEMT).

The semiconductor device used in the above-mentioned photoelectronics field or power semiconductor device has a problem in that convex or concave bending occurs during manufacturing. For example, in a power semiconductor device, a buffer layer (not shown), an undoped GaN layer (not shown), and an AlGaN layer (not shown) are sequentially disposed on a substrate (not shown). At this time, when the thickness of the buffer layer is small, the power semiconductor device is convexly curved, and as the thickness of the undoped GaN layer increases, the power semiconductor device is concavely curved.

The embodiment provides a semiconductor device with reduced warpage.

The semiconductor device of the embodiment includes a substrate; A nitride semiconductor layer disposed on the substrate; And an element portion disposed on the nitride semiconductor layer, wherein the nitride semiconductor layer is disposed on the substrate, and Al _X Ga _{1 -X} N(0≤X<0.3)/Al _Y Ga _{1 -Y} N(0.8<Y ≤1) A first superlattice layer portion having a structure in which a superlattice layer pair is overlapped at least once; At least one insertion layer disposed on the first super-gap layer portion and including GaN or AlGaN; And disposed on the insertion layer, Al _I Ga _{1 -I} N (0.8 <I ≤ ₁ ) / Al _J Ga _{1 -J} N (0 ≤ _J <0.3) superlattice layer pair has a structure at least once overlapped And a second superlattice layer portion.

The insertion layer may be doped by impurities. The impurity may include at least one of iron (Fe), carbon (carbon), or zinc (Zn).

The thickness of the insertion layer may be 100 nm to 300 nm.

The insertion layer may be disposed between 0.2L and 0.8L in the total length (L) of the nitride semiconductor layer.

The aluminum (Al) content ratio of AlGaN included in the insertion layer may be 0.1 or less.

The I and X may be different or the same.

The device portion is a channel layer disposed on the nitride semiconductor layer; An electron supply layer disposed on the channel layer; An electrode portion disposed on the electron supply layer, and the electrode portion includes a gate electrode; A source contact spaced apart from one side of the gate electrode; And a drain contact spaced apart from the other side of the gate electrode.

Alternatively, the device portion may include a first conductivity type semiconductor layer disposed on the nitride semiconductor layer; An active layer disposed on the first conductive semiconductor layer; And a second conductivity type semiconductor layer disposed on the active layer.

The semiconductor device according to the embodiment improves the degree of warping of the wafer by disposing the insertion layer between the first superlattice layer part and the second superlattice layer part, so that the device part is formed thick, so it can have a high breakdown voltage and excellent device characteristics Have

1 is a sectional view showing a semiconductor device according to an embodiment.
2 is a cross-sectional view of a power semiconductor device using the semiconductor device shown in FIG. 1.
3 is a sectional view showing a semiconductor device for a light emitting device according to an embodiment.
4A to 4C are process cross-sectional views illustrating a manufacturing method according to an embodiment of a semiconductor device.
5A and 5B are graphs for describing a bending phenomenon of a semiconductor device according to an embodiment.

Hereinafter, examples will be described to specifically describe the present invention, and the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments according to the present invention may be modified in various other forms, and the scope of the present invention should not be interpreted as being limited to the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art.

In the description of the embodiment according to the present invention, in the case of being described as being formed on "top (top)" or "bottom (bottom)" of each element, the top (top) or bottom (bottom) (on or under) includes both two elements directly contacting each other or one or more other elements formed indirectly between the two elements. In addition, when expressed as “up (up)” or “down (down)” (on or under), it may include the meaning of the downward direction as well as the upward direction based on one element.

In addition, relational terms, such as “first” and “second,” “upper” and “lower”, as used below, do not necessarily require or imply any physical or logical relationship or order between such entities or elements. Thus, it may be used only to distinguish one entity or element from another entity or element.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity. Also, the size of each component does not entirely reflect the actual size.

1 is a sectional view showing a semiconductor device 100 according to an embodiment.

Referring to FIG. 1, the semiconductor device 100 includes a substrate 110, a buffer layer 112, a nitride semiconductor layer 120, and a device unit 130.

The buffer layer 112 is disposed on the substrate 110. The substrate 110 may be a silicon substrate, a silicon carbide substrate, a GaN substrate, or a sapphire substrate, but the embodiment is not limited to the type of the substrate 110. For example, the substrate 110 may be a silicon substrate having a (111) crystal surface as a main surface, and the thickness of the silicon substrate 110 may be 100 nm to 200 nm.

The buffer layer 112 serves to alleviate deformation caused by a difference in lattice constant between the element unit 130 and the substrate 110 disposed on the substrate 110 and prevent the influence of impurities contained in the substrate 110. do. To this end, the buffer layer 112 may include at least one of AlN, AlAs, SiC or AlGaN.

When the buffer layer 112 has a critical thickness or more, diffusion of silicon atoms from the silicon substrate 110 is prevented, and thus melt-back may be prevented. To this end, the buffer layer 112 may have a thickness of tens or hundreds of nanometers, for example, 100 nm or more and less than 300 nm. In some cases, the buffer layer 112 may be omitted.

The nitride semiconductor layer 120 may be disposed between the buffer layer 120 and the device portion 130 to impart compressive stress to the device portion 130. When the compressive stress applied to the element portion 130 increases through the nitride semiconductor layer 120, the element portion 130 having a relatively large thickness may be formed.

When the semiconductor device illustrated in FIG. 1 is a power semiconductor device, device characteristics may be improved, such as a breakdown voltage (BV) of the power semiconductor device increases when the thickness of the device unit 130 increases.

According to an embodiment, the nitride semiconductor layer 120 includes a first super lattice (SL) layer portion 122, at least one insertion layer 124, and a second super lattice layer portion 126. Here, the superlattice layer may be a layer in which the adjacent superlattice layer and the wave function overlap, and the spacing between the adjacent superlattice layers is 3 nm to 4 nm. It is not limited to this.

The first superlattice layer portion 122 is disposed between the buffer layer 112 and the insertion layer 124, and the Al _X Ga _1-X N/Al _Y Ga _1-Y N superlattice layer pair 122-1 , ..., 122-N) may have a structure overlapped at least once. Here, 0 <X <0.3, 0.8 <Y ≤ 1, N is a positive integer of 1 or more. Al _X Ga _{1 - X} N / Al _Y Ga _{1 - Y} N super lattice layer pair (122-1, ..., 122-N) in each, Al _X Ga _{1 - X} N super lattice layer (122-1A, ...122-NA) and Al _Y Ga _{1 - Y} N The relative positions of the superlattice layers 122-1B, ..., 122-NB are not limited. For example, as illustrated in FIG. 1, Al _X Ga _{1 - X} N superlattice layers 122-1A, ... 122-NA are top layers and Al _Y Ga _{1 - Y} N superlattice layers (122-1B, ... 122-NB) may be a bottom layer (bottom layer). Alternatively, as illustrated in FIG. 1, the Al _X Ga _1-X N superlattice layers 122-1A, ... 122-NA are bottom layers and the Al _Y Ga _{1 - Y} N superlattice layers 122-1B, ... 122-NB) may be a top layer.

Further, the second superlattice layer portion 126 is disposed between the insertion layer 124 and the device portion 130, and the Al _I Ga _1-I N/Al _J Ga _1-J N superlattice layer pair 126-1 , ...126-M) may have an overlapped structure at least once. Here, 0.8<I≦1, 0≦J<0.3, and M is a positive integer greater than or equal to 1. Al _I Ga _{1 - I} N / Al _J Ga _{1 - J} N super lattice layer pair (126-1, ..., 126-M) in each, Al _I Ga _1-I N super lattice layer (126-1A, ...126-MA) and Al _J Ga _{1 - J} N The relative positions of the superlattice layers (126-1B, ..., 126-MB) are not limited. For example, as illustrated in FIG. 1, the Al _I Ga _{1 - I} N superlattice layers 126-1A, ... 126-MA are bottom layers and the Al _J Ga _{1 - J} N superlattice layers 126- 1B, ...126-MB) may be a top layer. Alternatively, as illustrated in FIG. 1, the Al _I Ga _{1 - I} N superlattice layers 126-1A, ... 126-MA are top layers and the Al _J Ga _{1 - J} N superlattice layers 126-1B,. ..126-MB) may be a bottom layer.

For example, the first superlattice layer portion 122 _{Al 0 .25 Ga 0 .75 N /} AlN pairs may have a nested structure at least once, the second superlattice layer portion 126 is AlN / GaN second The lattice layer pair may have a structure overlapping at least once.

The content ratio (I) of aluminum in the second superlattice layer portion 126 and the content ratio (X) of aluminum in the first superlattice layer portion 122 may be different from each other or may be the same. In addition, the constituent materials of the first superlattice layer portion 122 and the second superlattice layer portion 126 may be different or the same.

The first superlattice layer portion 122 described above may be a high resistance layer rich in aluminum, and the second superlattice layer portion 126 may be close to GaN because it is not rich in aluminum.

Meanwhile, the insertion layer 124 is disposed between the first super-lattice layer portion 122 and the second super-lattice layer portion 126, and may include at least one of GaN or AlGaN.

Further, the insertion layer 124 may be an undoped layer, or may be doped with at least one of impurities, for example, iron (Fe), carbon (carbon), or zinc (Zn).

In addition, when the thickness t of the insertion layer 124 is smaller than 100 nm or larger than 300 nm, it may be difficult to control the degree of warping of the wafer to less than 50 μm. Therefore, the thickness t of the insertion layer 124 may be 100 nm to 300 nm. The thickness t of the insertion layer 124 may be determined according to the thickness of each superlattice layer included in the second superlattice layer portion 126.

In addition, when the insertion layer 124 is disposed at a position less than 0.2L or greater than 0.8L in the entire length L of the nitride semiconductor layer 120, it may be difficult to control the degree of warping of the wafer to less than 50 μm. . Accordingly, the insertion layer 124 may be disposed at a position of 0.2L to 0.8L, for example, 0.3L to 0.7L, in the entire length L of the nitride semiconductor layer 120.

In addition, when the insertion layer 124 is made of AlGaN, the content ratio of aluminum (Al) included in AlGaN may be 0.1 or less.

The degree of warpage of the wafer may be controlled by at least one of the insertion layer 124 at which point the entire length L of the nitride semiconductor layer 120 is disposed or the thickness t of the insertion layer 124.

Meanwhile, the device unit 130 is disposed on the nitride semiconductor layer 120. The device unit 130 may have various shapes according to an application example of the semiconductor device 100 shown in FIG. 1.

Hereinafter, the configuration and operation of the semiconductor device 100A applied to the power semiconductor device will be described with reference to FIG. 2 as follows.

2 is a cross-sectional view of a power semiconductor device 100A using the semiconductor device 100 shown in FIG. 1.

Referring to FIG. 2, the power semiconductor device 100A includes a substrate 110, a buffer layer 112, a nitride semiconductor layer 120, and a device unit 130A. Since the substrate 110, the buffer layer 112, and the nitride semiconductor layer 120 shown in FIG. 2 are the same as those shown in FIG. 1, the same reference numerals are used and redundant descriptions thereof will be omitted.

The device portion 130A includes a channel layer 132, an electron supply layer 134, a coating layer 136, and an electrode portion 138.

The channel layer 132 is disposed between the nitride semiconductor layer 120 and the electron supply layer 134. The channel layer 132 may be an undoped layer to improve electron mobility, and may include at least one GaN layer.

The electron supply layer 134 is disposed between the channel layer 132 and the coating layer 136. The electron supply layer 134 is a layer that helps to form the channel 132A, and serves to bend the band gap energy. The electron supply layer 134 is a layer having a larger band width than the channel 132A, and may have a uniform polarization density throughout the layer. The electron supply layer 134 has a lattice constant smaller than that of the channel layer 132. Thus, the electron supply layer 134 and the channel layer 132 form a heterojunction interface 132B. As described above, when the channel layer 132 having the lattice constant difference and the electron supply layer 1334 form the heterojunction interface 132B, spontaneous polarization and piezoelectric polarization are caused by the lattice constant difference. Due to this, a two-dimensional electron gas (2-DEG: 2-Dimensional Electron Gas) layer 132A, which is a channel, may be generated on the channel layer 132 side at the heterojunction interface 132B. That is, when a gate bias is applied to the gate electrode 138G, a channel 132A is formed on the channel layer 132 side at the heterojunction interface 132B. As such, since the electron supply layer 134 serves as a barrier to electrons, a 2-DEG layer 132A may be formed on the channel layer 132 at the heterojunction interface 132B.

The electron supply layer 134 may be formed of a compound semiconductor such as silver group 3-5 or group 2-6. For example, a semiconductor material having a composition formula of Al _a In _b Ga _(1-ab) N (0≤a≤1, 0≤b≤1, 0≤a+b≤1) may be included. The electron supply layer 134 may include a nitride semiconductor layer such as GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, or at least one of AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP, or InP. . For example, the electron supply layer 134 may include Al _x GaN or Al _x InGaN. Also, the electron supply layer 134 may be an undoped layer to improve the mobility of electrons.

The coating layer 136 is disposed on the electron supply layer 134. The coating layer 136 serves to protect the electron supply layer 134. The coating layer 136 may include at least one of GaN or SiN _y , and may have a thickness of 2 nm. Here, y is a positive natural number. In some cases, the coating layer 136 may be omitted.

The electrode portion 138 is disposed on the coating layer 136. The electrode portion 138 includes a gate electrode 138G, a source contact 138S, and a drain contact 138D.

The gate electrode 138G may include a metal material. For example, the gate electrode 138G may be a refractory metal or a mixture of refractory metals. Alternatively, the gate electrode 138G may include Ni (Nickel), Au (Aurum), Pt (Platinum), Ta (Tantalum), TaN (Tantalum Nitride), TiN (Titanium Nitride), Pd (Palladium), W (tungsten) or WSi ₂ (Tungstem silicide) may be formed of a single layer or a multi-layer structure by including at least one material. For example, the gate electrode 138G may have a multilayer structure of Ni/Au or a single layer structure of Pt.

The source contact 138S is spaced from one side of the gate electrode 138G and is disposed on the electron supply layer 136. The drain contact 138D is spaced from the other side of the gate electrode 138G and is disposed on the electron supply layer 136.

Each of the source and drain contacts 138S and 138D may be formed of metal. Further, each of the source and drain contacts 138S and 138D may include the same material as the material of the gate electrode 138G. Further, each of the source and drain contacts 138S and 138D may be formed of a reflective electrode material having ohmic characteristics. For example, each of the source and drain contacts 138S, 138D is aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), copper (Cu), gold (Au), or molybdenum (Mo) It may be formed of a single-layer or multi-layer structure, including at least one of. For example, each of the source and drain contacts 138S and 138D may have a multilayer structure of Ti/Al or Ti/Mo.

The embodiment is not limited by the shape and structure of the gate electrode 138G, source and drain contacts 138S, 138D illustrated in FIG. 2. That is, according to another embodiment, a gate insulating layer (not shown) may be further disposed between the gate electrode 138G and the coating layer 136.

Hereinafter, a configuration and operation of the semiconductor device 100B according to an embodiment in which the light emitting device is implemented using the semiconductor device 100 illustrated in FIG. 1 will be described as follows.

3 is a sectional view showing a semiconductor device 100B for a light emitting device according to an embodiment.

Referring to FIG. 3, the semiconductor device 100B for a light emitting device includes a substrate 110, a buffer layer 112, a nitride semiconductor layer 120, and a device unit 130B. Since the substrate 110, the buffer layer 112, and the nitride semiconductor layer 120 shown in FIG. 3 are the same as those shown in FIG. 1, the same reference numerals are used and redundant descriptions thereof are omitted.

The device unit 130 illustrated in FIG. 1 may include a light emitting structure 130B. The light emitting structure 130B includes a first conductivity type semiconductor layer 133, an active layer 135, and a second conductivity type semiconductor layer 137.

The first conductivity type semiconductor layer 133 is disposed between the nitride semiconductor layer 120 and the active layer 135, and may include a group III-V compound semiconductor doped with a first conductivity type dopant, Al _c In _d It may include a semiconductor material having a composition formula of Ga _(1-cd) N (0 ≤ c ≤ 1, 0 ≤ d ≤ 1, 0 ≤ c+d ≤ 1). For example, the first conductive semiconductor layer 133 may be formed of at least one selected from GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP, and InP. Can. In addition, when the first conductivity-type semiconductor layer 133 is an n-type semiconductor layer, the first conductivity-type dopant may include, but is not limited to, Si, Ge, Sn, Se, or Te.

In the active layer 135, electrons (or holes) injected through the first conductivity type semiconductor layer 133 and holes (or electrons) injected through the second conductivity type semiconductor layer 137 meet each other, and the active layer It is a layer that emits light having energy determined by the energy band inherent to the material constituting (135).

The active layer 135 is at least one of a single well structure, a multi well structure, a single quantum well structure, a multi quantum well structure (MQW), a quantum-wire structure, or a quantum dot structure. Can be formed. For example, the active layer 135 is injected with trimethyl gallium (TMG: Trimethyl Gallium) gas, ammonia (NH ₃ ) gas, nitrogen gas (N ₂ ), and trimethyl indium gas (TMIn: Trimethyl Indium) to form a multi-quantum well structure. It may be formed, but is not limited thereto.

The well layer/barrier layer of the active layer 135 has a pair structure of InGaN/GaN, InGaN/InGaN, GaN/AlGaN, InAlGaN/GaN, GaAs(InGaAs)/AlGaAs and GaP(InGaP)/AlGaP, or more. It may be formed, but is not limited thereto. The well layer may be formed of a material having a band gap smaller than the band gap of the barrier layer.

The second conductivity-type semiconductor layer 137 may include a group III-V compound semiconductor doped with a second conductivity-type dopant, and In _e Al _f Ga _{1 -e- f} N (0 ≤ e ≤ 1, 0 ≤ It may include a semiconductor material having a composition formula of f ≤ 1, 0 ≤ e+f ≤ 1). For example, when the second conductivity-type semiconductor layer 137 is a p-type semiconductor layer, the second conductivity-type dopant is a p-type dopant, and may include Mg, Zn, Ca, Sr, or Ba, but is not limited thereto. Does not.

In the above-described light emitting structure, the first conductive type semiconductor layer 133 is made of an n-type semiconductor layer, and the second conductive type semiconductor layer 137 is a case made of a p-type semiconductor layer. However, the first conductivity-type semiconductor layer 133 may be formed of a p-type semiconductor layer, and the second conductivity-type semiconductor layer 137 may be formed of an n-type semiconductor layer. That is, the light emitting structure may be implemented with any one of n-p junction structure, p-n junction structure, n-p-n junction structure, and p-n-p junction structure.

Although not illustrated, first and second electrodes (not shown) that are electrically connected to the first and second conductivity-type semiconductor layers 133 and 137, respectively, may be disposed. That is, the semiconductor device 100B illustrated in FIG. 3 may be a light emitting device having a horizontal bonding structure. In this case, the first conductive type semiconductor layer 133, the active layer 135, and the second conductive type semiconductor layer 137 are first exposed on the first conductive type semiconductor layer 133 exposed by MESA etching. An electrode is disposed, and a second electrode is disposed on the second conductivity-type semiconductor layer 137.

Hereinafter, a manufacturing method according to an embodiment of the semiconductor device 100 illustrated in FIG. 1 will be described with reference to FIGS. 4A to 4C attached as follows, but the embodiment is not limited thereto. That is, the semiconductor device 100 illustrated in FIG. 1 may be manufactured by a method other than the method illustrated in FIGS. 4A to 4C.

4A to 4C are process cross-sectional views illustrating a manufacturing method according to an embodiment of the semiconductor device 100.

Referring to FIG. 4A, the substrate 110 is prepared. The substrate 110 may be a silicon substrate, a silicon carbide substrate, a GaN substrate, or a sapphire substrate, but the embodiment is not limited to the type of the substrate 110. For example, the substrate 110 may be a silicon substrate having a (111) crystal surface as a main surface, and the thickness of the silicon substrate 110 may be 100 nm to 200 nm.

If, when the substrate 110 is a silicon substrate, by depositing an ultra aluminum film by exposing it to Trimethyl Aluminum (TMA) gas for 15 seconds in the absence of ammonia (NH ₃ ) gas, silicon nitride is a silicon substrate. It is prevented from being formed on the surface of (110). In some cases, a process of removing the natural oxide film on the silicon substrate 110 by rapid annealing the silicon substrate 110 to a temperature of about 900° C. may be additionally performed. However, the present invention is not limited thereto, and the silicon substrate 110 may be prepared in various forms.

Thereafter, a buffer layer 112 is formed on the substrate 110. The buffer layer 112 may include at least one of AlN, AlAs, SiC, or AlGaN. When the buffer layer 112 has a critical thickness or more, diffusion of silicon atoms from the silicon substrate 110 is prevented, and thus melt-back may be prevented. To this end, the buffer layer 112 may have a thickness of tens or hundreds of nanometers, for example, 100 nm or more and less than 300 nm. In some cases, the buffer layer 112 may be omitted.

If the substrate 110 is a silicon substrate, an AlN buffer layer 112 having a predetermined thickness may be formed on the silicon substrate 110 at a temperature of about 900° C. while using ammonia. At this time, when the thickness of the AlN buffer layer 112 increases above the crystal thickness, the fusion of the AlN islands changes from the 3D growth mode to the 2D growth mode. Since the fused AlN island can completely cover the silicon substrate 110, diffusion of silicon atoms can be prevented. Alternatively, the AlN buffer layer 112 may be formed on the silicon substrate 110 by various methods other than the above-described methods.

Subsequently, referring to FIG. 4A, the first superlattice layer portion 122 is formed on the buffer layer 112. In the first superlattice layer portion 122, Al _X Ga _{1 - X} N/Al _Y Ga _{1 - Y} N superlattice layer pairs 122-1, ..., 122-N are overlapped at least once. It can have a structure. Al _X Ga _{1 - X} N / Al _Y Ga _{1 - Y} N super lattice layer pair (122-1, ..., 122-N) in each, Al _X Ga _{1 - X} N super lattice layer (122-1A, ...122-NA) and Al _Y Ga _{1 - Y} N The relative positions of the superlattice layers 122-1B, ..., 122-NB are not limited. For example, as illustrated in FIG. 4A, Al _Y Ga _{1 - Y} N superlattice layers 122-1B, ... 122-NB are first formed, and then Al _Y Ga _{1 - Y} N superlattice layers 122 Al _X Ga _{1 - X} N superlattice layers 122-1A, ... 122-NA may be formed on -1B, ...122-NB). Or, as illustrated in Figure 4a, after forming the Al _X Ga _{1 - X} N superlattice layer (122-1A, ... 122-NA), Al _X Ga _{1 - X} N superlattice layer (122-1A) , ... 122-NA) may form an Al _Y Ga _1-Y N superlattice layer 122-1B, ... 122-NB.

Thereafter, referring to FIG. 4B, an insertion layer 124 is formed on the first superlattice layer portion 122.

The insertion layer 124 may be formed using at least one of GaN or AlGaN.

In addition, the insertion layer 124 may be an undoped layer, or may be formed by doping at least one of impurities such as iron (Fe), carbon (carbon), or zinc (Zn).

Further, the insertion layer 124 can be formed with a thickness t of 100 nm to 300 nm.

In addition, the insertion layer 124 may be formed at a position of, for example, 0.3L to 0.7L between 0.2L and 0.8L in the entire length L of the nitride semiconductor layer 120.

Further, the insertion layer 124 may be formed of AlGaN having an aluminum (Al) content ratio of 0.1 or less.

Thereafter, referring to FIG. 4C, a second superlattice layer portion 126 is formed on the insertion layer 124.

The second superlattice layer portion 126 may have a structure in which Al _I Ga _{1 - I} N/Al _J Ga _{1 - J} N superlattice layer pairs 126-1, ... 126-M are overlapped at least once. have. Al _I Ga _{1 - I} N / Al _J Ga _{1 - J} N super lattice layer pair (126-1, ..., 126-M) in each, Al _I Ga _{1 - I} N super lattice layer (126-1A, ...126-MA) and Al _J Ga _{1 - J} N The relative positions of the superlattice layers (126-1B, ..., 126-MB) are not limited. For example, after forming the Al _I Ga _{1 - I} N superlattice layers 126-1A, ... 126-MA, as illustrated in FIG. 4C, the Al _I Ga _{1 - I} N superlattice layers 126 Al _J Ga _{1 - J} N superlattice layers (126-1B, ...126-MB) may be formed on -1A, ...126-MA). Or, as illustrated in Figure 4c, after forming the Al _J Ga _{1 - J} N superlattice layer (126-1B, ... 126-MB), Al _J Ga _{1 - J} N superlattice layer (126-1B) , ... 126-MB) Al _I Ga _{1 - I} N superlattice layer (126-1A, ... 126-MA) may be formed.

In addition, the content ratio (X) of aluminum may be different or the same as each other, thereby forming the first and second superlattice layer portions 122 and 126.

Thereafter, referring to FIG. 1, the device unit 130 is formed on the second superlattice layer unit 126.

The device unit 130 is as illustrated in FIG. 2 when the semiconductor device 100 shown in FIG. 1 is applied to the power semiconductor device 100A.

In this case, the channel layer 132 is formed on the second superlattice layer portion 126. The channel layer 132 may be an undoped layer to improve electron mobility. The channel layer 132 may be formed by at least one GaN layer.

Thereafter, an electron supply layer 134 is formed on the channel layer 132. The electron supply layer 134 may be formed using a compound semiconductor such as group 3-5 or group 2-6. For example, Al _a In _b Ga _(1-ab) N (0≤a≤1, 0≤b≤1, 0≤a+b≤1) may be formed of a semiconductor material having a composition formula. The electron supply layer 134 may be formed using a nitride semiconductor layer such as GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, or at least one of AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP, or InP. Can. For example, the electron supply layer 134 may be formed of Al _x GaN or Al _x InGaN. Also, the electron supply layer 134 may be an undoped layer to improve the mobility of electrons.

Thereafter, a coating layer 136 is formed on the electron supply layer 134. The coating layer 136 may be formed to a thickness of 2 nm using at least one of GaN or SiN _y . Here, y is a positive natural number. In some cases, the coating layer 136 may be omitted.

Thereafter, an electrode portion 138 is formed on the coating layer 136. That is, the gate electrode 138G, the source contact 138S, and the drain contact 138D may be formed on the coating layer 136 to be spaced apart from each other. For example, the gate electrode 138G uses a refractory metal or a mixture of refractory metals, or Ni(Nickel), Au(Aurum), Pt(Platinum), Ta(Tantalum), TaN(Tantalum Nitride), TiN( Titanium Nitride), Pd (Palladium), W (tungsten) or WSi ₂ (Tungstem silicide) may be formed of a single layer or a multi-layer structure using at least one material.

Each of the source and drain contacts 138S and 138D may be formed of metal. Further, each of the source and drain contacts 138S and 138D may be formed of the same material as the material of the gate electrode 138G. Further, each of the source and drain contacts 138S and 138D may be formed of a reflective electrode material having ohmic characteristics. For example, each of the source and drain contacts 138S, 138D is aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), copper (Cu), gold (Au), or molybdenum (Mo) It may be formed of a single-layer or multi-layer structure, including at least one of.

Alternatively, the device unit 130 is as illustrated in FIG. 3 when the semiconductor device 100 shown in FIG. 1 is applied to a light emitting device.

In this case, the light emitting structure 130B is formed on the second superlattice layer portion 126. That is, the first conductivity type semiconductor layer 133 is formed on the second superlattice layer portion 126.

The first conductivity type semiconductor layer 133 may include a group III-V compound semiconductor doped with a first conductivity type dopant, and Al _c In _d Ga _(1-cd) N (0 ≤ c ≤ 1, 0 ≤ d≦1, 0≦c+d≦1). For example, the first conductive semiconductor layer 133 may be formed of at least one selected from GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP, and InP. Can. In addition, when the first conductivity-type semiconductor layer 133 is an n-type semiconductor layer, the first conductivity-type dopant may include, but is not limited to, Si, Ge, Sn, Se, or Te.

Thereafter, the active layer 135 is formed on the first conductive semiconductor layer 133. The active layer 135 is at least one of a single well structure, a multi well structure, a single quantum well structure, a multi quantum well structure (MQW), a quantum-wire structure, or a quantum dot structure. Can be formed. For example, the active layer 135 is injected with trimethyl gallium (TMG: Trimethyl Gallium) gas, ammonia (NH ₃ ) gas, nitrogen gas (N ₂ ), and trimethyl indium gas (TMIn: Trimethyl Indium) to form a multi-quantum well structure. It may be formed, but is not limited thereto.

The well layer/barrier layer of the active layer 135 has a pair structure of InGaN/GaN, InGaN/InGaN, GaN/AlGaN, InAlGaN/GaN, GaAs(InGaAs)/AlGaAs and GaP(InGaP)/AlGaP, or more. It may be formed, but is not limited thereto. The well layer may be formed of a material having a band gap smaller than the band gap of the barrier layer.

Thereafter, a second conductivity type semiconductor layer 137 is formed on the active layer 135. The second conductivity-type semiconductor layer 137 may include a group III-V compound semiconductor doped with a second conductivity-type dopant, and In _e Al _f Ga _{1 -e- f} N (0 ≤ e ≤ 1, 0 ≤ It may include a semiconductor material having a composition formula of f ≤ 1, 0 ≤ e+f ≤ 1). For example, when the second conductivity-type semiconductor layer 137 is a p-type semiconductor layer, the second conductivity-type dopant is a p-type dopant, and may include Mg, Zn, Ca, Sr, or Ba, but is not limited thereto. Does not.

Each of the above-described buffer layer 112, nitride semiconductor layer 120, and device portion 130, for example, Ga, Al and N metal organic chemical vapor deposition (MOCVD: Metal Organic Chemical Vapor Deposition) method, organic metal vapor phase growth (MOVPE: Metal Organic Vapor Phase Epitaxy), Molecular Beam Epitaxy (MBE), Hydrogen Vapor Phase Epitaxy (HVPE), or the like. For example, by using a precursor material containing trimethyl gallium (TMG: Trimethyl Gallium), TMA and NH ₃ , MOCVD method to the first to third semiconductor layers (140, 160C, 190) containing Ga, Al and N ) May be formed.

Hereinafter, the bending phenomenon of the semiconductor devices 100, 100A, and 100B according to the embodiment will be described with reference to the accompanying drawings.

5A and 5B are graphs for explaining the bending phenomenon of the semiconductor devices 100, 100A, and 100B according to an embodiment. Here, the abscissa represents the thickness T for growing the semiconductor devices 100, 100A, and 100B, and the ordinate represents the wafer bowing or warping. The point where the thickness T is 0 corresponds to an interface between the nitride semiconductor layer 120 and the device unit 130 illustrated in FIGS. 1, 2 and 3, and is based on a point where the thickness T is '0'. The left (-) portion corresponds to the nitride semiconductor layer 120, and the right (+) portion corresponds to the device portion 130. Further, when the wafer is convexly curved, the degree of warping of the wafer on the vertical axis is less than 0, and when the wafer is concavely curved, the degree of warping of the wafer on the vertical axis is greater than 0.

5A shows the degree of warpage of the wafer when the nitride semiconductor layer 120 includes only the first and second superlattice layer portions 122 and 126 and does not include the insertion layer 124. 5A, when the thickness of the nitride semiconductor layer 120 is 1.7 μm (▲), when 2.0 μm (●), the degree of warping of the wafer is greater, and when the thickness is 2.0 μm (●), it is 2.3 μm. When (■) it can be seen that the degree of warping of the wafer is greater. As such, the larger the thickness of the nitride semiconductor layer 120, the more the wafer is concavely bent. In addition, it can be seen that although the degree of warping of the wafer decreases at the initial stage of growing the element portion 130, the degree of warping of the wafer increases as the element portion 130 grows thicker than 1 µm.

5B does not include the wafer bending degree and the insertion layer 124 when the nitride semiconductor layer 120 includes the first and second superlattice layer portions 122 and 126 as well as the insertion layer 124 (●). If it does not (■), it is shown in contrast to the degree of warping of the wafer. Referring to FIG. 5B, when the thickness T of the device unit 130 is grown to 2 μm or more, the semiconductor devices 100, 100A, and 100B according to the embodiment include an insertion layer 124 (●) Therefore, it can be seen that the degree of warping of the wafer is reduced than when the insertion layer 124 is not included (■).

As described above, when the insertion layer 124 is not provided in the nitride semiconductor layer 120, when the thickness of the device portion 130 grows to 2 µm or more, the warpage of the wafer exceeds 50 µm. According to this, even if the thickness of the device portion 130 grows to 2 µm or more by providing the insertion layer 124, the warpage of the wafer may not exceed 50 µm.

The semiconductor device according to the embodiment may include the thickly grown device layer 130 by arranging the insertion layer 124 to improve the degree of warping of the wafer. Therefore, the semiconductor devices 100 and 100B of the embodiment may have good device characteristics since the thickness of the device unit 130 increases and the breakdown voltage BV of the power semiconductor device increases.

The embodiments have been mainly described above, but this is merely an example, and the present invention is not limited thereto, and those skilled in the art to which the present invention pertains are not exemplified above in the range that does not depart from the essential characteristics of the present embodiment. It will be appreciated that various modifications and applications are possible. For example, each component specifically shown in the embodiment can be implemented by modification. And differences related to these modifications and applications should be construed as being included in the scope of the invention defined in the appended claims.

100, 100A, 100B: semiconductor element 110: buffer layer
120: nitride semiconductor layer 122: the first superlattice layer portion
124: insertion layer 126: second superlattice layer portion
130: 130A, 130B: element portion 132: channel layer
133: first conductive semiconductor layer 134: electron supply unit
135: active layer 136: coating
137: second conductivity type semiconductor layer 138: electrode portion
138G: gate electrode 138S: source contact
138D: drain contact

Claims (10)

Board;
A nitride semiconductor layer disposed on the substrate; And
And an element portion disposed on the nitride semiconductor layer,
The nitride semiconductor layer
Al _X Ga _1-X N (0≤X<0.3)/Al _Y Ga _1-Y N(0.8<Y≤1) superlattice layer pair is disposed on the substrate and has an overlapped structure at least once. A first superlattice layer portion having a high content of high resistance components;
One insertion layer disposed on the first superlattice layer portion and having a thickness of 100 nm to 300 nm including GaN or AlGaN; And
Al _I Ga _1-I N (0.8<I≤1)/Al _J Ga _1-J N(0≤J<0.3) superlattice layer pair is disposed on the insertion layer and has a structure overlapping at least once. And a second superlattice layer portion having a lower Al content than the first superlattice layer portion,
The insertion layer is disposed between 0.4L and 0.7L in the entire length (L) of the nitride semiconductor layer,
The aluminum (Al) content ratio of AlGaN included in the insertion layer is less than or equal to 0.1 semiconductor device. The method of claim 1, wherein the insertion layer is doped with impurities,
The impurity is a semiconductor device including at least one of iron (Fe), carbon (carbon), or zinc (Zn). delete delete delete delete delete delete The method of claim 1, wherein the element portion
A channel layer disposed on the nitride semiconductor layer;
An electron supply layer disposed on the channel layer;
It includes an electrode portion disposed on the electron supply layer,
The electrode portion
Gate electrode;
A source contact spaced apart from one side of the gate electrode; And
A semiconductor device including a drain contact spaced apart from the other side of the gate electrode. The method of claim 1, wherein the element portion
A first conductivity type semiconductor layer disposed on the nitride semiconductor layer;
An active layer disposed on the first conductive semiconductor layer; And
A semiconductor device including a second conductive type semiconductor layer disposed on the active layer.

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