JP4446869B2 - Heterojunction type III-V compound semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a III-V compound semiconductor device having a heterojunction structure and a method for manufacturing the same.

Research on III-V compound semiconductor devices is active, and for example, research on heterojunction type III-V compound semiconductor devices using gallium nitride (GaN) is being actively conducted. An example of this is proposed in Non-Patent Document 1.
A heterojunction type III-V group compound semiconductor device disclosed in Non-Patent Document 1 includes a UID (unintentionally doped) -GaN layer and an AlGaN layer having a larger band gap than the band gap of the UID-GaN layer. It has a joined structure. The AlGaN layer contains Al in the semiconductor crystal and has a larger band gap than the UID-GaN layer. A source electrode and a gate electrode are formed on the surface of the AlGaN layer. An n-GaN layer serving as a drain and a drain electrode are formed on the back surface of the GaN layer. A p-type GaN layer having an opening is formed between the UID-GaN layer and the n-GaN layer. The opening and the gate electrode are formed at opposing positions.
In this heterojunction type III-V compound semiconductor device, when a voltage lower than the threshold voltage is applied to the gate electrode, the conduction band energy level on the UID-GaN layer side of the heterojunction interface between the UID-GaN layer and the AlGaN layer is reduced. It rises above the Fermi level. Since the conduction band energy level is higher than the Fermi level, there is no electron (2DEG (2 Dimensional Electron Gas)) in the UID-GaN layer near the heterojunction interface. It becomes a state. Therefore, the heterojunction semiconductor device is turned off. On the other hand, when a voltage higher than the threshold voltage is applied to the gate electrode, a potential well is formed on the UID-GaN layer side of the heterojunction interface between the UID-GaN layer and the AlGaN layer. In the potential well, the conduction band energy level falls below the Fermi level. Since the conduction band energy level is lower than the Fermi level, electrons can be generated in the UID-GaN layer near the heterojunction interface. The generated electrons move from the potential well facing the source electrode to the potential well facing the gate electrode along the heterojunction interface based on the potential difference in the region where the two-dimensional electron gas is generated. Electrons that have moved into the potential well facing the gate electrode move to the UID-GaN layer by two conductive mechanisms. One is a conduction mechanism that moves into the UID-GaN layer across the energy barrier between the conduction band energy level in the potential well and the conductor energy level of the UID-GaN layer. The other is a conductive mechanism that moves into the UID-GaN layer through a level formed due to defects present at the heterojunction interface. Electrons that have moved into the UID-GaN layer by these conductive mechanisms move to the drain electrode through the opening of the p-GaN layer and the drain layer. Accordingly, the heterojunction semiconductor device is turned on.
Journal of Applied Physics. Volume 95, Number 4. p2073-2078

A heterojunction type III-V group compound semiconductor device proposed in Non-Patent Document 1 includes an n-GaN layer serving as a drain, a p-GaN layer having an opening, a UID-GaN layer, and an AlGaN on a sapphire substrate. The layers are produced by epitaxial growth in sequence. Crystal defects based on lattice mismatch with the sapphire substrate propagate to each layer. Therefore, crystal defects exist at a high density in almost the entire region of the heterojunction interface between the UID-GaN layer and the AlGaN layer.
If crystal defects are present at high density throughout the heterojunction interface, the levels formed due to crystal defects existing at high density at the heterojunction interface will be reduced even if the heterojunction semiconductor device is turned off. Current will flow through. Since a current passing through the heterojunction interface flows through a level formed due to crystal defects, there arises a problem that a leak current flows even when the heterojunction semiconductor device is turned off.
In order to prevent leakage current, a GaN substrate having a small number of crystal defects over the entire layer is prepared, and a III-V compound having a larger band gap is heterojunctioned thereon. That's fine. If there are few crystal defects in the entire region of the heterojunction interface, current flowing beyond the heterojunction interface via the level formed due to the crystal defects can be suppressed, and countermeasures against leakage current can be taken. It should be possible.
However, if a GaN substrate having few crystal defects throughout the entire layer is used, the energy required for electrons in the potential well to move to the GaN substrate increases when the heterojunction semiconductor device is turned on. . As a result, the on-resistance increases.
Accordingly, in the case of a semiconductor device in which a III-V group compound having a small band gap and a III-V group compound having a large band gap are heterojunction, and a vertical semiconductor device in which current flows through the heterojunction interface, III If the crystal defect of the -V group compound is high density, the leakage current at the off time becomes a problem. If the crystal defect of the III-V compound compound is low density, the resistance at the on time becomes high. Yes.
The present invention realizes a heterojunction type III-V group compound semiconductor device that can suppress a leakage current when turned off and reduce a resistance when turned on. A manufacturing method for this purpose is also proposed.

A heterojunction type III-V compound semiconductor device according to the present invention comprises a lower layer of a III-V compound semiconductor, a III-V group that is heterojunctioned to the lower layer and has a larger band gap than the lower band gap. An upper layer of the compound semiconductor, a main electrode formed on a part of the surface of the upper layer, and a gate electrode formed on another part of the surface of the upper layer are provided.
The lower layer is characterized in that crystal defect high density regions and crystal defect low density regions are distributed in a plane parallel to the heterojunction interface. The main electrode is formed in a region facing the crystal defect low density region, and the gate electrode is formed in a region facing the crystal defect high density region.
The gate electrode may be formed in a part of a region facing the crystal defect high-density region, or may be formed in a region substantially the same shape as the crystal defect high-density region, or the crystal defect high-density region. May be formed. The gate electrode may be in Schottky contact with the upper layer, or may be opposed to the upper layer through an insulating film.

In the semiconductor device described above, the main electrode faces the low density heterojunction interface having crystal defects. In the crystal defect low density region, since there are few crystal defects, almost no leakage current flows through the heterojunction interface. The gate electrode is opposed to the region where the crystal defects are high density. Since the crystal defect high-density region can be strongly influenced by the gate-off voltage of the gate electrode, the leakage current flowing from the crystal defect high-density region through the heterojunction interface can be effectively suppressed. Therefore, when the semiconductor device is turned off, there is no current flowing along the heterojunction interface. Therefore, even if there is a heterojunction interface with a high density of crystal defects in the part separated from the main electrode, the leakage current is reduced. It will not increase.
When the semiconductor device is turned on, carriers move from the potential well to the lower layer in the region facing the gate electrode. In the region facing the gate electrode, the number of crystal defects at the heterojunction interface is high, so that carriers in the potential well can move to the lower layer through the levels formed due to the crystal defects. As a result, the on-resistance is reduced. When the semiconductor device is on, a potential well is formed on the lower layer side of the heterojunction interface. Carriers move from within the potential well facing the main electrode into the potential well facing the gate electrode along the heterojunction interface. Carriers flow to the lower layer through levels formed due to crystal defects at the heterojunction interface facing the gate electrode. The carriers that have flowed to the lower layer pass through the lower layer along crystal defects that exist at high density in the crystal defect high-density region. Resistance when the carrier passes through the lower layer is also low.
The heterojunction type III-V group compound semiconductor device of the present invention can suppress the leakage current when turned off and can reduce the resistance when turned on.

In order to further suppress the leakage current of the heterojunction type III-V compound semiconductor device, it is preferable to form a gate electrode that extends beyond the region facing the high-density region of crystal defects.
When the semiconductor device is turned off, a phenomenon in which carriers are generated at the heterojunction interface where crystal defects exist at a high density due to the influence of the gate-off voltage of the gate electrode can be reliably prevented.

It is preferable that an insulating region is further provided in at least a part of the crystal defect low density region in the lower layer. The insulating region here can be formed of, for example, an insulator, a dielectric, a semiconductor having a conductivity type opposite to that of majority carriers, or a combination thereof.
Due to the presence of this insulating region, the resistance on the side of the crystal defect low density region in the lower layer can be increased. As a result, when the III-V compound semiconductor device is turned off, it is possible to suppress the leakage current from flowing in the potential well below the main electrode (corresponding to the crystal defect low density region).

  It is preferable that the insulating region is not located in the existence range of the two-dimensional electron gas generated at the heterojunction interface. With this positional relationship, carriers moving in the potential well formed at the heterojunction interface are not hindered by the presence of the insulating region.

The above III-V compound semiconductor device can be easily produced by using the following manufacturing method. This manufacturing method includes a step of preparing a semiconductor substrate. A step of forming an epitaxial growth inhibiting member having openings dispersedly arranged on the surface of the semiconductor substrate is provided. A step of forming a lower layer by epitaxially growing a III-V group compound from the surface of the semiconductor substrate exposed at the opening of the epitaxial growth prohibiting member is provided. From the surface of the lower layer, there is provided a step of forming an upper layer by epitaxially growing a III-V group compound having a band gap larger than that of the lower layer III-V group compound. Forming a main electrode on the surface of the upper layer in a region facing the epitaxial growth prohibiting member; Furthermore, a step of forming a gate electrode on a surface of an upper layer in a region facing the opening is provided.
Note that the surface of the upper layer in the region facing the opening or the surface of the upper layer in the region facing the epitaxial growth prohibiting member originally has an opening when the epitaxial growth prohibiting member has been removed by another process. Can be interpreted in the sense of facing the position where the epitaxial growth prohibiting member originally existed.
As the epitaxial growth prohibiting member, a material that does not epitaxially grow III-V group crystals from the surface thereof is selected. Typically, silicon oxide, silicon nitride, or the like can be preferably used.
When the lower layer of the III-V compound is formed by epitaxial growth from the surface of the semiconductor substrate exposed at the opening of the epitaxial growth prohibiting member, the layer is formed from the position of the opening in the lower layer based on lattice mismatching between the semiconductor substrate and the lower layer. Crystal defects are propagated and formed in the thickness direction. This becomes a crystal defect high density region. On the other hand, since the crystal grows in the lateral direction above the epitaxial growth prohibiting member, a crystal defect low density region with relatively few crystal defects is formed. Therefore, when a gate electrode is formed on the surface of the upper layer in the region facing the opening, a crystal defect high-density region exists at the lower layer side interface below the gate electrode. Furthermore, when the main electrode is formed on the surface of the upper layer in the region facing the epitaxial prohibiting member, a crystal defect low density region exists at the lower layer side interface below the main electrode. The above heterojunction type III-V compound semiconductor device can be easily obtained simply by determining the positions of the gate electrode and the main electrode based on the epitaxial growth prohibiting member and the opening position thereof.

  In the gate electrode formation step, the gate electrode is preferably formed beyond the region facing the opening. The gate electrode formed in this positional relationship is formed beyond the region facing the crystal defect high density region.

  The heterojunction type III-V compound semiconductor device of the present invention can suppress a leakage current at the time of OFF. Furthermore, the resistance at the time of ON can be reduced.

First, the main features of the embodiment are listed.
(First Form) The III-V group compound semiconductor is a GaN-based compound semiconductor.
(2nd form) A gate electrode is formed exceeding the area | region of the surface of the upper layer of the area | region facing a crystal defect high density area | region.
(3rd form) A gate electrode is extended and formed from the area | region of the surface of the upper layer facing a crystal defect high density area | region to the area outside.
(Fourth Embodiment) The drain electrode is in electrical contact with the entire back surface of the lower layer (or the entire back surface of the semiconductor layer when another semiconductor layer is interposed).
(5th form) A crystal defect high density area | region is an area | region whose crystal defect density is 1 * 10 ^{< 6} > cm ^<-2 > or more.

Embodiments will be described in detail below with reference to the drawings.
FIG. 1 schematically shows a cross-sectional view of an essential part of a heterojunction type III-V group compound semiconductor device (hereinafter referred to as a semiconductor device 10) of this example.
The semiconductor device 10 includes a lower layer 46 made of intrinsic GaN (gallium nitride). In the lower layer 46, a region having a large number of crystal defects 70 and a region having a small number of crystal defects 70 are distributed in a plane orthogonal to the layer thickness direction (up and down direction in the drawing). The crystal defect 70 exists penetrating in the layer thickness direction. As will be described later, the crystal defect 70 exists not only in the lower layer 46 but also in the semiconductor layers above and below it. Further, the crystal defect high density region 72 in which many crystal defects 70 exist is distinguished from the region in which the remaining crystal defects 70 are small (crystal defect low density region). Typically, when the crystal defect density is 1 × 10 ⁶ cm ⁻² or more, the crystal defect high-density region 72 can be evaluated.
An upper layer 48 made of AlGaN containing an n-type impurity is formed on the lower layer 46. The upper layer 48 contains Al in the semiconductor crystal and has a larger band gap than the GaN layer. The lower layer 46 and the upper layer 48 constitute a heterojunction structure. It can be said that the crystal defect high density region 72 and the crystal defect low density region are distributed in a plane parallel to the heterojunction interface.
A gate electrode 52 is formed on the surface of the upper layer 48 in a region facing the crystal defect high density region 72. The gate electrode 52 is formed on the surface of the upper layer 48 beyond the region facing the crystal defect high-density region 72. The gate electrode 52 has a laminated structure of nickel (Ni) and gold (Au), and is in Schottky contact with the surface of the upper layer 48. A source electrode 54 that is in electrical contact with the surface of the upper layer 48 in a region facing a region having few crystal defects 70 (a crystal defect low density region) is formed. The source electrode 54 has a laminated structure of titanium (Ti) and aluminum (Al), and is in ohmic contact with the surface of the upper layer 48.
Furthermore, a GaN drain layer 42 containing n-type impurities is formed on the back side of the lower layer 46. Therefore, the back surface of the lower layer 46 is electrically connected to the drain electrode 32 via the drain layer 42.

Next, the operation of the junction semiconductor device 10 will be described.
When a voltage lower than the threshold voltage is applied to the gate electrode 52 with the source electrode 54 of the junction semiconductor device 10 of the present embodiment grounded and 5 V applied to the drain electrode 32, the heterojunction interface between the lower layer 46 and the upper layer 48 is applied. The conduction band energy level on the lower layer 46 side is higher than the Fermi level. The conduction band energy level on the lower layer 46 side below the source electrode 54 that is located away from the gate electrode 52 is less affected by the gate-off voltage, and in some cases, a potential well is formed, and electrons are induced in this potential well. There is a case. However, even in this case, since the crystallinity of the heterojunction interface below the source electrode 54 is good, the electrons in the potential well are prevented from moving into the lower layer 46. A situation in which a leak current flows is prevented. There is a crystal defect high density region 72 at the heterojunction interface below the gate electrode 52, but since this region can strongly influence the gate-off voltage of the gate electrode 52, a potential well is not formed, A state in which no electrons exist can be obtained. Therefore, a situation in which a leak current flows from the crystal defect high density region 72 is also prevented. Therefore, the semiconductor device 10 can be turned off without leakage current flowing.
On the other hand, when a voltage higher than the threshold voltage is applied to the gate electrode 52 while the source electrode 54 is grounded and 5 V is applied to the drain electrode 32, a potential well is formed on the lower layer 46 side of the heterojunction interface between the lower layer 46 and the upper layer 48. It is formed. In the potential well, the conduction band energy level falls below the Fermi level. Since the conduction band energy level is lower than the Fermi level, electrons (two-dimensional electron gas) can exist in the potential well. In FIG. 2, the flow of electrons in the ON state is indicated by arrows. As shown in FIG. 2, the electrons in the potential well first move along the heterojunction interface from the potential well below the source electrode 54 to the potential well below the gate electrode 52. The electrons that have moved to the lower side of the gate electrode 52 move into the lower layer 46 through the levels caused by the crystal defect high-density region 72 present at the lower layer 46 side interface. Since it moves through the level caused by the crystal defect high-density region 72, electrons in the potential well can be moved into the lower layer 46 without requiring large energy. The on-resistance of the semiconductor device 10 is small.

Next, this phenomenon will be described using the energy band diagram shown in FIG. The energy band diagram shown in FIG. 3 is an energy band diagram in the vicinity of the interface between the lower layer 46 and the upper layer 48 corresponding to the line III-III in FIG.
FIG. 3A shows an energy band when the power is on. The conduction band energy level of the potential well formed at the heterojunction interface between the lower layer 46 and the upper layer 48 is lower than the Fermi level. Electrons in the potential well can easily move into the lower layer 46 across the energy barrier between the conduction band energy levels through the levels caused by crystal defects. When there is no crystal defect, it is necessary to move into the lower layer 46 over a large energy barrier between the conduction band energy levels, and the on-resistance increases.
FIG. 3B is an energy band diagram when turned off. By applying a voltage lower than the threshold voltage to the gate electrode 52, the conduction band energy level in the vicinity of the lower layer 46 side interface in the interface between the lower layer 46 and the upper layer 48 exists above the Fermi level. Thus, no electrons are present in the vicinity of the interface on the lower layer 46 side. The semiconductor device 10 is turned off. At this time, if there are many crystal defects at the heterojunction interface below the source electrode 54, a leakage current may occur in some cases. However, in this embodiment, since the crystallinity of the heterojunction interface below the source electrode 54 is good, the energy barrier between the potential well and the conduction band energy level of the lower layer 46 is large, and a leak current is generated in this region. It is prevented.
The semiconductor device 10 according to the present embodiment distributes the amount of crystal defects 70 in the lower layer 46 to prevent leakage current in a region where the crystal defects 70 are small, and electrons in the region 46 where the crystal defects 70 are large. By easily moving, both leakage current prevention and low on-resistance can be achieved.

In addition, the semiconductor device 10 can stably control the amount of current between the source electrode 54 and the drain electrode 32 because the crystal defect high-density region 72 exists at the lower layer 46 side interface below the gate electrode 52. Has the advantage. For example, if the crystal defect high-density region 72 exists below the source electrode 54, the leak current through the crystal defect increases, and the current is turned off even when a voltage lower than the threshold voltage is applied to the gate electrode 52. The situation that cannot be done will occur.
On the other hand, even if the crystal defect high density region 72 exists at the lower layer 46 side interface below the gate electrode 52, the influence of the gate voltage applied to the gate electrode 52 is caused by the heterojunction between the lower layer 46 and the upper layer 48 below the gate electrode 52. Since the interface (heterojunction interface where current can easily flow) can be greatly affected, it is possible to stably adjust the amount of current based on the gate voltage.
In the semiconductor device 10 of this embodiment, the crystal defect high-density region 72 penetrates the lower layer 46 in the layer thickness direction. Therefore, the electrons that have moved into the lower layer 46 below the gate electrode 52 can move to the drain electrode 32 across the crystal defect high-density region 72. A semiconductor device with extremely low on-resistance can be obtained.
Further, in the heterojunction semiconductor device 10 of this embodiment, the gate electrode 52 extends outward beyond the region facing the crystal defect high-density region 72. When the gate electrode 52 extends, the amount of electrons induced by the gate-on voltage can be increased in the potential well below this portion. In other words, since the gate electrode 52 is formed so as to be opposed to the region moving in the lateral direction along the heterojunction interface, the resistance of the lateral movement can be lowered, and the on-resistance can be further reduced. Has the advantage.

Next, a method for manufacturing the semiconductor device 10 of this embodiment will be described with reference to FIGS.
As shown in FIG. 4, first, a sapphire substrate 22 is prepared. Instead of the sapphire substrate 22, for example, a substrate made of a material such as a silicon substrate, a silicon carbide substrate, or a gallium arsenide substrate can be used. A buffer layer 24 is formed on the sapphire substrate 22 with a layer thickness of about 50 nm by metal organic vapor phase epitaxy (MOCVD) at a low temperature. At this time, trimethylgallium (TMGa) can be preferably used as the gallium source, and ammonia gas (NH ₃ ) can be preferably used as the nitrogen source. The material of the buffer layer 24 may be the same crystal as the compound crystal formed on the buffer layer 24 in the next step, or a crystal having a similar lattice constant and thermal expansion coefficient.
Next, a silicon oxide layer 26 (an example of an epitaxial growth prohibiting member) having an opening width L26 is patterned on the buffer layer 24 by sputtering or CVD. The silicon oxide layers 26 are formed in a dispersed manner, for example, in a stripe shape when viewed in plan.

Next, as shown in FIG. 5, a drain layer 42 made of n-GaN is formed on the buffer layer 24 by metal organic vapor phase epitaxy. At this time, trimethylgallium (TMGa) can be preferably used as the gallium source, ammonia gas (NH ₃ ) as the nitrogen source, and monosilane (SiH ₄ ) as the dopant material.
In the step of forming the drain layer 42, a technique of so-called selective lateral growth can be preferably used. In the selective lateral growth method using the metal organic vapor phase epitaxy method, a group III organic metal and a group V hydride chemically react in a hydrogen atmosphere to grow crystals. When the crystal is grown by the selective lateral growth method, the GaN crystal grown in the layer thickness direction (up and down direction in the drawing) from the opening of the silicon oxide layer 26 does not coincide with the sapphire substrate 22 and the lattice constant and the like, and thus has crystal defects. Many of the crystal defect high density regions 72 through which dislocations penetrate are formed. On the other hand, in the region above the silicon oxide layer 26, since the GaN crystal cannot grow from the silicon oxide layer 26, the GaN crystal grows in the lateral direction and dislocations are formed by bending horizontally. The region above the silicon oxide layer 26 is a region with few crystal defects (crystal defect low density region).
If necessary, the surface of the grown drain layer 42 can be planarized by setting the conditions such that the crystal growth is faster in the horizontal direction than in the vertical direction (for example, adjusting the temperature, gas flow rate, etc.). At this stage, the sapphire substrate 22, the buffer layer 24, and the silicon oxide layer 26 on the back surface side may be polished and removed. In this embodiment, an example of not removing is shown.

Next, a lower layer 46 made of GaN is formed with a layer thickness of about 10 μm by using a metal organic vapor phase epitaxial method. At this time, trimethylgallium (TMGa) can be preferably used as the gallium source, and ammonia gas (NH ₃ ) can be preferably used as the nitrogen source. The lower layer 46 may be made n-type by using monosilane (SiH ₄ ) as a dopant material.
Further, the upper layer 48 made of AlGaN is formed with a film thickness of about 25 nm by using a metal organic vapor phase epitaxial method. At this time, trimethylaluminum (TMAl) can be preferably used as the aluminum source, trimethylgallium (TMGa) as the gallium source, and ammonia gas (NH ₃ ) as the nitrogen source.
As shown in FIG. 6, the crystal defect high density region 72 penetrates the drain layer 42, the lower layer 46, and the upper layer 48 and propagates in the layer thickness direction.

Next, the back side sapphire substrate 22, the buffer layer 24, and the silicon oxide layer 26 are polished, and the drain layer 42 is further polished to a desired layer thickness. In order to reduce the damage on the polished surface, the polished surface may be etched using RIE or the like. Thereafter, as shown in FIG. 7, titanium (Ti) and aluminum (Al) are sequentially deposited to form the drain electrode 32.
Next, titanium (Ti) and aluminum (Al) are sequentially deposited on the surface of the upper layer 48. Thereafter, the source electrode 54 is patterned using a photo process and an etching technique. The source electrode 54 is patterned on the surface of the upper layer 48 so as to face a region other than the crystal defect high density region 72 (crystal defect low density region). After patterning, heat treatment is performed at 550 ° C. for 30 seconds by RTA (Rapid Thermal Anneal) method. The contact resistance of the source electrode 54 with respect to the upper layer 48 is reduced, and ohmic contact is realized.
Next, the gate electrode 52 is formed using a lift-off method. That is, after a resist film is formed in a place other than where the gate electrode 44 is to be formed, nickel (Ni) and gold (Au) are sequentially deposited. Thereafter, the nickel (Ni) and gold (Au) formed on the resist film together with the resist film are peeled off. Thereby, the gate electrode 52 can be formed at a desired position. The gate electrode 52 is formed on the surface of the upper layer 48 so as to face the crystal defect high density region 72. Here, L26 in the figure is the opening width of the silicon oxide layer 26 polished and removed in the previous step. The width L52 of the gate electrode 52 is formed larger than the opening width L26 of the silicon oxide layer 26, and is formed to extend outward from the outer peripheral contour of the opening by a width D52.
The positions where the gate electrode 52 and the source electrode 54 are formed can also be formed based on the amount of crystal defects that appear on the surface of the upper layer 48, for example.
Through the above steps, the semiconductor device of this embodiment can be obtained.

The semiconductor device 10 may be the following modification.
In the semiconductor device 110 shown in FIG. 8, the gate electrode 152 is formed on the surface of the upper layer facing the outer peripheral contour of the crystal defect high density region 172 existing at the lower layer 146 side interface among the interfaces where the upper layer 148 and the lower layer 146 are in contact. Yes. The gate electrode 152 is not formed at a position facing the inside of the crystal defect high density region 172.
Even in this case, when off, a state in which no electrons exist at the heterojunction interface can be created by the gate-off voltage of the gate electrode 152 facing the outer peripheral contour, so that a high-density crystal defect region below the gate electrode 152 from below the source electrode 154 The situation where electrons flow into 172 can be prevented, and leakage current can be prevented from flowing. In addition, since the heterojunction interface below the source electrode 154 has good crystallinity, the occurrence of leakage current in this region is prevented. Further, since the gate electrode 152 extends outward beyond the region facing the crystal defect high-density region 172, many electrons are generated in the potential well below the extending portion by the gate-on voltage when turned on. Can be induced, so that the on-resistance can be reduced.
In the semiconductor device 210 illustrated in FIG. 9, an insulating region 262 made of silicon oxide is formed in a region (crystal defect low density region) other than the crystal defect high density region 272 in the lower layer 146. This insulating region 262 may be formed of a p-type semiconductor region.
The presence of the insulating region 262 can increase the resistance on the crystal defect low density region side in the lower layer 246. As a result, leakage current can be suppressed from flowing in the lower layer 246 in the region below the source electrode 254 (which coincides with the crystal defect low density region).

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In the above embodiment, a GaN-based compound semiconductor has been described as an example, but a GaAs (gallium arsenide) -based compound semiconductor, InP (indium phosphide), or the like may be used instead.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

The principal part sectional drawing of the semiconductor device of an Example is shown. Current flow when on. The energy band diagram of the semiconductor device of an Example is shown. The manufacturing method of the semiconductor device of an Example is shown (1). The manufacturing method of the semiconductor device of an Example is shown (2). The manufacturing method of the semiconductor device of an Example is shown (3). The manufacturing method of the semiconductor device of an Example is shown (4). A modification of the semiconductor device of the embodiment is shown (1). A modification of the semiconductor device of the embodiment is shown (2).

Explanation of symbols

22: sapphire substrate 24: buffer layer 26: silicon oxide layer 32: drain electrode 42: drain layer 46: lower layer 48: upper layer 52: gate electrode 54: source electrode 70: crystal defect 72: crystal defect high density region 262: insulating region

Claims (6)

A lower layer of a III-V compound semiconductor;
An upper layer of a III-V compound semiconductor that is heterojunction with the lower layer and has a band gap larger than that of the lower layer;
A main electrode formed on a part of the surface of the upper layer;
A gate electrode formed on another part of the surface of the upper layer;
With
In the lower layer, the crystal defect high density region and the crystal defect low density region are distributed in a plane parallel to the heterojunction interface,
The main electrode is formed in a region facing the crystal defect low density region,
The heterojunction type III-V group compound semiconductor device, wherein the gate electrode is formed in a region facing the crystal defect high density region.   2. The semiconductor device according to claim 1, wherein the gate electrode is formed beyond a region facing the crystal defect high density region.   3. The semiconductor device according to claim 1, wherein an insulating region is formed in a part of the crystal defect low density region in the lower layer.   4. The semiconductor device according to claim 3, wherein the insulating region is formed outside a range where a two-dimensional electron gas generated at the heterojunction interface exists. Preparing a semiconductor substrate;
Forming an epitaxial growth prohibiting member in which openings are dispersedly arranged on the surface of the semiconductor substrate;
Forming a lower layer by epitaxially growing a III-V compound from the surface of the semiconductor substrate exposed at the opening of the epitaxial growth prohibiting member;
Forming an upper layer from the surface of the lower layer by epitaxially growing a III-V group compound having a band gap larger than the band gap of the lower group III-V compound;
Forming a main electrode on the surface of the upper layer in the region facing the epitaxial growth prohibiting member;
Forming a gate electrode on the surface of the upper layer of the region facing the opening;
A method of manufacturing a heterojunction type III-V compound semiconductor device comprising:   6. The method according to claim 5, wherein in the gate electrode forming step, the gate electrode is formed beyond a region facing the opening.

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