TWI740457B - Semiconductor structure and semiconductor device - Google Patents

Abstract

A semiconductor structure and a semiconductor device are provided in the present disclosure, including a substrate, a seed layer on the substrate, a buffer layer on the seed layer, a back barrier layer on the seed layer, a channel layer on the back layer, and a front barrier layer on the channel layer. The back barrier layer has polarity of V group element.

Description

Semiconductor structure and semiconductor device

The present disclosure relates to a semiconductor structure, and particularly relates to a semiconductor structure with a back barrier layer.

GaN-based semiconductor materials have many excellent material properties, such as high heat resistance, wide band-gap, and high electron saturation rate. Therefore, GaN-based semiconductor materials are suitable for high-speed and high-temperature operating environments. In recent years, GaN-based semiconductor materials have been widely used in light emitting diode (LED) devices and high-frequency devices, such as high electron mobility transistors (HEMTs) with heterogeneous interface structures. ).

Although the high electron mobility transistor package structures manufactured in the prior art can roughly meet their original intended use, they still do not fully meet the requirements in all aspects. For example, the current structure is prone to cause surface polarization during the operation of the device, resulting in surface channels, which in turn causes problems such as current collapse and affects the operation of the device. Therefore, the development of structures and manufacturing methods that can further improve the performance and reliability of high electron mobility transistor devices is still one of the current research topics in the industry.

The embodiment of the present invention provides a semiconductor structure including a substrate, a seed layer on the substrate, a buffer layer on the seed layer, a back barrier layer on the buffer layer, a channel layer on the back barrier layer, and a The front barrier layer on the channel layer. The back barrier layer has group V element polarity.

The embodiment of the present invention also provides a semiconductor device including the aforementioned semiconductor structure, a gate electrode on the semiconductor structure, a source electrode and a drain electrode on opposite sides of the gate electrode.

In order to make the features of the present disclosure obvious and easy to understand, the following examples are specially cited, in conjunction with the accompanying drawings, and detailed descriptions are as follows. For other precautions, please refer to the technical field.

Various embodiments or examples are provided below for implementing different elements of the provided semiconductor structure. If it is mentioned in the description that the first part is formed on the second part, it may include an embodiment in which the first and second parts are in direct contact, or may include additional parts formed between the first and second parts, so that the first An embodiment in which the second component is not in direct contact. In addition, the embodiments of the present invention may use repeated component symbols in many examples. These repetitions are only for the purpose of simplification and clarity, and do not represent a specific relationship between the various embodiments and/or configurations discussed.

Furthermore, related terms in space, such as "front", "back", "above", "below", "above...", "below" and similar terms, except for including pictures In addition to the orientation shown in the formula, it also includes the different orientations of the device in use or operation. When the device is turned to other orientations (rotated by 90 degrees or other orientations), the relative description of the space used here can also be interpreted according to the rotated orientation.

Here, the terms "about", "approximately", and "approximately" usually mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the manual is an approximate quantity, that is, without specifying "about", "approximately", "approximately", "about", "approximately" and "approximately" can still be implied. The meaning of "probably".

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. It is understandable that these terms, such as those defined in commonly used dictionaries, should be interpreted as having meaning consistent with the relevant technology and the background or context of this disclosure, and should not be interpreted in an idealized or excessively formal way. Unless there is a special definition in the embodiment of the present disclosure.

The semiconductor structure with the back barrier layer provided by the embodiment of the present invention can prevent current collapse due to the surface polarization effect. In addition, by providing barrier layers on the upper and lower surfaces of the channel layer and making them polarized, two potential wells are generated in the channel layer close to the two barrier layers and there are two conductive channels, which can confine and control the carrier in There are two conductive channels to improve the stability and reliability of the semiconductor device.

Please refer to Figure 1 first. FIG. 1 is a schematic cross-sectional view of an exemplary semiconductor structure according to some embodiments of the present invention. In some embodiments, the semiconductor structure includes the substrate 102. The substrate 102 may include, for example, a ceramic substrate 102C and a pair of barrier layers 102B respectively provided on the upper and lower surfaces of the ceramic substrate 102C. The substrate 102 may be, for example, a silicon on insulator (SOI) substrate.

In some embodiments, the ceramic substrate 102C includes a ceramic material. Ceramic materials include metallic inorganic materials. In some embodiments, the ceramic substrate 102C may include silicon carbide, aluminum nitride (AlN), sapphire substrate, or other suitable materials. The above-mentioned sapphire substrate may be alumina.

In some embodiments, the barrier layer 102B on the upper and lower surfaces of the ceramic substrate 102C may include a single or multiple layers of insulating material and/or other suitable material layers, such as semiconductor layers. The insulating material layer may be oxide, nitride, oxynitride, or other suitable insulating materials. The semiconductor layer may be polysilicon. The barrier layer 102B can prevent the diffusion of the ceramic substrate 102C, and can also prevent the ceramic substrate 102C from interacting with other membrane layers or process tools. In some embodiments, the barrier layer 102B may also encapsulate the ceramic substrate 102C. At this time, the barrier layer 102B not only covers the upper and lower surfaces of 102C, but also covers both sides of 102C.

Next, continuing to refer to FIG. 1, a seed layer 104 is formed on the substrate 102. In some embodiments, the seed layer 104 may be formed of silicon (Si), aluminum nitride (AlN), or other suitable materials. In some embodiments, the seed layer 104 may include one or more layers of suitable materials. For example, the seed layer 104 may include an aluminum nitride layer grown at a low temperature and another aluminum nitride layer grown at a high temperature on the substrate 102. In some embodiments, the aluminum nitride layer grown at a low temperature has a thickness of about 0.5-2 nanometers (nm), and then another aluminum nitride layer grown at a high temperature has a thickness of about 100-300 nanometers (nm). In the related drawings of this example, only a single layer of the seed layer 104 is shown in order to clearly illustrate the formation method of the semiconductor structure.

In some embodiments, the method for forming the seed layer 104 may include a selective epitaxy growth (SEG) process, a chemical vapor deposition (CVD) process, and a molecular-beam epitaxy process (molecular-beam epitaxy). beam epitaxy (MBE), solid-phase epitaxial recrystallization (SPER) step after deposition of doped amorphous semiconductor (such as Si), by direct seed transfer, or other suitable manufacturing processes . The chemical vapor deposition process is, for example, a vapor-phase epitaxy (VPE) process, a low pressure chemical vapor deposition (LPCVD) process, and an ultra-high vacuum chemical vapor deposition (ultra-high vacuum chemical vapor deposition) process. vapor deposition (UHV-CVD) process, or other suitable processes.

Next, continuing to refer to FIG. 1, the buffer layer 110 is formed on the substrate 102. In some embodiments, the buffer layer 110 includes a superlattice layer 106 and a resistance layer 108 on the superlattice layer 106.

In some embodiments, the superlattice layer 106 can provide stress buffer and greatly reduce the warpage of the wafer.

In some embodiments, the superlattice layer 106 may be formed by stacking repeating units composed of two III-V group compounds. For example, the repeating unit can be composed of binary and ternary III-V compounds.

In some embodiments, the superlattice layer 106 may be a material layer formed of only one type of repeating unit. Specifically, the repeating unit may be composed of aluminum nitride (AlN) and aluminum gallium nitride (AlGaN). In some embodiments, the superlattice layer 106 may also be a material layer formed of multiple repeating units. For example, one of the repeating units may be composed of aluminum nitride (AlN) and aluminum gallium nitride (Al _x Ga _1-x N), and the other repeating unit may be aluminum nitride (AlN) and aluminum gallium nitride (AlN) and aluminum gallium nitride (Al x Ga 1-x N). Al _y Ga _1-y N), where x and y are not the same. In some embodiments, the repeating unit far from the substrate 102 in the superlattice layer 106 has a higher aluminum mol fraction, while the repeating unit close to the substrate 102 has a lower aluminum mol fraction. In some embodiments, the total thickness of the repeating units far from the substrate 102 in the superlattice layer 106 is about 1 to 5 microns (μm), and the total thickness of the repeating units near the substrate 102 is about 0.4 to 1.5 microns (μm). . In the related drawings of this example, only the single-layer superlattice layer 106 is shown to illustrate the repeating unit therein, and the method for forming the semiconductor structure is clearly illustrated.

In some embodiments, the method for forming the superlattice layer 106 may include hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), one of the foregoing methods Combination or similar methods.

In some embodiments, the superlattice layer 106 may be more doped to facilitate the generation of holes and increase the resistance to prevent leakage current. The dopant may be a p-type dopant, such as iron (Fe) or carbon (C).

In some embodiments, the resistance layer 108 can be used as an electrical resistance layer to reduce the leakage current of the device. In some embodiments, the resistance layer 108 may include a group III-V compound. In some embodiments, the resistance layer 108 may be a binary or ternary III-V compound, such as gallium nitride (GaN).

In some embodiments, the material of the resistance layer 108 has a lower energy gap than the material of the back barrier layer 112 on the resistance layer 108, so as to improve the epitaxial quality of the resistance layer, reduce epitaxial defects and suppress leakage current. For example, the back barrier layer 112 may be a III-V compound containing aluminum (Al) while the resistance layer 108 does not contain aluminum (Al). Alternatively, the back barrier layer 112 and the resistance layer 108 are both III-V compounds containing aluminum (Al), but the resistance layer 108 has a lower aluminum (Al) molar fraction. The back barrier layer 112 may be listed as Al _z1 Ga _1-z1 N, the resistance layer 108 is Al _z2 Ga _1-z2 N, and z1>z2. The detailed description of the back barrier layer 112 can be referred to later.

In some embodiments, the resistance layer 108 has a thickness of about 0.5-5 micrometers (μm).

In some embodiments, the method for forming the resistance layer 108 may include hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), a combination of the foregoing methods, or Similar method.

In some embodiments, the resistance layer 108 may be more doped to prevent the carriers in the conductive channel 120 from being trapped by the resistance layer 108. The dopant may be a p-type dopant, such as iron (Fe) or carbon (C), and has a doping concentration of ^{1×10 19} cm ⁻³ to about 5× ^{10 20} cm ^−3.

Next, continuing to refer to FIG. 1, a back barrier layer 112, a channel layer 114 and a front barrier layer 116 are sequentially formed on the buffer layer 110.

In some embodiments, the back barrier layer 112 has III or V group element polarity. In some embodiments, the front barrier layer 116 has a group III element polarity.

In some embodiments, group V elements include non-metallic elements, such as nitrogen (N), phosphorus (P), arsenic (As), etc., and the polarity of group V elements includes the polarity of non-metal elements, such as nitrogen polarity (N-polar ), phosphorus polarity (P-polar), arsenic polarity (As-polar).

In some embodiments, group III elements include metal elements, such as aluminum (Al), gallium (Ga), indium (In), thallium (Tl), etc., while group III elements have polar metal elements, such as aluminum polarity (Al -polar), gallium (Ga-polar), indium (In-polar), thallium (Tl-polar).

Generally speaking, the III-V group compound may have the polarity of the group III element or the polarity of the group V element. Refer to FIG. 2 together. FIG. 2 takes gallium nitride (GaN) as an example, and illustrates a schematic diagram of a lattice arrangement of gallium nitride (GaN) with gallium polarity and nitrogen polarity.

Since the electronegativity of nitrogen atoms and gallium atoms is very different, and gallium nitride is the most densely packed hexagonal, the gallium nitride bond (Ga-N bond) has a dipole moment, resulting in internal Build-in polarization. Therefore, the III-V group compound with polarity will tilt its potential energy, and it is easier to control the formation position of the carrier.

]方向成長的氮化鎵(GaN)的極性稱之為鎵面(Ga-face)或鎵極性，如第2圖左側所示。而將沿著[000

]方向成長的氮化鎵(GaN)的極性稱之為氮面(N-face)或氮極性，如第2圖右側所示。 In this field, generally along [000

The polarity of gallium nitride (GaN) grown in the] direction is called Ga-face or gallium polarity, as shown on the left side of Figure 2. And will go along [000

The polarity of gallium nitride (GaN) grown in the] direction is called N-face or nitrogen polarity, as shown on the right side of Figure 2.

Simply put, the difference between the polarity of nitrogen and gallium comes from different formation methods that produce different lattice arrangements, and the two will have opposite polar properties.

In some embodiments, the group III-V compound of nitrogen polarity and the group III-V compound of gallium polarity can be obtained by Plasma Induced Molecular Beam Epitaxy (PIMBE) or metal chemical vapor deposition method. (metalorganic chemical vapor deposition, MOCVD) formation.

It should be noted that the film layer under the back barrier layer 112 (for example, the resistance layer 108) may also have a polarity, such as the polarity of group III elements, which can be arbitrarily adjusted according to actual requirements.

Next, referring to FIG. 3, FIG. 3 is a graph showing the potential energy relationship of the back barrier layer 112, the channel layer 114, and the front barrier layer 116 in FIG. 1 as the depth changes.

Since the channel layer 114 and the front barrier layer 116 and the back barrier layer 112 contain different materials, a heterogeneous interface is generated between the channel layer 114 and the front barrier layer 116 and the back barrier layer 112. Specifically, the channel layer 114 and the front barrier layer 116 and the back barrier layer 112 have materials with different bands, so the interface between the channel layer 114 and the front barrier layer 116 and the back barrier layer 112 The conductive band is bent, and a potential energy well is generated at the junction.

Since the potential energy of the potential energy well is relatively low, the carriers free in the channel layer 114 tend to accumulate to the potential energy well to generate a conductive channel 120, such as two-dimensional electron gas (2DEG).

Refer to Figure 1 and Figure 3 at the same time. In some embodiments, the front barrier layer 116, the channel layer 114, and the back barrier layer 112 are configured to form a first energy well and a second energy well. In detail, the first energy well is located at the interface between the channel layer 114 and the front barrier layer 116, and the second energy well is located at the interface between the channel layer 114 and the back barrier layer 112.

Continue to refer to Figures 1 and 3. In some embodiments, the conductive channel 120 is provided at the potential energy well. In detail, the first conductive channel 1201 and the second conductive channel 1202 are respectively located at the interface between the channel layer 114 and the front barrier layer 116 and the interface between the channel layer 114 and the back barrier layer 112. It can also be said that the position of the conductive channel roughly overlaps the potential energy well. Therefore, the first potential energy well may correspond to the first conductive channel 1201 and the second potential energy well may correspond to the second conductive channel 1202.

In the embodiment of FIG. 3, the potential energy of the back barrier layer 112 with the polarity of the group V element (for example, the nitrogen polarity) and the front barrier layer 116 with the polarity of the group III element (for example, the gallium polarity) are closer to the channel layer. 114 and dropped. This can encourage free carriers to concentrate toward the place where the potential energy drops. This is mainly because the energy gap of the back barrier layer 112 is higher than that of the channel layer 114 and the energy band lifting effect is caused.

In addition, since the polarization degree of the polarity of the group V element and the polarity of the group III element is not the same, the potential energy depth generated by the two is not the same. In the embodiment of FIG. 3, the potential energy depth of the front barrier layer 116 with the polarity of the group III element is greater than that of the back barrier layer 112 with the polarity of the group V element, and therefore the potential energy of the first potential well is lower. The result of the potential energy in the second energy well. In this way, a relatively large number of carriers can be restricted to the conductive channel 1201 corresponding to the first energy well during operation.

Compared with the first potential energy well only at the interface between the front barrier layer 116 and the channel layer 114, the embodiment of the present invention provides a second potential energy well at the interface between the channel layer 114 and the back barrier layer 112 It can concentrate the remaining carriers in the channel layer 114 here, and reduce impact ionization, thereby improving the breakdown voltage and reliability of the device.

In other words, the first conductive channel 1201 and the conductive channel 1202 respectively have different functions. The former allows carriers to flow and conduct, while the latter allows carriers to concentrate and not conduct.

In some embodiments, the front barrier layer 116 and the back barrier layer 112 with polarity can control the position of the conductive channel 120. Specifically, the front barrier layer 116 having the polarity of the group III element (for example, gallium polarity) can make the first conductive channel 1201 be located in the channel layer 114 close to the front barrier layer, and have the polarity of the group V element (for example, the nitrogen polarity) The back barrier layer 112 can make the second conductive channel 1202 be located in the channel layer 114 close to the back barrier layer 112.

Hereinafter, the materials of the back barrier layer 112, the channel layer 114, and the front barrier layer 116 and the forming method thereof will be explained.

In some embodiments, the back barrier layer 112 is a III-V compound containing aluminum (Al), such as aluminum gallium nitride (AlGaN), aluminum nitride (AlN), aluminum indium nitride (AllnN), nitride Aluminum gallium indium (AlGaInN) or a combination thereof, etc.

In some embodiments, the channel layer 114 is a III-V compound that does not contain aluminum (Al), such as gallium nitride (GaN), indium gallium nitride (InGaN), or a combination thereof, and so on. In some embodiments, the front barrier layer 116 is a III-V compound containing aluminum (Al), which can be selected from materials similar to or the same as the back barrier layer 112, and will not be repeated here.

In some embodiments, the front barrier layer 116 and the back barrier layer 112 have the same material to ensure epitaxial uniformity and electrical uniformity.

The channel layer 114 does not contain aluminum (Al) and the front barrier layer 116 and the back barrier layer 112 contain aluminum (Al), so that the material of the front barrier layer 116 and the back barrier layer 112 is more than that of the channel layer 114 The material has a high band gap. For example, the energy gap of gallium nitride (GaN) is 3.4eV, the energy gap of aluminum nitride (AlN) is 6.2eV, and the energy gap of aluminum gallium nitride (AlGaN) should be between Between the two, for example 4.35eV. Thereby, a heterogeneous interface can be generated between the channel layer 114 and the front barrier layer 116 and the back barrier layer 112 to generate the first conductive channel 1201 and the second conductive channel 1202.

In some embodiments, the front barrier layer 116 and the back barrier layer 112 may include aluminum nitride (AlN). Because aluminum nitride (AlN) can provide a higher energy gap to provide a deeper potential energy well. In one embodiment, aluminum nitride is used as the back barrier layer 112 to provide sufficient carriers from the channel layer to further avoid surface channels.

In addition, providing a higher energy gap back barrier layer 112 between the channel layer 114 and the buffer layer 110 can change the potential energy changes under the channel layer 114 (refer to Figure 3), such as raising the potential energy to limit The carriers are in the channel layer 114.

It should be noted that the materials and their energy gaps listed here are only illustrative, and those skilled in the art can still apply other materials based on this principle.

In some embodiments, the back barrier layer 112 has a thickness of about 5-25 nanometers (nm), the channel layer 114 has a thickness of about 200-500 nanometers (nm), and the front barrier layer 116 has a thickness of about 5-25 nanometers (nm). Nanometer (nm) thickness.

In some embodiments, the back barrier layer 112 may or may not have dopants. In the case of dopants, it is more conducive to increase the breakdown voltage of the semiconductor structure. The dopant may be a p-type dopant, such as carbon (C) or iron (Fe), and has a doping concentration of ^{1×10 19} cm ⁻³ to about 5× ^{10 20} cm ^−3. In some embodiments, the channel layer 114 is unintentionally doped (UID), and thus has free carriers therein. In some embodiments, the front barrier layer 116 is unintentionally doped (UID).

Since epitaxial defects are generated during the epitaxial process, electron traps (donor traps) are formed to contribute to N-type impurities. In this article, "unintentional doping" should be understood as dopants caused by epitaxial defects. Generally, about equivalent to the unintentionally doped with a doping concentration of less than about 5x10 ¹⁹ cm ^-3, for example about 1x10 ¹⁹ cm ^-3.

In some embodiments, both the back barrier layer 112 and the underlying film layer (such as the buffer layer) can have p-type dopants (such as carbon (C)), and the doping concentration can gradually decrease as it approaches the substrate to prevent the underlying The film has a leakage path.

In some embodiments, the formation of the front barrier layer 116, the channel layer 114, and the back barrier layer 112 may include molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), and hydride vapor phase epitaxy. Crystal method (HVPE), other appropriate methods, or a combination of the above methods.

Compared with the case where there is only the front barrier layer 116, the embodiment of the present invention further provides a back barrier layer 112, which can increase the potential energy between the channel layer and the underlying film layer, and not only prevents free carriers in the channel layer 114 Moving to the lower film layer can also prevent the surface polarization during operation and capture electrons to form surface channels, and then the problem of current collapse.

That is to say, in the embodiment of the present invention, the back barrier layer 112 is disposed under the channel layer 114 to reduce the surface polarization, thereby reducing the surface field (reduced surface field, RESURF), and achieve the effects of suppressing current collapse and increasing the collapse voltage.

In addition, disposing the back barrier layer in the embodiment of the present invention on the substrate having the barrier layer and the ceramic base material can reduce the warpage and improve the semiconductor performance.

FIG. 4 is a schematic cross-sectional view of an exemplary semiconductor structure according to other embodiments of the present invention. The difference between FIG. 4 and FIG. 1 is that a pair of back barrier layer 112 and resistance layer 108 are additionally provided on the buffer layer 108. Specifically, the resistance layer 108/back barrier layer 112/resistance layer 108/back barrier layer 112 are alternately stacked on the superlattice layer 106. In this embodiment, leakage current can be further prevented to increase the breakdown voltage.

In addition, the two back barrier layers 112 can be made of the same or similar materials, and the two resistance layers 108 can also be made of the same or similar materials and have the same or similar dopants. The dopant can be a p-type dopant, such as carbon (C) or iron (Fe), to increase resistance and prevent leakage current.

In the embodiment of Figure 4, the back barrier layer 112 of higher energy gap material is inserted between the two resistance layers 108, which not only can further prevent the leakage of carriers to the substrate, but also help adjust the stress and make the substrate Not easy to warp.

FIG. 5 is a schematic cross-sectional view of an exemplary semiconductor structure according to other embodiments of the present invention. The difference between FIG. 5 and FIG. 1 is that the back barrier layer 112 is a composite layer including a first back barrier layer 112a and a second back barrier layer 112b. Specifically, the first back barrier layer 112 a is close to the channel layer 114 and the second back barrier layer 112 b is far away from the channel layer 114. The first back barrier layer 112a and the second back barrier layer 112b may be any two of III-V compounds including aluminum (Al), for example, the first back barrier layer 112a may be aluminum butide (AlN) The second back barrier layer 112b is aluminum gallium nitride (AlGaN). By forming the composite layer as the back barrier layer 112, the back barrier layer 112 and the underlying film layer can be prevented from generating parasitic two-dimensional hole gas (two dimensional hole gas, 2DHG) and affecting the semiconductor performance, and the substrate 102 can be prevented from occurring. The problem of bending.

In some embodiments, the energy gap of the material of the first back barrier layer 112a is higher than the energy gap of the material of the second back barrier layer 112b. By the first back barrier layer 112a with a higher energy gap, the carriers in the channel layer 114 can be prevented from migrating to the channel layer 114 (for example, in the back barrier layer 112), and by the second back barrier with a lower energy gap The barrier layer 112b can reduce the energy gap difference between the back barrier layer 112 and the underlying film layer (for example, the buffer layer 110), so as to reduce the generation of parasitic two-dimensional hole gas (2DHG).

FIG. 6 is a schematic cross-sectional view of an exemplary semiconductor device according to other embodiments of the present invention. In some embodiments, the semiconductor device is a high electron mobility transistor (HEMT). The difference between FIG. 6 and FIG. 1 is that the gate electrode G on the front barrier layer 116 is further provided on the front barrier layer 116, and the source electrode S and the drain electrode are located on opposite sides of the gate electrode G. Electrode D, and a doped compound semiconductor layer GP is disposed under the gate electrode G.

In some embodiments, the material of the gate electrode G may be a conductive material, such as a metal, a metal nitride, or a semiconductor material. In some embodiments, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, a combination of the foregoing, or multiple layers of the foregoing. The semiconductor material can be polycrystalline silicon or polycrystalline germanium. The above-mentioned conductive material can be formed by, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) (for example, sputtering) ), resistance heating evaporation method, electron beam evaporation method, or other suitable deposition methods are formed on the front barrier layer 116, and then the gate electrode G is formed through a patterning process.

In some embodiments, before forming the gate electrode G, a doped compound semiconductor layer GP may be formed on the front barrier layer 116 first, and then the gate electrode G may be successively formed on the doped compound semiconductor layer GP. By forming a doped compound semiconductor layer GP between the gate electrode G and the front barrier layer 116, the generation of two-dimensional electron gas (2DEG) under the gate electrode G can be suppressed, so as to achieve the normally-off state of the semiconductor structure .

In some embodiments, the material of the doped compound semiconductor layer GP may be a III-V group compound with p-type dopants or n-type dopants, such as gallium nitride (GaN). In some embodiments, the p-type dopant may include magnesium (Mg), carbon (C), etc., and have a doping concentration of ^{about 1×10 17} cm ⁻³ to about 1×10 ²¹ cm ^−3.

In some embodiments, the doped compound semiconductor layer GP has a thickness of about 50-200 nanometers (nm).

The step of forming the doped compound semiconductor layer GP may include depositing a doped compound semiconductor layer (not shown) on the front barrier layer 116 by an epitaxial growth process and performing a patterning process on it to form a doped compound semiconductor layer. The compound semiconductor layer GP corresponds to a position where the gate electrode G is scheduled to be formed.

In some embodiments, the gate electrode G is connected to the doped compound semiconductor layer GP. A Schottky contact is formed between the gate electrode G and the doped compound semiconductor layer GP.

In some embodiments, the source electrode S and the drain electrode D formed on opposite sides of the gate electrode G may include the same or similar materials to the gate electrode G and may be formed in the same deposition process. No longer.

FIG. 7 is a schematic cross-sectional view of an exemplary semiconductor device according to other embodiments of the present invention. The difference between FIG. 7 and FIG. 6 is that the source electrode S and the drain electrode D pass through the front barrier layer 116 and contact the channel layer 114. In detail, the bottom surfaces of the source electrode S and the drain electrode D are flush with the top surface of the channel layer 114. In this way, the contact area can be increased and the contact resistance can be reduced.

FIG. 8 is a schematic cross-sectional view of an exemplary semiconductor device according to other embodiments of the present invention. The difference between FIG. 8 and FIG. 7 is that the source electrode S and the drain electrode pass through a part of the channel layer 114 but do not contact the back barrier layer 112. In detail, the source electrode S and the drain D electrode only pass through the first conductive channel 1201 but do not contact the second conductive channel 1202, so as to prevent the carriers of the second conductive channel 1202 from flowing and generating leakage current.

FIG. 9 is a schematic cross-sectional view of an exemplary semiconductor device according to other embodiments of the present invention. The difference between FIG. 9 and FIG. 7 is that the cap layer 118 replaces the doped compound semiconductor layer GP, and the cap layer 118 extends below the source electrode S and the drain electrode D. In detail, the cap layer 118 includes a III-V compound, such as gallium nitride (GaN). In some embodiments, the cap layer 118 is non-intentionally doped.

In the process of forming the gate electrode G, the source electrode S, and the drain electrode D, a high-temperature environment and a high-energy plasma source are usually required. However, in this high-temperature and high-energy process, the surface of the underlying film layer (such as the front barrier layer 116) is easily damaged, and many charged defects (traps) are generated, thereby affecting the performance of the manufactured semiconductor device. Therefore, the cap layer 118 can protect the underlying film layer from damage.

In some embodiments, the cap layer 118 and the doped compound semiconductor layer GP may exist at the same time (not shown) to protect the semiconductor device and make the semiconductor device normally off.

In summary, the embodiment of the present invention provides a back barrier layer and a front barrier layer on both sides of the channel layer, which can generate two conductive channels in the channel layer, which not only reduces the surface electric field generated by surface polarization, but also It can also prevent the underlying film layer (such as the resistance layer) from capturing electrons and improve the breakdown current. In addition, by making the back barrier layer and the front barrier layer have different polarities, the carriers can be confined in the channel layer. Furthermore, by making the back barrier layer have dopants, the current can be prevented from leaking to the underlying film layer, so as to improve the breakdown voltage. By disposing the back barrier layer on a substrate having a ceramic substrate and a barrier layer disposed on and on the lower surface of the ceramic substrate, the warpage of the substrate can be adjusted, and the dynamic on-resistance can be further reduced. In other words, the embodiments of the present invention can improve the operation stability and reliability of the semiconductor device by using the above-mentioned features.

Several embodiments are summarized above so that those with ordinary knowledge in the technical field of the present invention can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can design or modify other manufacturing processes and structures based on the embodiments of the present invention to achieve the same purposes and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field of the present invention should also understand that such equivalent manufacturing processes and structures do not depart from the spirit and scope of the present invention, and they can do so without departing from the spirit and scope of the present invention. Make all kinds of changes, substitutions and replacements.

102: substrate 102B: Barrier layer 102C: Ceramic substrate 104: Seed layer 106: Superlattice layer 108: impedance layer 110: buffer layer 112: Back Barrier 112a: first back barrier layer 112b: second back barrier layer 114: Channel layer 116: front barrier layer 118: cap layer 120: Conductive channel 1201: The first conductive channel 1202: second conductive channel D: Drain electrode G: Gate electrode GP: doped compound semiconductor layer S: source electrode

The embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, according to standard practices in the industry, various features are not drawn to scale and are only used for illustration and illustration. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the characteristics of the embodiment of the present invention. FIG. 1 is a schematic cross-sectional view of an exemplary semiconductor structure according to some embodiments of the present invention. FIG. 2 is a schematic diagram of gallium nitride (GaN) as an example, showing that the gallium nitride (GaN) is a lattice arrangement of gallium polarity and nitrogen polarity. Figure 3 is a graph showing the potential energy relationship of the back barrier layer, the channel layer and the front barrier layer in Figure 1 as the depth changes. FIGS. 4-5 are schematic cross-sectional diagrams illustrating exemplary semiconductor structures according to other embodiments of the present invention. FIGS. 6-9 are schematic cross-sectional views illustrating exemplary semiconductor devices according to other embodiments of the present invention.

102: substrate

102B: Barrier layer

102C: Ceramic substrate

104: Seed layer

106: Superlattice layer

108: impedance layer

110: buffer layer

112: Back Barrier

114: Channel layer

116: front barrier layer

120: Conductive channel

1201: The first conductive channel

1202: second conductive channel

Claims (19)

A semiconductor structure includes: a substrate; a seed layer located on the substrate; a buffer layer located on the seed layer; a back barrier layer located on the buffer layer and having group V Element polarity; a channel layer located on the back barrier layer; and a front barrier layer (front barrier) located on the channel layer, wherein the front barrier layer has a group III element polarity. For example, the semiconductor structure of claim 1, further comprising a first conductive channel and a second conductive channel respectively located at the interface between the channel layer and the front barrier layer and the interface between the channel layer and the back barrier layer. The semiconductor structure of claim 1, wherein the back barrier layer has a dopant, and the dopant is a p-type dopant. The semiconductor structure of claim 1, wherein the back barrier layer is a III-V compound including aluminum (Al). The semiconductor structure of claim 1, wherein the back barrier layer includes aluminum gallium nitride (AlGaN), aluminum nitride (AlN), aluminum indium nitride (AllnN), aluminum gallium indium nitride (AlGaInN), or a combination thereof. The semiconductor structure of claim 1, wherein the front barrier layer and the back barrier layer have the same material. Such as the semiconductor structure of claim 1, wherein the back barrier layer is a nitrogen Polar aluminum gallium nitride (AlGaN). The semiconductor structure of claim 1, wherein the back barrier layer includes a first back barrier layer close to the channel layer and a second back barrier layer far from the channel layer, wherein the first back barrier layer The energy gap of the material is higher than the energy gap of the material of the second back barrier layer. The semiconductor structure of claim 1, wherein the buffer layer includes a resistive layer under the back barrier layer. The semiconductor structure of claim 9, wherein the resistance layer has a dopant, and the dopant is carbon (C) or iron (Fe). The semiconductor structure of claim 9, wherein the energy gap of the material of the back barrier layer is higher than the energy gap of the material of the resistance layer. The semiconductor structure of claim 9, wherein the semiconductor structure further includes another back barrier layer on the resistance layer and another resistance layer on the other back barrier layer. The semiconductor structure of claim 12, wherein the resistance layers and the back barrier layers all have dopants, and the dopants include carbon (C) or iron (Fe). The semiconductor structure of claim 1, wherein the front barrier layer is a gallium-polarized aluminum gallium nitride (AlGaN). The semiconductor structure of claim 1, wherein the energy gaps of the materials of the front barrier layer and the back barrier layer are both higher than the energy gaps of the material of the channel layer. The semiconductor structure of claim 1, wherein the channel layer is an unintentionally doped (UID) III-V compound and does not include aluminum (Al). The semiconductor structure of claim 1, wherein the substrate includes a ceramic A substrate and a pair of barrier layers are respectively provided on the upper and lower surfaces of the ceramic substrate. The semiconductor structure of claim 1, wherein the buffer layer includes a superlattice layer on the seed layer. A semiconductor device, comprising: the semiconductor structure according to any one of claims 1-18; a gate electrode located on the semiconductor structure; and a source electrode and a drain electrode located on opposite sides of the gate electrode .

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