KR20180070039A - Semiconductor device and semiconductor device package having thereof - Google Patents

Abstract

An embodiment of the present invention relates to a semiconductor device and a semiconductor device package including the same. The semiconductor device disclosed in the embodiment of the present invention includes: a first conductive semiconductor layer including a plurality of first recesses; an active layer arranged on the first conductive semiconductor layer; a second conductive semiconductor layer arranged on the active layer; and a cap layer arranged on the active layer and the second conductive semiconductor layer. The cap layer includes a first region arrange don the lateral side of the first recess. The first region includes a lower region whose thickness is thick in a direction from the upper side of the lateral side of the first recess to the lower side of the lateral side of the first recess. Accordingly, the present invention can prevent a current leakage.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor device and a semiconductor device package having the same,

Embodiments relate to semiconductor devices.

An embodiment relates to a semiconductor device package.

Embodiments relate to a lighting device having a semiconductor device or a semiconductor device package.

Semiconductor devices including compounds such as GaN and AlGaN have many merits such as wide and easy bandgap energy, and can be used variously as light emitting devices, light receiving devices, and various diodes.

Particularly, light emitting devices such as light emitting diodes and laser diodes using III-V or II-VI compound semiconductor materials of semiconductors can be used for various applications such as red, Blue, and ultraviolet rays. By using fluorescent materials or combining colors, it is possible to realize a white light beam with high efficiency. Also, compared to conventional light sources such as fluorescent lamps and incandescent lamps, low power consumption, , Safety, and environmental friendliness.

The embodiment provides a semiconductor device in which the thickness at the bottom center of the recess in the light emitting structure layer increases.

The embodiment provides a semiconductor device in which a cap layer is disposed between an active layer and a second conductivity type semiconductor layer, and the cap layer extends on a recess transferred below the light emitting structure layer.

The embodiment provides a semiconductor device in which a cap layer is disposed between an active layer and a second conductivity type semiconductor layer, and the recessed active layer and the cap layer are extended below the light emitting structure layer.

An embodiment provides a semiconductor device in which a first region of a cap layer is disposed on a recess transferred from a lower portion of a light emitting structure layer, and a thickness of a first region of the cap layer is increased toward a lower portion of the recess.

The embodiment provides a semiconductor device for improving a crystal quality of an interface between semiconductor layers by disposing a cap layer having indium between the electron blocking layer and the second conductivity type semiconductor layer.

The embodiment provides a semiconductor device for improving the injection efficiency of carriers by disposing a cap layer having indium between the electron blocking layer and the second conductivity type semiconductor layer.

The embodiment is characterized in that a cap layer having indium is disposed between the electron blocking layer and the second conductivity type semiconductor layer to reduce the thickness of the electron blocking layer and the second conductivity type semiconductor layer, Lt; / RTI >

The embodiment can provide a semiconductor element capable of improving carrier injection efficiency and a semiconductor element package having the semiconductor element.

Embodiments can provide a semiconductor element and a semiconductor device package having the same capable of increasing hole injection efficiency and improving current spreading.

Embodiments can provide a semiconductor device and a semiconductor device package having the semiconductor device capable of improving the light extraction efficiency by improving the reduction of the light emitting area and increasing the carrier injection efficiency.

The semiconductor device of the embodiment includes: a first conductivity type semiconductor layer having a plurality of first recesses; An active layer disposed on the first conductive semiconductor layer; A second conductive semiconductor layer disposed on the active layer; And a cap layer disposed on the active layer and the second conductive type semiconductor layer, wherein the cap layer includes a first region disposed on a side surface of the first recess, And a thicker lower region in the lower side of the first recess at the upper side of the seth.

According to an embodiment, the active layer includes an extension region extending to the side of the first recess, the extension region being disposed between a side of the first recess and a first region of the cap layer.

According to an embodiment of the present invention, an electron blocking layer may be disposed between the cap layer and the active layer.

According to an embodiment, the electron blocking layer may include a first extension disposed between the extended region of the active layer and the first region of the cap layer on the first recess.

According to an embodiment, the cap layer may comprise a semiconductor having indium and aluminum.

According to the embodiment, the cap layer may have a dopant concentration lower than that of the second conductivity type dopant added to the second conductivity type semiconductor layer, or may include an undoped semiconductor.

According to the embodiment, the cap layer may have a thickness smaller than the thickness of the electron blocking layer or the thickness of the second conductivity type semiconductor layer.

According to the embodiment, the first region of the cap layer may become thicker from the lower side of the side of the first recess to the center of the first recess.

According to the embodiment, the first conductive semiconductor layer includes a first semiconductor layer, a second semiconductor layer on which the lower portion of the first recess is disposed on the first semiconductor layer, and a second semiconductor layer disposed between the second semiconductor layer and the active layer. And the first recess may include an extended third semiconductor layer.

The cap layer may be formed of a single layer of InAlGaN semiconductor, and the electron blocking layer may include a plurality of AlGaN-based semiconductor layers. The second conductive semiconductor layer may include a plurality of GaN- .

According to an embodiment, the second conductivity type semiconductor layer may include a first nitride layer undoped over the cap layer, a second nitride layer having a second conductivity type dopant concentration on the first nitride layer, a second nitride layer having a second conductivity type dopant concentration on the second nitride layer, A doped third nitride layer and a fourth nitride layer having a dopant concentration higher than the dopant concentration of the second nitride layer over the third nitride layer.

According to the embodiment, the second conductivity type semiconductor layer may have a protrusion protruding in the first recess direction.

According to an embodiment of the present invention, a transparent electrode layer may be formed on the second conductive semiconductor layer.

The semiconductor device package according to the embodiment may include the semiconductor device described above.

The embodiment can arrange a cap layer having indium between the electron blocking layer and the second conductivity type semiconductor layer to prevent current leakage through the threading dislocation TD.

Embodiments can improve the interface quality between the electron blocking layer and the second conductivity type semiconductor layer by disposing a cap layer having indium between the electron blocking layer and the second conductivity type semiconductor layer.

The embodiment is characterized in that a cap layer having indium is disposed between the electron blocking layer and the second conductivity type semiconductor layer to merge the pits or recesses through the enhancement of the two dimensional growth by the cap layer, ) Can be improved.

The embodiment can improve the carrier injection efficiency.

The embodiment can arrange the undoped layer in the cap layer and the second conductivity type semiconductor layer to prevent the dopant from diffusing and to reduce the defect density on the surface.

Embodiments can improve the electrical and optical reliability of semiconductor devices and semiconductor device packages having the same.

1 is a plan view showing a semiconductor device according to an embodiment.
2 is a view schematically showing the AA side cross section of the semiconductor device of FIG.
3 is an enlarged view of the recess structure of Fig.
4 is another example of the recess structure of Fig.
5 is a diagram showing energy band diagrams of an active layer, an electron blocking layer and a cap layer of the semiconductor device of FIG.
FIG. 6 is a view for explaining a carrier injection path to the second conductive type semiconductor layer of FIG. 3; FIG.
7 is a view showing an example in which electrodes are arranged in the semiconductor device of FIG.
8 is a view showing an example of a vertical chip using the semiconductor device of FIG.
9 is a side sectional view showing a semiconductor device package having the semiconductor element of Fig.
10 is a diagram illustrating a TEM (transmission electron microscopy) image for explaining a first region on a first recess in a semiconductor device according to an embodiment.

The embodiments may be modified in other forms or various embodiments may be combined with each other, and the scope of the present invention is not limited to each embodiment described below.

Although not described in the context of another embodiment, unless otherwise described or contradicted by the description in another embodiment, the description in relation to another embodiment may be understood.

For example, if the features of configuration A are described in a particular embodiment, and the features of configuration B are described in another embodiment, even if the embodiment in which configuration A and configuration B are combined is not explicitly described, It is to be understood that they fall within the scope of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG.

In the description of the embodiment according to the present invention, in the case of being described as being formed "on or under" of each element, the upper (upper) or lower (lower) or under are all such that two elements are in direct contact with each other or one or more other elements are indirectly formed between the two elements. Also, when expressed as "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

The semiconductor device may include various electronic devices such as a light emitting device, a light receiving device, an optical modulator, and a gas sensor. Although the embodiment has been described as an example of a semiconductor device, the present invention is not limited thereto and can be applied to various fields.

FIG. 1 is a plan view showing a semiconductor device according to an embodiment, FIG. 2 is a view schematically showing an AA side cross section of the semiconductor device of FIG. 1, FIG. 3 is an enlarged view of the recess structure of FIG. 2, 4 is another example of the recess structure of FIG. 3, and FIG. 5 is a diagram showing energy band diagrams of the active layer, the electron blocking layer, and the cap layer of the semiconductor device of FIG.

1 to 5, a semiconductor device according to an embodiment includes a first conductive semiconductive layer 40A, an active layer 50, an electron blocking layer 60, a capping layer 70, And a conductive semiconductor layer (80). The semiconductor device includes at least one of a substrate 20 and a buffer layer 30. The first conductive semiconductor layer 40A may be disposed on at least one of the substrate 20 and the buffer layer 30. [ 1, the surface of the semiconductor element, for example, the surface of the second conductivity type semiconductor layer 80, may be exposed as a recess 80A on a recess or pit V inside the light emitting structure layer. These recesses 80A can be partially exposed or removed by filling recesses or pits V created in the light emitting structure layer.

≪ Substrate (20) >

The substrate 20 may be, for example, a translucent, conductive substrate or an insulating substrate. For example, the substrate 20 is a sapphire (Al ₂ O _3), SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, and Ga ₂ O ₃ Or the like. The sapphire is a Hexa-Rhombo R3c symmetric crystal having lattice constants of 13.001 Å and 4.758 Å in the c-axis and a-axis directions, and has C (0001), A (1120) ) Face and the like. In this case, since the C-plane is relatively easy to grow the nitride film and is stable at high temperature, it is mainly used as a substrate for growing a nitride semiconductor.

The substrate 20 may include a thickness in the range of 30 탆 to 500 탆, and the refractive index thereof may be 2.4 or less, for example, 2 or less. The length of the adjacent sides of the substrate 111 may be the same or different, and the length of at least one side may be 0.3 mm x 0.3 mm or more, or may be provided in a size having a large area, for example, 1 mm x 1 mm or more . The substrate 20 may be formed in a polygonal shape such as a rectangular shape or a hexagonal shape when viewed from above, but is not limited thereto.

A plurality of protrusions (not shown) may be formed on the top surface and / or bottom surface of the substrate 20, and each of the plurality of protrusions may include at least one of a hemispherical shape, a polygonal shape, and an elliptical shape, Or in the form of a matrix. The protrusions can improve the light extraction efficiency. The substrate 20 may be removed from the semiconductor device.

The substrate 20 may be loaded into the growth equipment and may be formed in layer or pattern form using compound semiconductors of Group 3-Group 5 or Group 2-Group 6 elements thereon. The growth equipment may be an electron beam evaporator, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporator sputtering, metal organic chemical vapor deposition, etc. may be employed and are not limited to such equipment.

≪ Buffer layer 30 >

The buffer layer 30 is disposed on the substrate 20 and may be formed of one layer or a plurality of layers selectively using group II to VI compound semiconductors. The buffer layer 30 is mainly grown on the growth surface 0001 of the substrate 20, and when a potential is generated by the lattice constant, the potential is mostly propagated in the growth direction.

The buffer layer 30 may be formed of a semiconductor layer using, for example, a Group III-V compound semiconductor such as Al _x In _y Ga _(1-xy) N (0? X? 1, 0? _Y? y < / = 1). The buffer layer 30 may include at least one of materials such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and ZnO.

The buffer layer 30 includes at least one of a lattice constant relaxation layer and an undoped undoped semiconductor layer. The lattice constant moderating layer is a layer for reducing a lattice defect difference from the substrate 20, and the undoped semiconductor layer may be formed of a layer having a lower dopant concentration than the n-type semiconductor layer. Dislocations may be generated in at least one of the lattice constant relaxation layer and the undoped semiconductor layer. In an embodiment, the buffer layer 30 may be removed from the semiconductor device.

In an embodiment, a light emitting structure layer may be disposed on the substrate 10 or the buffer layer 30. The light emitting structure layer includes a first conductive semiconductor layer 40A, an active layer 50, and a second conductive semiconductor layer 80. The light emitting structure layer may include a layer structure from the first conductivity type semiconductor layer 40A to the second conductivity type semiconductor layer 80.

≪ First conductive type semiconductor layer 40A >

The first conductive semiconductor layer 40A includes a semiconductor having a first conductivity type dopant and includes a single layer or a multi-layer structure. The first conductive semiconductor layer 40A may be a semiconductor layer using a Group III-V compound semiconductor such as Al _x In _y Ga _(1-xy) N (0? X? 1, 0? _Y? X + y < / = 1). The buffer layer 30 may include at least one of materials such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and ZnO.

The first conductive semiconductor layer 40A includes a plurality of first recesses V1, and the plurality of first recesses V1 may have a V-shaped cross section or an inclined plane. The top view shape of the plurality of first recesses V1 may be circular or polygonal. The first recess V1 may be defined as a V-shaped recess or pit, but is not limited thereto.

The side surface of the first recess (V1) may have a gradually lower height from the top to the bottom. The width of the first recess V1 may gradually increase toward the upper portion. The width of the first recess (V1) may be gradually narrower toward the bottom. The width direction may be a horizontal direction on the upper surface or the lower surface of the first conductive type semiconductor layer 40A.

2, the first conductive semiconductor layer 40A is formed on the first semiconductor layer 40, the second semiconductor layer 41 on the first semiconductor layer 40, And the third semiconductor layer 450. The first to third semiconductor layers 41, 43, and 45 may include a semiconductor having a dopant of the first conductivity type.

The first semiconductor layer 40 may be disposed between the substrate 20 and the active layer 50. The first semiconductor layer 40 may be disposed between the buffer layer 30 and the second semiconductor layer 41. When at least one or both of the substrate 20 and the buffer layer 30 are removed, the bottom surface or the entire surface of the first semiconductor layer 40 may be exposed, but the present invention is not limited thereto. The generated potential T1 may be transmitted through the first semiconductor layer 40.

The first semiconductor layer 40 may be formed of at least one compound semiconductor of group III-V or II-VII elements. The first semiconductor layer 40 is formed of a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + y? . The first semiconductor layer 40 may include at least one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP and AlGaInP. The first semiconductor layer 40 may be an n-type semiconductor layer doped with an n-type dopant such as Si, Ge, Sn, Se or Te. The first semiconductor layer 40 may be formed as a single layer or a multilayer. When the first semiconductor layer 40 is a multi-layered structure, two different layers or three layers may be alternately repeatedly stacked. For example, at least one of AlGaN / GaN, AlInN / GaN, InGaN / GaN and AlInGaN / InGaN / And may be formed in two to 30 cycles. This first semiconductor layer 40 may comprise a superlattice structure.

As shown in FIGS. 2 and 3, the second semiconductor layer 41 may be disposed on the first semiconductor layer 40. The second semiconductor layer 41 may have a plurality of first recesses V1. The second semiconductor layer 41 may be formed with a plurality of first recesses V1. The first recess V1 is generated as the lower point Vc of the first recess V1 is generated and the width of the first recess V1 is further away from the lower point Vc And may include a gradually expanding structure. The second semiconductor layer 41 may be a recessed or pit-generating layer.

The second semiconductor layer 41 may be formed of at least one compound semiconductor of group III-V or II-VII elements. The second semiconductor layer 41 is formed of a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + y? . The second semiconductor layer 41 may include at least one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP and AlGaInP. The second semiconductor layer 41 may be an n-type semiconductor layer doped with an n-type dopant such as Si, Ge, Sn, Se or Te. The second semiconductor layer 41 may be a single layer or a multilayer. In the case where the second semiconductor layer 41 is a multi-layered structure, two different layers or three layers may be alternately repeatedly stacked, and at least one of AlGaN / GaN, AlInN / GaN, InGaN / GaN and AlInGaN / InGaN / And may be formed in two to 30 cycles. The second semiconductor layer 41 may include a superlattice structure.

At least one of the plurality of first recesses V1 may be connected to one or a plurality of potentials T1. That is, the first recess V1 may be generated on the region where the potential T1 is exposed. Each of the first recesses (V1) has a letter V-shaped cross-section and may have a hexagonal or circular planar shape. The first recess V1 disposed in the second semiconductor layer 41 may be formed to extend from the potential T1, and the width may gradually increase as it goes up. The width of the first recesses V1 becomes larger as the thickness of the second semiconductor layer 41 increases. The inclined face or the crystal face of the first recess (V1) may have a range of 35 degrees to 60 degrees with respect to a horizontal axis.

The third semiconductor layer 45 may be formed of at least one compound semiconductor of group III-V or II-VI elements. The third semiconductor layer 45 is formed of a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + . The third semiconductor layer 45 may include at least one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP and AlGaInP. The third semiconductor layer 45 may be an n-type semiconductor layer doped with an n-type dopant such as Si, Ge, Sn, Se or Te. The third semiconductor layer 45 may have a multi-layer structure. For example, two or three layers, which are different from each other, may be alternately repeated. The materials of the compound semiconductor may be different from those of the different layers, and the materials of the two compound semiconductor layers may be the same, but the composition of the dopant and the composition of aluminum or indium may be different. At least one of AlGaN / AlGaN, GaN / GaN, AlGaN / GaN, AlInN / GaN, AlGaN / InGaN, InGaN / GaN and AlInGaN / InGaN / GaN is formed on the third semiconductor layer 45, And may be formed in two to 30 cycles. The third semiconductor layer 45 may hold the first recess V1 or widen the width of the first recess V1. The third semiconductor layer 45 may function to block a potential that is propagated through regions other than the region where the first recesses V1 propagate.

The third semiconductor layer 45 may extend through the first recess V1 and may have a first hole 45A in the region of the first recess V1. The first hole 45A may have a narrower bottom width and a wider top width. The first hole 45A may have a polygonal top shape, for example, a hexagonal top shape or a circular top shape. The third semiconductor layer 45 may be removed.

<Active layer 50>

The active layer 50 may be disposed between the first semiconductor layer 40 and the electron blocking layer 60. The active layer 50 may be disposed between the third semiconductor layer 45 and the electron blocking layer 60. The active layer 50 may be in contact with at least one or both of the third semiconductor layer 45 and the electron blocking layer 60.

The active layer 50 may optionally include a single quantum well, a multiple quantum well (MQW), a quantum wire structure, or a quantum dot structure. As shown in FIG. 5, the active layer 50 may include a period of the well layer 51 and a period of the barrier layer 52. The well layer 51 comprises a composition formula of _{In x Al y Ga 1 -x- y} N (0≤≤x≤≤1, 0≤≤y≤≤1, 0≤≤x + y≤≤1) the barrier layer 52 comprises a composition formula of _{in x Al y Ga 1 -x- y} N (0≤≤x≤≤1, 0≤≤y≤≤1, 0≤≤x + y≤≤1) can do. The period of the well layer / barrier layer 51/52 is set to 2 占 퐉 by using a laminated structure of InGaN / GaN, GaN / AlGaN, InGaN / AlGaN, InAlGaN / AlGaN, InGaN / InGaN, InGaN / InAlGaN and GaN / InAlGaN. For example, 3 cycles to 30 cycles. As shown in FIG. 5, the band gap G2 of the barrier layer 52 may be formed of a semiconductor material having a band gap wider than the band gap G1 of the well layer 51. FIG. The band gap G2 of the barrier layer 52 may be the same or at least one band gap may be different. The band gap G1 of the well layer 51 may be the same or at least one band gap may be different. The embodiment may further include a lower electron blocking layer 60 between the active layer 50 and the third semiconductor layer 45 for blocking electrons, but the present invention is not limited thereto. The thickness of the well layer 51 may be thinner than the thickness of the barrier layer 52, but is not limited thereto.

The active layer 50 may be formed as an extended region 50A extending to the side of the first recess V1 or may be formed as a hole not extending to the side of the first recess V1. The recess in the extended region 50A may be larger than the width of the first hole 45A formed in the second semiconductor layer 41. [ The recess width of the extended region 50A may gradually increase as the distance increases. The extension region 50A may overlap the region of the first recess V1 in the vertical direction. The recessed shape of the extended region 50A includes a polygonal shape, for example, a hexagonal shape as viewed from above. The side surface of the extended region 60A may be formed as an inclined surface and may extend on the inclined surface of the first recess V1.

The active layer 50 may control the growth mode of the growth of the well layer 51 and the barrier layer 52 so that the extension layer 50A extending on the side of the first recess V1, A part of the barrier layer 51 and the barrier layer 52 may be formed to have a small thickness or may be formed in a hole shape other than the extended region 50A and this configuration may vary depending on the horizontal growth and / .

At least one of the first recesses V1 in the active layer 50 may have an upper width D2 of 250 nm or less, for example, 220 nm to 240 nm. If the upper width D2 of the first recess V1 in the active layer 50 is out of the above range, the leakage current may be increased. The depth H1 of the first recess V1 is a vertical height from the top surface to the bottom point Vc of the active layer 50. The depth H1 of the first recess V1 is a vertical height from the top surface of the active layer 50 to the bottom point Vc, May be larger than the sum, but is not limited thereto.

&Lt; Electron barrier layer 60 >

The electron blocking layer 60 is disposed on the active layer 50 to block electrons traveling through the active layer 50. The electron blocking layer 60 may be formed of any one of compound semiconductors such as GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN doped with a dopant of the second conductivity type. Of the electron blocking layer 60, 60 is, for example _{In x Al y Ga 1 -x- y} N (0≤≤x≤≤1, 0 <y≤≤1, 0 <x + y≤≤1) the composition formula And a p-type semiconductor layer having a semiconductor having a p-type semiconductor layer. The electron blocking layer 60 may be formed of an AlN semiconductor having a band gap G4 wider than the barrier layer 52 of the active layer 50 as shown in FIG. The AlN-based semiconductor may include at least one of AlN, AlGaN, InAlGaN, and AlInN-based semiconductors. The second conductivity type dopant of the electron blocking layer 60 may be a p-type dopant including Mg, Zn, Ca, Sr, and Ba.

The electron blocking layer 60 can suppress propagation of the first recesses V1. When the first recesses (V) are exposed to the surface of the semiconductor element, ESD may be affected. Accordingly, the electron blocking layer 60 may be formed in a horizontal growth mode in which the first recesses V are removed. A part of the first recess (V1) may be propagated in the electron blocking layer 60, but the present invention is not limited thereto.

The electron blocking layer 60 may be formed as a single layer or a multilayer. When the electron blocking layer 60 has a multilayer structure, the superlattice structure may include a superlattice structure of AlGaN / AlGaN or a superlattice structure of AlGaN / GaN. The superlattice structure of the electron blocking layer 60 may protect the active layer 50 by diffusing a current contained in the voltage abnormally.

As shown in FIG. 2, when the electron blocking layer 60 is multi-layered, it may include at least three layers, for example, at least two of the at least three layers may have different compositions of aluminum. The electron blocking layer 60 may include a laminate structure of the first to sixth layers 61, 62, 63, 64, 65 and 66, and the first to sixth layers 61, 62, 63, 64, 65, and 66 may be formed of an AlGaN-based semiconductor. The first layer 61 is disposed on the last barrier layer of the active layer 50 and the second layer 62 is disposed between the first layer 61 and the second layer 62, The layer 63 is disposed between the second layer 62 and the fourth layer 64 and the fourth layer 64 is disposed between the third layer 63 and the fifth layer 65, The fifth layer 65 may be disposed between the fourth layer 64 and the sixth layer 66 and the sixth layer 66 may be disposed between the fifth layer and the cap layer 70.

The aluminum composition of the first to sixth layers 61, 62, 63, 64, 65, and 66 may be higher than the aluminum composition of the barrier layer 52 of the active layer 50. The aluminum composition of the first, third, and fifth layers (61, 63, 65) may be higher than the aluminum composition of the second, fourth, sixth layers (62, 64, 66). The first layer (61) may be lower than the aluminum composition of the third and fourth layers (63, 65). The aluminum composition of the third layer 63 may be higher than that of the first, second and fourth to sixth layers 61, 62, 64, 65 and 66. The third layer 63 is in a range of 1.2 times or more, for example, 1.3 to 1.7 times as much as the composition of aluminum in the first layer 61, , And may range from 2.2 times to 2.8 times. The fifth layer 65 may be higher than the aluminum composition of the first layer 61 and lower than the aluminum composition of the third layer 63 and may have a composition difference of aluminum with respect to the first layer 61 (Difference 2) between the first layer 63 and the first layer 63 may be the same or the difference 2> the difference 1. The composition of aluminum in the first, third and fifth layers (61, 63, 65) is in the range of more than 10%, for example, 11% to 30% The composition of aluminum may be in the range of 10% or less, for example, 10% to 6%. The aluminum compositions of the second, fourth, and sixth layers (62, 64, 66) may be the same. The thickness of each of the first to sixth layers 61, 62, 63, 64, 65, and 66 may be in the range of 3 nm to 6 nm. The thickness of the electron blocking layer 60 may be less than 30 nm, for example, in the range of 24 nm to 26 nm.

The electron blocking layer 60 has a multi-layered AlGaN-based semiconductor laminated structure and blocks electrons from blocking the extension of the first recesses V1. The electron blocking layer 60 has a first extending portion 60A extending on the first recess V1 and the first extending portion 60A is formed on the surface of the first recess V1 The second recess V2 may be formed. The thickness T2 of the first extended portion 60A may be 25 nm or less in the oblique direction on the surface of the first recess V1. The first extended portion 60A may be in contact with the extended region 50A of the active layer 50 or when the extended region of the active layer 50 is formed as a hole, 41, 45).

The bottom portion of the first extending portion 60A forms a second recess V2 having the same shape as that of the first recess V1. The side inclination angle of the second recess V2 may be the same as the inclination angle of the first recess V1 in the active layer 50. The upper width D1 of the second recess V2 may be smaller than the upper width D2 of the first recess V1.

&Lt; Cap layer (70) >

The cap layer 70 may be disposed between the electron blocking layer 60 and the second conductive semiconductor layer 80. The cap layer 70 may be in contact with the electron blocking layer 60 and the second conductivity type semiconductor layer 80. The cap layer 70 may be in contact with the lower surface of the sixth layer 66 of the electron blocking layer 60 and the lower surface of the second conductivity type semiconductor layer 80.

The cap layer 70 may be formed of a semiconductor layer having indium. The cap layer 70 may be formed of a semiconductor layer having indium and aluminum. The cap layer 70 may be formed of a semiconductor having a composition formula of In _x Al _y Ga _1-xy N (0 < _{x? 1} , 0 < _{y? 1} , 0 <x + y? . The composition of indium (In) in the cap layer 70 may be 5% or less and 2 to 4%. The composition of the aluminum (Al) may be in the range of 13% or less, for example, 10% to 13%. The indium composition of the cap layer 70 may be less than the composition of aluminum. The aluminum composition of the cap layer 70 is larger than the aluminum composition of the second, fourth, and sixth layers 62, 64, and 66 of the electron blocking layer 60, Lt; / RTI &gt; composition of aluminum. The band gap G7 of the cap layer 70 is wider than the bandgaps G3, G5 and G6 of the second, fourth and sixth layers 62, 64 and 66, 63 and 65, respectively. Here, the band gap can have a relationship of G4 < G3 < G7 < G6 &lt; G5.

The thickness of the cap layer 70 may be in the range of 7 nm or less, for example, 4 nm to 6 nm, and if it is within the range, the interface quality between the electron blocking layer 60 and the second conductivity type semiconductor layer 80 may be improved have. In addition, the cap layer 70 can be grown to have a two-dimensional structure with indium. As a result, the two-dimensional growth is enhanced in the region between the electron blocking layer 60 and the second conductivity type semiconductor layer 80 on the first recess V1, Can be buried and merge. Here, merge may include growth with a thickness greater than the thickness of the cap layer 70 in the region of the first recess Vl. When the active layer 50 is grown at a temperature of 900 ° C or lower, the cap layer 60 may be grown at a temperature of 50 ° C or higher, for example, 50 ° C to 200 ° C, higher than the temperature of the active layer 50.

The cap layer 70 may include a first region 70A that overlaps the first recess V1 in the vertical direction. The first region 70A may extend to the side of the first recess V1 in the light emitting structure layer. The first region 70A may extend to the side of the first recess V1 of the first conductive semiconductor layer 40A. The first region 70A may be disposed on the first recess V1 of the first conductive type semiconductor layer 40A and / or on the first extended portion 60A of the electron blocking layer 60 , And a second extension portion. The first region 70A may be increased in thickness from the upper side to the lower side in the first recess V1. The thickness of the first region 70A may gradually increase from the lower side of the first recess V1 to the center of the first recess V1.

Since the cap layer 70 has indium, the electron blocking layer 60 and the second conductivity type semiconductor layer 80 are grown on the second recess V2 of the electron blocking layer 60 through two- As a surfactant. The first region 70A of the cap layer 70 may be merged with the first recess V1 to improve the ESD.

The cap layer 70 may be formed of an undoped semiconductor layer. The undoped semiconductor layer may have a lower conductivity than the conductivity of the layer having the second conductive dopant. The cap layer 70 may be formed of, for example, unintentional doped InAlGaN, and the composition of the indium may be in the range of 2% to 4%, and the composition of the aluminum may be in the range of 13% Lt; / RTI &gt; The cap layer 70 may serve as a cap for preventing diffusion of a dopant into the second conductive semiconductor layer 80 and transmission of the dopant to the active layer 50.

The first region 70A of the cap layer 70 may overlap the extended region 50A of the active layer 50 or may not overlap the active layer 50 when the active layer 50 is formed alone. The thickness of the first region 70A may be increased from the upper region having the predetermined width D4 toward the lower region 75 or the center region. The thickness T4 of the upper region in the first region 70A may be smaller than the thickness of the lower region 75 and the maximum thickness H2 or the maximum height of the lower region 75 is greater than the thickness T4 . H2 may be at least two times T3. The height of the upper surface of the lower region 75 may be lower than the height of the upper surface of the active layer 50 and may be equal to or lower than the height of the lower surface of the active layer 50, for example. The lower region 75 may be thicker from the upper side of the side surface of the first recess V1 to the lower side or the lower center thereof, for example, may gradually become thicker. The upper surface of the lower region 75 may be a flat or concave curved surface.

The center region corresponding to the bottom point 76 of the second recess V2 in the first region 70A may be the thickest. A third recess V3 in the first region 70A is disposed on the second recess V2 and a horizontal width D3 of the lower region 75 is disposed on the second recess V2. V2 may be less than the upper width D1 of the upper portion.

The bottom region 75 of the first region 70A of the cap layer 70 corresponds to the bottom point Vc of the first and second recesses V1 and V2 and the thickness H2 of the first region 70A, Lt; / RTI &gt; The lower region 75 of the first region 70A may have a height or a thickness H2 greater than the thickness T3 of the inclined region of the first region 70A. The height H3 from the upper surface of the lower region 75 of the first region 70A to the upper surface of the cap layer 70 may be equal to or less than H2.

The first region 70A is provided on the first recess V1 with a thickness H2 which is thicker than the other region and is provided with the undoped semiconductor, so that carrier injection into the threading dislocation T1 can be suppressed. The cap layer 70 is an undoped semiconductor layer and the lower region 75 of the first region 70A is thickened so that the potential T1 across the low point Vc of the first recess V1 The height of the barrier can be increased. The width D3 of the lower region 75 may range from 20% to 70% of the width D1 of the upper region. The barrier height with respect to the lower region 75 of the first region 70A can be increased by the width D3. The first region 70A has a concave third recess V3 and the side face of the third recess V3 may have an inclined face. The inclination angle of the inclined face of the third recess V3 is May be greater than an inclination angle of the first recess (V1).

The height of the upper surface of the lower region 75 corresponding to the trough 76 in the first region 70A may be lower than the upper surface or the lower surface of the active layer 50. [ The height of the upper surface of the lower region 75 corresponding to the lower point 76 in the first region 70A may be lower than the upper surface of the third semiconductor layer 45 or the upper surface of the second semiconductor layer 41 . The thickness T3 of the lower region 75 of the first region 70A is thickened in the lower region 75 so that carriers are prevented from being injected into the threading dislocation T1 and leaked. 10 is a TEM image of a semiconductor device according to the embodiment, in which the lower region of the first region 70A of the cap layer 70 on the first recess V1 of the first conductivity type semiconductor layer 40A has a thick thickness And is disposed lower than the lower surface of the active layer 50.

Here, the thicknesses of the respective layers in the regions overlapping with the active layer 50 in the vertical direction are compared as follows. Wherein the thickness of the electron blocking layer 60 is a, the thickness of the cap layer 70 is b, the thickness of the second conductivity type semiconductor layer 80 is c and the thickness of the electron blocking layer 60 and the cap layer 70 ) Is d, the following relationship can be obtained.

The ratio (a: b) of the thickness a of the electron blocking layer 60 to the thickness b of the cap layer 70 may range from 4.5: 1 to 5.5: 1. The thickness of the second conductive semiconductor layer 80 and the thickness ratio c: b of the cap layer 70 may be in a range of 11: 1 to 14: 1. The thickness d of the electron blocking layer 60 and the cap layer 70 may be less than the thickness c of the second conductive semiconductor layer 80. The sum of the thicknesses of the electron blocking layer 60 and the cap layer 70 is d and the thickness of the second conductivity type semiconductor layer 80 is c, : 1.8 to 1: 2.3. When the thickness of the cap layer 70 is smaller than the above range, the thickness of the merged portion in the lower region 75 of the first region 70A may become thinner and the current leakage above the penetration hole may not be blocked. The thickness from the cap layer 70 to the second conductivity type semiconductor layer 80 increases, and the current injection efficiency may be lowered.

&Lt; Second conductive type semiconductor layer 80 >

The second conductive semiconductor layer 80 may be formed of at least one compound semiconductor of Group III-V or Group II-VII elements. The second conductivity type semiconductor layer 80 is formed of a semiconductor material having a composition formula of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + y? . The second conductive semiconductor layer 80 may include at least one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP and AlGaInP. The second conductive semiconductor layer 80 may be a p-type semiconductor layer having a p-type dopant such as Mg, Zn, Ca, Sr, or Ba. The second conductive semiconductor layer 80 may be a single layer or a multilayer.

When the second conductive semiconductor layer 80 is a multi-layered structure, at least one layer may include a layer doped with a p-type dopant. The second conductive semiconductor layer 80 may include, for example, a layer having a p-type dopant and a layer having an undoped p-type dopant. The second conductive semiconductor layer 80 may be formed of a GaN-based semiconductor in multiple layers. Wherein the second conductive semiconductor layer includes first to fourth nitride layers 81, 82, 83, and 84, the first nitride layer 81 is disposed on the cap layer 70, 2 nitride layer 82 is disposed between the first and third nitride layers 82,83 and 84 and the third nitride layer 83 is between the second and fourth nitride layers 82,84 And the fourth nitride layer 84 may be disposed between the third nitride layer 83 and the electrode layer (90 in FIG. 7). The dopant concentration of the first and third nitride layers 81 and 83 may be lower than the dopant concentration of the second and fourth nitride layers 82 and 84. The fourth nitride layer 84 may be higher than the dopant concentration of the second nitride layer 82. Since the fourth nitride layer 84 is disposed higher than the dopant concentration of the second nitride layer 82, carriers can be effectively implanted. Since the first and third nitride layers 81 and 83 are disposed as low-doped or undoped layers, the dopant doped in the second and fourth nitride layers 82 and 84 can be diffused, It is possible to prevent deterioration of the crystal quality of the semiconductor device.

Wherein the thickness of the first nitride layer 81 is z1, the thickness of the second nitride layer 82 is z2, the thickness of the third nitride layer 83 is z3, Z3> z2> z4> z1, and the relationship z1 + z2 + z4 = z3 can be obtained. The ratio of z1: z2 may be 1: 2.7 to 1: 3.2, and the ratio of z1: z4 may be 1: 1.7 to 1: 2.2.

The sum of the thicknesses of the first to fourth nitride layers 81, 82, 83, and 84 may be 70 nm or less, for example, 55 nm to 70 nm. And if it is smaller than the above range, it is difficult to fill the first recess (V1). The first and third nitride layers 81 and 83 may enhance the ESD by merging the region of the first recess V1.

The second conductive semiconductor layer 80 may have a protruding portion 85 protruding in a region corresponding to the first recess V1 and the protruding portion 85 may fill the first recess V1. have. The protrusions 85 are disposed on the first region 70A of the cap layer 70 and fill the third recesses V3 so that the recesses 85 appearing on the surface of the second conductivity type semiconductor layer 80 The depth of the concave portion 80A corresponding to the concave portion 80A can be reduced. A recess 80A may be formed on a surface of the second conductive semiconductor layer 80 in a region corresponding to the first recess V1. The depth of the concave portion 80A is not more than 10 nm, for example, not more than 5 nm, and may be in a range not affecting crystal defects.

The semiconductor device can have a plurality of first recesses (V1) therein, and the density of the threading dislocations is lowered to 1E8 / cm2 or less to provide a high-quality template, reduce the operating voltage, Can be improved.

In the embodiment, the layers from the first semiconductor layer 40 to the second conductivity type semiconductor layer 80 may be defined as a light emitting structure layer. Although the first semiconductor layer 40 is an n-type semiconductor layer and the second conductive semiconductor layer 80 is a p-type semiconductor layer, the light emitting structure layer is not limited to this, the p-type semiconductor layer, and the second conductivity type semiconductor layer 80 may be an n-type semiconductor layer. In addition, the light emitting structure layer may be formed with a semiconductor (e.g., an n-type semiconductor layer) (not shown) having a polarity opposite to the second conductivity type on the second conductive semiconductor layer 80. Accordingly, the semiconductor device of the embodiment can be implemented by any one of an n-p junction structure, a p-n junction structure, an n-p-n junction structure, and a p-n-p junction structure. Other layers may be disposed above or below the layers in the light emitting structure layer of the embodiment, but the present invention is not limited thereto.

In the embodiment, a cap layer 70 having indium is disposed between the electron blocking layer 60 and the second conductivity type semiconductor layer 80, and the first region 70A of the cap layer 70 is provided with the first The barrier height at the interface of the first recess V1 can be increased and the carrier can be injected through the threaded potential in the center region of the first recess V1 since the recess V1 is filled in the center region, Can be suppressed. The carrier E2 injected into the first region 70A of the cap layer 70 among the carriers E1 and E2 injected through the second conductivity type semiconductor layer 80 is injected into the lower region 75, So that the carrier injection efficiency into the active layer 50 can be improved.

The cap layer 70 having indium is disposed between the electron blocking layer 60 and the second conductivity type semiconductor layer 80 to form the electron blocking layer 60 and the second conductivity type semiconductor layer 80, Can be improved. Also, since the cap layer 70 covers the first recesses V1, the thicknesses of the electron blocking layer 60 and the second conductivity type semiconductor layer 80 can be reduced. Accordingly, the first recesses V1 are filled with the second conductivity type semiconductor layers 80 and 80 by 90% or more, so that the carrier injection efficiency between the second conductivity type semiconductor layer 80 and the electrode layers Can be improved.

In the embodiment, since the cap layer 70 disposed between the electron blocking layer 60 and the second conductivity type semiconductor layer 80 has indium and is formed in a two-dimensional structure on the first recess V1, And ESD can be improved by merging on the first recess V1.

Since the cap layer 70 having indium between the electron blocking layer 60 and the second conductivity type semiconductor layer 80 is disposed in an undoped layer, the cap layer 70 is diffused in the second conductivity type semiconductor layer 80 And can prevent the dopant from propagating to the active layer 50.

In the embodiment, the undoped first and third nitride layers 81 and 83 are disposed at different positions on the second conductivity type semiconductor layer 80 to improve current diffusion, Can be improved. The interface quality between the first and third nitride layers 81 and 82 and the interface quality between the third and fourth nitride layers 83 and 84 can be improved. By providing the thickness of the second conductivity type semiconductor layer 80 to 70 nm or less, the optical output can be improved by providing it as an optical cavity. The embodiment can enhance the ESD by merging the first pit V1 with the first and third nitride layers 81 and 83 in the second conductivity type semiconductor layer 80. [

4 shows another example of the first region of the cap layer of FIG. 3, wherein the first region 70A of the cap layer 70 has a gradually lower height as it approaches the center Vc of the first recess V1, It can become thicker gradually. This is because the side inclination angle of the third recess V3 of the first region 70A may be larger than the side inclination angle of the first recess V1. This may vary depending on the thickness of the cap layer 70 and the side inclination angle of the third recess V3 in the first region 70A. The lower region 75 may become thicker toward the center in the upper region, for example, the region lower than the upper surface or the lower surface of the active layer 50, and may become thicker, for example, gradually. The upper surface of the lower region 75 may be inclined with respect to the center, or may have a concave curved surface.

3 and 4, the lower region 75 of the first region 70A of the cap layer 70 may have a symmetrical shape with respect to the thickest center.

7 is a view showing a horizontal type device in which electrodes are disposed in the semiconductor device of FIG. The horizontal type device may be connected by one or a plurality of wires and may be arranged in a flip chip type.

Referring to FIG. 7, the semiconductor device 101 has the same reference numerals as those shown in FIGS. 1 to 6, and the technical features of FIGS. 1 to 6 can be employed.

As shown in FIGS. 1 and 7, the semiconductor device 101 may include a first electrode 191 and a second electrode 195. The first electrode 191 may be electrically connected to the first semiconductor layer 40. The second electrode 195 may be electrically connected to the second conductive semiconductor layer 80. The first electrode 191 may be disposed on the first semiconductor layer 40 and the second electrode 195 may be disposed on the second conductive semiconductor layer 80.

The first electrode 191 and the second electrode 195 may have a current diffusion pattern of an arm structure or a finger structure. The first electrode 191 and the second electrode 195 may be made of a metal having properties of an ohmic contact, an adhesive layer, and a bonding layer, and may not be transparent. The first electrode 193 and the second electrode 195 may be formed of a material selected from the group consisting of Ti, Ru, Rh, Ir, Mg, Zn, Al, In, Ta, Pd, Co, Ni, Si, Alloys.

An electrode layer 90 having an ohmic function may be disposed between the second electrode 195 and the second conductive semiconductor layer 80. The electrode layer 90 may include at least one conductive material. The electrode layer 90 may be a single layer or multiple layers. The electrode layer 90 may include at least one of a metal, a metal oxide, and a metal nitride material. The electrode layer 90 may include a light-transmitting material. For example, the electrode layer 90 may be formed of one selected from the group consisting of ITO (indium tin oxide), IZO (indium zinc oxide), IZON (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), IGZO ), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), IrOx, RuOx, RuOx / ITO, Ni / IrOx / / ITO, Pt, Ni, Au, Rh, or Pd. The electrode layer 90 may have a thickness of 5 nm or less on the second conductivity type semiconductor layer 80 to improve current injection efficiency into the second conductivity type semiconductor layer 80.

An insulating layer 180 may be disposed on the electrode layer 90. The insulating layer 180 may be in contact with the electrode layer 80 and the first and second electrodes 191 and 195. The insulating layer 180 may include an oxide having at least one of Al, Cr, Si, Ti, Zn, , An insulating material formed of at least one of nitride, fluoride, and sulfide, or an insulating resin. The insulating layer 180 may be selectively formed, for example, of SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , and TiO ₂ . The insulating layer 180 may be formed as a single layer or a multilayer, but is not limited thereto.

8 is a view showing a vertical type device in which electrodes are disposed in the semiconductor device of FIG. The elements of Fig. 8 are denoted by the same reference numerals as those of the elements shown in Figs. 1 to 6, and the technical features of Figs. 1 to 6 can be employed.

As shown in FIG. 8, the semiconductor device 102 may include a first electrode 191 electrically connected to the first semiconductor layer 40. The first electrode 191 may be disposed on the upper surface of the first semiconductor layer 40. The second electrode 160 may be disposed under the second conductive semiconductor layer 40.

The substrate 20 and buffer layer 30 of Figure 1 may be removed by physical and / or chemical means. The method of removing the substrate 20 can be removed by physical methods (e.g., laser lift off) and / or chemical methods (such as wet etching). Can be removed by performing isolation etching through the direction in which the substrate 20 is removed. The upper surface of the first semiconductor layer 40 may be formed as a rough surface, or an insulating layer may be disposed.

The first electrodes 191 may be disposed in different regions, and may have an arm pattern or a bridge pattern. However, the present invention is not limited thereto. A portion of the first electrode 191 may be used as a pad to which a wire (not shown) is bonded.

The second electrode 160 may include a plurality of conductive layers, for example, a contact layer 165, a reflective layer 167, a bonding layer 169, and a conductive support member 183. The contact layer 165 may be a low conductive material such as ITO, IZO, IZTO, IAZO, IGZO, IGTO, AZO, or ATO or a metal such as Ni or Ag. A reflective layer 167 is formed under the contact layer 165 and the reflective layer 167 is formed of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, And at least one layer made of a material selected from the group. A part of the reflective layer 167 may be in contact with the second conductive semiconductor layer 80 and may be in ohmic contact with a metal or ohmic contact with a conductive material such as ITO.

A bonding layer 169 is formed under the reflection layer 167 and the bonding layer 169 may be used as a barrier metal or a bonding metal. The material may be Ti, Au, Sn, Ni, Cr, Ga, In, Bi, Cu, Ag, and Ta and an optional alloy.

A conductive support member 173 is formed under the bonding layer 169. The conductive support member 173 may be a metal or a carrier substrate and may be made of a metal such as copper-copper, gold- (Ni-nickel), molybdenum (Mo), copper-tungsten (Cu-W), and carrier wafers (e.g., Si, Ge, GaAs, ZnO, SiC and the like). As another example, the conductive supporting member 173 may be embodied as a conductive sheet.

Fig. 9 is a view showing a package having the semiconductor element of Fig. 7 or Fig. 8;

9, the semiconductor device package includes a body 311 having a cavity 315, a first lead frame 321 and a second lead frame 323 disposed in the body 311, a light emitting element 101, wires 331, and a molding member 341.

The body 311 may include a conductive or insulating material. The body 311 may include at least one of a resin material such as polyphthalamide (PPA), a silicon (Si), a metal material, a photo sensitive glass (PSG), a sapphire (Al ₂ O ₃ ), a printed circuit board Can be formed. The body 311 may include a resin material such as polyphthalamide (PPA) or epoxy.

The body 311 has a cavity 315 having an open top and a side and a bottom. The cavity 315 may include a concave cup structure or a recessed structure from the upper surface of the body 311, but the present invention is not limited thereto.

The first lead frame 321 is disposed in a first region of a bottom region of the cavity 315 and the second lead frame 323 is disposed in a second region of a bottom region of the cavity 315. The first lead frame 321 and the second lead frame 323 may be spaced apart from each other in the cavity 315.

The first and second lead frames 321 and 323 may be formed of a metal material such as titanium (Ti), copper (Cu), nickel (Ni), gold (Au), chromium (Cr), tantalum ), Platinum (Pt), tin (Sn), silver (Ag), and phosphorus (P) and may be formed of a single metal layer or a multilayer metal layer.

The light emitting device 101 may be disposed on at least one of the first and second lead frames 321 and 223 and may be disposed on the first lead frame 321 and the first and second lead frames 321 and 223, And is connected to the second lead frames 321 and 223.

The light emitting device 101 can selectively emit light in a visible light band to an ultraviolet light band. For example, the light emitting device 101 can be selected from a red LED chip, a blue LED chip, a green LED chip, and a yellow green LED chip. The light emitting chips 101 and 102 may include Group III-V or Group II-VI compound semiconductors. The light emitting devices 101 and 102 may employ the technical features of FIGS.

A molding member 341 is disposed in the cavity 315 of the body 311 and the molding member 341 includes a light transmitting resin layer such as silicon or epoxy and may be formed as a single layer or a multilayer. The phosphor may include a phosphor for changing the wavelength of emitted light on the molding member 341 or the light emitting devices 101 and 102. The phosphor may partially excite light emitted from the light emitting devices 101 and 102, And emits light of a different wavelength. The phosphor may be selectively formed from YAG, TAG, Silicate, Nitride, and Oxy-nitride based materials. The phosphor may include at least one of a red phosphor, a yellow phosphor, and a green phosphor, but the present invention is not limited thereto. The surface of the molding member 341 may be formed in a flat shape, a concave shape, a convex shape, or the like, but is not limited thereto.

A lens may be further formed on the body 311. The lens may include a concave or convex lens structure and light distribution of light emitted by the light emitting devices 101 and 102 may be formed. Can be adjusted.

A protective element may be disposed in the light emitting device package. The protection device may be realized with a thyristor, a zener diode, or a TVS (Transient Voltage Suppression).

The semiconductor device can prevent an increase in operation voltage that can occur in a high-quality template having a dislocation defect (TD) density of 1E8 / cm 2 or less. Further, the semiconductor device of the embodiment can improve the carrier injection efficiency.

The light emitting device package described above can be used as a light source of an illumination system. The light emitting device package can be used as a light source of a video display device or a lighting device, for example.

When used as a backlight unit of a video display device, it can be used as an edge type backlight unit or as a direct-type backlight unit. When used as a light source of a lighting device, it can be used as a regulator or a bulb type. It is possible.

The light emitting element includes a laser diode in addition to the light emitting diode described above.

The laser diode may include the first conductivity type semiconductor layer, the active layer and the second conductivity type semiconductor layer having the above-described structure, like the light emitting element. Then, electro-luminescence (electroluminescence) phenomenon in which light is emitted when an electric current is applied after bonding the p-type first conductivity type semiconductor and the n-type second conductivity type semiconductor is used, And phase. That is, the laser diode can emit light having one specific wavelength (monochromatic beam) with the same phase and in the same direction by using a phenomenon called stimulated emission and a constructive interference phenomenon. It can be used for optical communication, medical equipment and semiconductor processing equipment.

As the light receiving element, a photodetector, which is a kind of transducer that detects light and converts the intensity of the light into an electric signal, is exemplified. As such a photodetector, a photodiode (e.g., a PD with a peak wavelength in a visible blind spectral region or a true blind spectral region), a photodiode (e.g., a photodiode such as a photodiode (silicon, selenium), a photoconductive element (cadmium sulfide, cadmium selenide) , Photomultiplier tube, phototube (vacuum, gas-filled), IR (Infra-Red) detector, and the like.

In addition, a semiconductor device such as a photodetector may be fabricated using a direct bandgap semiconductor, which is generally excellent in photo-conversion efficiency. Alternatively, the photodetector has a variety of structures, and the most general structure includes a pinned photodetector using a pn junction, a Schottky photodetector using a Schottky junction, and a metal-semiconductor metal (MSM) photodetector have.

The photodiode, like the light emitting device, may include the first conductivity type semiconductor layer having the structure described above, the active layer, and the second conductivity type semiconductor layer, and may have a pn junction or a pin structure. The photodiode operates by applying reverse bias or zero bias. When light is incident on the photodiode, electrons and holes are generated and a current flows. At this time, the magnitude of the current may be approximately proportional to the intensity of the light incident on the photodiode.

A photovoltaic cell or a solar cell is a type of photodiode that can convert light into current. The solar cell, like the light emitting device, may include the first conductivity type semiconductor layer, the active layer and the second conductivity type semiconductor layer having the above-described structure.

In addition, it can be used as a rectifier of an electronic circuit through a rectifying characteristic of a general diode using a p-n junction, and can be applied to an oscillation circuit or the like by being applied to a microwave circuit.

In addition, the above-described semiconductor element is not necessarily implemented as a semiconductor, and may further include a metal material as the case may be. For example, a semiconductor device such as a light receiving element may be implemented using at least one of Ag, Al, Au, In, Ga, N, Zn, Se, P, or As, Or may be implemented using a doped semiconductor material or an intrinsic semiconductor material. While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

20: substrate
30: buffer layer
40A: a first conductivity type semiconductor layer
40: first semiconductor layer
41: second semiconductor layer
45: Third semiconductor layer
50:
60: electron blocking layer
60A: first extension portion
70: cap layer
70A: first region
80: second conductive type semiconductor layer
81, 82, 83, 84:

Claims (16)

A first conductive semiconductor layer having a plurality of first recesses;
An active layer disposed on the first conductive semiconductor layer;
A second conductive semiconductor layer disposed on the active layer; And
And a cap layer disposed on the active layer and the second conductive type semiconductor layer,
Wherein the cap layer comprises a first region disposed on a side of the first recess,
Wherein the first region includes a lower region that is thicker in a lower side portion of the first recess than a side portion of the first recess. 2. The device of claim 1, wherein the active layer comprises an extended region extending laterally of the first recess,
Wherein the extension region is disposed between a side of the first recess and a first region of the cap layer. The semiconductor device according to claim 2, further comprising an electron blocking layer disposed between the cap layer and the active layer. 4. The semiconductor device of claim 3, wherein the electron blocking layer comprises a first extension disposed between the extended region of the active layer and the first region of the cap layer on the first recess. 5. The semiconductor device according to any one of claims 1 to 4, wherein the cap layer comprises a semiconductor having indium and aluminum. 6. The semiconductor device according to claim 5, wherein the cap layer has a dopant concentration lower than that of the second conductivity type dopant added to the second conductivity type semiconductor layer or includes an undoped semiconductor. The semiconductor device according to claim 5, wherein the cap layer has a thickness smaller than the thickness of the electron blocking layer or the thickness of the second conductivity type semiconductor layer. 6. The semiconductor device according to claim 5, wherein the first region of the cap layer is thicker from the lower side of the side of the first recess to the center of the first recess. 6. The semiconductor light emitting device according to claim 5, wherein the first conductive semiconductor layer comprises a first semiconductor layer, a second semiconductor layer on which the lower portion of the first recess is disposed, and a second semiconductor layer on the first semiconductor layer, And a third semiconductor layer in which the first recess is extended. The semiconductor device according to claim 5, wherein the cap layer is formed of a single layer of InAlGaN semiconductor. The semiconductor device according to claim 3 or 4, wherein the electron blocking layer comprises a plurality of AlGaN-based semiconductor layers. 12. The semiconductor device according to claim 11, wherein the second conductivity type semiconductor layer includes a plurality of GaN-based semiconductor layers. 14. The method of claim 12, wherein the second conductive semiconductor layer comprises a first nitride layer undoped over the cap layer, a second nitride layer having a second conductivity type dopant concentration over the first nitride layer, An undoped third nitride layer and a fourth nitride layer over the third nitride layer, the fourth nitride layer having a dopant concentration higher than the dopant concentration of the second nitride layer. 14. The semiconductor device according to claim 13, wherein the second conductivity type semiconductor layer has a protrusion protruding in the first recess direction. 14. The semiconductor device according to claim 13, further comprising an electrode layer of a transparent material on the second conductivity type semiconductor layer. A body having a cavity;
First and second lead frames disposed in the body; And
A semiconductor device package comprising the semiconductor device of claim 5.

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