KR102553773B1 - Methods of Forming Structures in Semiconductor Devices - Google Patents

Abstract

Embodiments described herein generally relate to enabling the formation of a metal gate structure having a reduced effective oxide thickness compared to similar structures formed through conventional methods. Following the plasma hydrogenation process, a plasma nitridation process, or a single step plasma hydrogenation and nitride process, is performed on the metal nitride layer of the film stack, thereby removing oxygen atoms disposed within the layers of the film stack, according to some embodiments. and, in some embodiments, adds nitrogen atoms to the layers of the film stack. As a result, the effective oxide thickness of the metal gate structure is reduced with little or no accompanying flatband voltage shift.

Description

Methods of Forming Structures in Semiconductor Devices

Embodiments described herein relate generally to methods and apparatus for processing semiconductor substrates, and more specifically to hydrogenation and nitridation processes that modify the effective oxide thickness of a film.

In integrated circuits, smaller transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), are highly desirable. First, smaller transistors allow more transistors to be formed in a given chip area, thereby reducing chip size. Second, smaller transistors are generally able to switch faster than larger transistors, thereby improving chip performance.

One approach to reducing the size of a MOSFET is scaling, in which critical device dimensions such as transistor length, transistor width, and oxide (or dielectric) thickness are proportionally reduced. In this approach, the transistor channel resistance does not change as the transistor size is reduced, while the transistor's gate capacitance and RC delay decrease proportionally with the size decrease.

However, while reducing the dielectric thickness of MOSFETs is important for scaling MOSFETs to the sizes required by future technology nodes, there are also important trade-offs. Specifically, with a linear decrease in the thickness of the conventional oxide/oxynitride dielectric layer of MOSFETs, there is an exponential increase in gate leakage, resulting in increased power consumption. Moreover, the thickness of the dielectric layer is now close to several atomic layers, raising reliability concerns. Accordingly, any means by which the oxide thickness or effective oxide thickness (EOT) of a transistor can be reduced without an exponential increase in gate leakage is highly desirable. These and other needs are addressed in this disclosure.

Embodiments described herein generally relate to sequential hydrogenation and nitridation processes for reducing interfacial and bulk O atoms of a conductive structure of a semiconductor device. In one embodiment, a method of forming a structure in a semiconductor device is provided, the method comprising depositing a high-k dielectric layer on a semiconductor substrate, a capping layer on the high-k dielectric layer to form part of the structure. depositing, the deposited capping layer having an exposed surface, and exposing the exposed surface to plasma excited hydrogen species and plasma excited nitrogen species. A portion of the substrate includes a capping layer and a high-k dielectric.

In one embodiment, a method of forming a structure in a semiconductor device includes depositing a high-k dielectric layer on a semiconductor substrate, depositing a metal nitride layer on the high-k metal dielectric layer to form part of the structure. step, wherein the portion includes a metal nitride layer and a high-k metal dielectric layer and has a first effective oxide thickness, the deposited metal nitride layer having an exposed surface, the first effective oxide thickness to a second effective oxide thickness; To reduce, sequentially exposing the exposed surface to non-oxidizing plasma excited hydrogen species followed by plasma excited nitrogen species.

In another embodiment, a method of forming a structure in a semiconductor device includes depositing a high-k dielectric layer on a semiconductor substrate, depositing a metal nitride layer on a high-k metal dielectric layer, and subjecting an exposed surface to a plasma. sequentially exposing the excited hydrogen species followed by plasma excited nitrogen species, sequentially exposing the exposed surface to plasma excited hydrogen species and then plasma excited nitrogen species, and then exposing the exposed surface to air. , and after exposing the exposed surface to air, performing a thermal annealing process on the high-k dielectric layer and the metal nitride layer at a specified temperature for a specified time.

In another embodiment, a method of forming a structure in a semiconductor device includes depositing a high-k dielectric layer on a semiconductor substrate, depositing a metal nitride layer on a high-k metal dielectric layer to form part of a structure. step, the portion comprising a metal nitride layer and a high-k metal dielectric layer and having a first effective oxide thickness, the deposited metal nitride layer having an exposed surface, subjecting the exposed surface to a non-oxidizing plasma excited hydrogen species; and then reducing the first effective oxide thickness to a second effective oxide thickness by sequential exposure to plasma excited nitrogen species.

In another embodiment, a method of forming a structure in a semiconductor device is provided, the method comprising: depositing a high-k dielectric layer on a semiconductor substrate; depositing a capping layer on a high-k metal dielectric layer; exposing the exposed surface of the ? to plasma excited hydrogen species and plasma excited nitrogen species, exposing the exposed surface to air, and thermally annealing the high-k dielectric layer and the capping layer at a specified temperature for a specified time. Including performing the process.

In another embodiment, a method of forming a structure in a semiconductor device is provided, the method comprising depositing a high-k dielectric layer on a semiconductor substrate, a capping layer on the high-k dielectric layer to form part of the structure. depositing, the deposited capping layer having an exposed surface, and exposing the exposed surface to a plasma excited hydrogen species and a plasma excited nitrogen species, wherein the plasma excited hydrogen species comprises ammonia; The nitrogenous species included include nitrogen gas (N ₂ ). Part of the structure includes a capping layer and a high-k dielectric.

In another embodiment, a method of forming a structure in a semiconductor device is provided, the method comprising: depositing a metal nitride capping layer on a high-k dielectric layer formed over a surface of a substrate, and exposing the deposited metal nitride capping layer. exposing the surface to a plasma comprising a first gas comprising hydrogen containing species and a second gas comprising nitrogen containing species, wherein the hydrogen containing species of the first gas comprises nitrogen.

In another embodiment, a method of forming a structure in a semiconductor device is provided, the method comprising: depositing a high-k dielectric layer on a semiconductor substrate; depositing a capping layer on the high-k dielectric layer; exposing the exposed surface of the ? to plasma excited hydrogen species and plasma excited nitrogen species, exposing the exposed surface to air, and thermally annealing the high-k dielectric layer and the capping layer at a specified temperature for a specified time. Including performing the process.

In another embodiment, a method of forming a structure in a semiconductor device is provided, the method comprising: depositing a high-k dielectric layer on a semiconductor substrate, a capping layer on the high-k dielectric layer to form part of the structure. depositing a portion comprising a capping layer and a high-k dielectric layer, the deposited capping layer having an exposed surface, and exposing the exposed surface to plasma excited hydrogen species and plasma excited nitrogen species; and wherein the plasma excited hydrogen species comprises ammonia and the plasma excited nitrogen species comprises nitrogen gas (N ₂ ).

In order that the above-mentioned features of the present disclosure may be understood in detail, a more specific description of the present disclosure briefly summarized above may be made with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it is to be understood that the accompanying drawings illustrate only typical embodiments of the present disclosure and are therefore not to be regarded as limiting the scope of the present disclosure, as the present disclosure may admit other equally effective embodiments. It should be noted.
1 illustrates a cross-sectional view of a contact structure formed on a substrate as part of a semiconductor device, in accordance with an embodiment of the present disclosure.
2A-2E are schematic diagrams of a metal nitride layer within the contact structure of FIG. 1 at various stages of fabrication of the contact structure, in accordance with an embodiment of the present disclosure.
3 shows an X-ray photoelectron spectroscopy (XPS) spectrum 310 for a deposited and thermally annealed TiN film before treatment and an XPS spectrum for the same deposited and thermally annealed TiN film after treatment, according to an embodiment of the present disclosure. It is the graph of (320).
4 is a cross-sectional side view of a processing chamber configured to implement one or more aspects of the present disclosure.
5 is a top plan view of a multi-chamber processing system configured to implement one or more aspects of the present disclosure.
6 presents a flow diagram of process steps for reducing bulk and interfacial oxygen of a contact structure, in accordance with some embodiments of the present disclosure.
7A-7E are schematic cross-sectional views of a semiconductor device corresponding to different stages of the process of FIG. 6, in accordance with various embodiments of the present disclosure.
8 presents a flow diagram of process steps for reducing bulk and interfacial oxygen of a contact structure, in accordance with some embodiments of the present disclosure.
9 presents a flow diagram of process steps for reducing bulk and interfacial oxygen of a contact structure, in accordance with some embodiments of the present disclosure.
10 illustrates a cross-sectional view of a metal gate structure formed in accordance with an embodiment of the present disclosure.
11 presents a flow diagram of process steps for reducing the effective oxide thickness (EOT) of a metal gate structure, in accordance with various embodiments of the present disclosure.
12A-12J are schematic cross-sectional views of a semiconductor device corresponding to different stages of the process of FIG. 11, in accordance with various embodiments of the present disclosure.
13 presents a flow diagram of process steps for processing a metal gate structure in a single step hydrogenation and nitridation process, in accordance with various embodiments of the present disclosure.
14A-14J are schematic cross-sectional views of a semiconductor device corresponding to different stages of the process of FIG. 13, in accordance with various embodiments of the present disclosure.
For ease of understanding, where possible, like reference numbers have been used to indicate like elements common to the drawings. It is contemplated that elements and features of one embodiment may be advantageously incorporated into other embodiments without further recitation.

Embodiments described herein generally relate to methods and apparatus for nitriding layers of a structure in a semiconductor device formed on a substrate. The single-step plasma hydrogenation and nitridation process may be performed on a stack of metal layers that is thermally annealed prior to deposition of a metal layer or metal layers included in the conductive structure, eg, a metal capping layer. In various embodiments, the single step plasma hydrogenation and nitridation process may be performed before the thermal annealing process, after the thermal annealing process, or both before and after the thermal annealing process. In each embodiment, the nitrogen atom concentration in the conductive structure is advantageously increased, thereby reducing the electrical resistance of the conductive structure. One such conductive structure is illustrated in FIG. 1 .

Conductive structures with reduced interfacial and bulk oxygen

1 illustrates a cross-sectional view of a conductive structure 100 or contact structure formed on a semiconductor substrate 110 as part of a semiconductor device, in accordance with an embodiment of the present disclosure. Conductive structure 100 can be any portion of a semiconductor device that is configured to conduct current and therefore benefits from reduced electrical resistance. In the embodiment illustrated in FIG. 1 , conductive structure 100 is shown as a contact structure for providing electrical contact to source or drain structure 101 , where conductive structure 100 is formed and subjected to a planarization process, such as a chemical mechanical It is shown after polishing (CMP) has been completed on the semiconductor substrate 110 . For example, the conductive structure 100 may be a contact structure for a field effect transistor (FET).

Conductive structure 100 is disposed in a contact well 109 or aperture, which is a cavity formed in insulating material 120 . Isolation material 120, alternatively referred to as shallow trench isolation (STI), may include one or more dielectric materials, such as silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), or multiple layers thereof. there is. The insulating material 120 may be formed by high-density plasma (HDP), flowable chemical vapor deposition (FCVD), tetraethyl orthosilicate (TEOS), or the like. Conductive structure 100 includes a plurality of metal layers, eg, first metal layer 102, metal nitride layer 103, and at least conductive disposed over first metal layer 102 and metal nitride layer 103. Can contain stacks of parts. The conductive portion may include capping layer 104 and/or conductive layer 106 .

The source or drain structure 101 may be formed from the semiconductor substrate 110 or from a different semiconductor material deposited on the semiconductor substrate 110 . In the latter case, different semiconductor materials may include silicon-germanium, III-V compound semiconductor materials, and the like. For example, in some embodiments an epitaxial process may be performed to grow the source or drain structure 101 .

A first metal layer 102 is formed on the source or drain structure 101 and comprises one or more metals selected to form a silicide 105 at the interface with the source or drain structure 101 after a suitable thermal annealing process. do. For example, in some embodiments, the first metal layer 102 includes or consists entirely of titanium (Ti) and may have a thickness of about 40 Å to about 50 Å. A metal nitride layer 103 is formed on the first metal layer 102 and includes, for example, a metal nitride to act as a diffusion barrier layer of the conductive structure 100 . In some embodiments, the metal nitride layer 103 includes titanium nitride (TiN), tantalum nitride (TaN), and/or tungsten nitride (W ₃ N ₂ ) and has a thickness of about 10 Å to 20 Å. can have Capping layer 104 is formed on metal nitride layer 103 and includes one or more metals, typically after a thermal annealing process in which silicide 105 is formed on conductive structure 100 . In some embodiments, the conductive structure 100 may include a separately formed conductive layer 106, which may include a metal, such as cobalt, copper, ruthenium, nickel, tungsten, aluminum, or other useful metal, or alloys thereof. ) may be included. In some embodiments, the capping layer 104 includes Co and may have a thickness between about 10 Å and 20 Å. In other embodiments, the capping layer 104 includes a metal (eg, cobalt) that completely fills the remainder of the contact well 109 .

As previously mentioned, the presence of O atoms in the first metal layer 102 and/or metal nitride layer 103 adversely affects the effective conductivity of the conductive structure 100 . First, oxides of any metal layer increase the bulk electrical conductivity of the formed metal layer. Second, the interfacial oxide, that is, the metal oxide formed at the interface between the metal nitride layer 103 and the capping layer 104, contributes to poor adhesion between the metal nitride layer 103 and the capping layer 104, and the conductive structure ( 100), potentially resulting in voids that significantly reduce the effective cross-sectional area. Unfortunately, low concentrations of O atoms are almost always present to some extent in the bulk portions of the metal layers of conductive structure 100 . Also, in many cases, oxides may form in higher concentrations on metal surfaces that are exposed to air between manufacturing steps. According to embodiments of the present disclosure, the presence of bulk and interfacial O atoms in conductive structure 100 may be reduced through a sequential hydrogenation and plasma nitridation process. A physical model of how such a sequential process reduces the bulk and interfacial O atoms of conductive structure 100 is illustrated in FIGS. 2A-E and 3A-D.

Physical model for reducing interfacial and bulk oxygen

2A-2E are schematic diagrams of a metal nitride layer 103 in contact structure 100 at various stages of fabrication of contact structure 100, according to an embodiment of the present disclosure. Note that FIGS. 2a-2e only illustrate one possible surface end of the metal nitride layer 103 and only represent a typical TiN structure. In some embodiments, the metal nitride layer 103 can have any other possible surface termination or crystalline structure associated with a TiN layer.

In FIG. 2A , a portion 200 of the metal nitride layer 103 is schematically illustrated immediately after the metal nitride layer 103 is deposited on the first metal layer 102 and before the portion 200 is exposed to air. . Portion 200 includes surface 201 of portion 200, which surface will ultimately have capping layer 104 deposited thereon. As shown, portion 200 has a NaCl cubic structure and is composed primarily of Ti and N atoms. Additionally, portion 200 includes a low concentration of bulk O atoms 211 (crosshatched) typically disposed in the bulk region of portion 200 below surface 201 . Bulk O atoms 211 may be entrained by contaminants found in the processing environment during the deposition process used to form portion 200 . Portion 200 also includes voids 213, which are regions within the crystal lattice of portion 200 that are generally devoid of atoms. Voids 213 are locations where additional oxidation within portion 200 may occur when nitride layer 103 is exposed to air. When the metal nitride layer 103 is formed by an atomic layer deposition (ALD) process, the voids 213 are found in the ALD process compared to traditional chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes. Note that it is relatively common due to membrane nucleation and growth mechanisms. Accordingly, one or more of the embodiments of the present disclosure provided herein may provide significant benefits when used with films formed by an ALD process over conventional PVD or CVD type processes.

In FIG. 2B , portion 200 after being removed from the processing system that deposited the metal nitride layer 103 is illustrated. For example, the semiconductor substrate 110 on which portion 200 is formed may be exposed to air in preparation for a thermal annealing process. Conventional thermal treatment chambers, such as annealing process chambers, typically have a first metal layer layer due to differences in the required cleanliness, thermal management control and vacuum level requirements needed to form most advanced device node applications today. (102) and in processing systems different from those used to form the metal nitride layer (103). Thus, in FIG. 2B , portion 200 after being exposed to air is illustrated. As shown, surface 201 is partially oxidized, and surface O atoms 212 occupy most or all of the voids 213 disposed on surface 201 . In some cases, some of the voids 213 disposed within portion 200 are occupied with bulk O atoms 211 as a result of portion 200 being exposed to air.

In FIG. 2C , portion 200 is illustrated after undergoing a thermal annealing process to form silicide 105 as shown in FIG. 1 . Some or all of the remaining empty spaces 213 are filled with bulk O atoms 211 or surface O atoms 212 . In some embodiments, bulk O atoms 211 may also replace some of the N atoms disposed within portion 200 . Accordingly, the annealing process generally increases the number of both bulk O atoms 211 and surface O atoms 212 in portion 200 . Even when the depth of the surface O atoms 212 on the surface 201 is only one or two monolayers, the effect on the resistivity of the conductive structure 100 is particularly significant for smaller device structures, e.g., advanced For device structures associated with advanced device nodes (eg, sub-65 nm technology nodes), this can be substantial.

2D , the portion after exposure to hydrogen atoms reacting with bulk O atoms 211 and/or surface O atoms 212 included in portion 200, according to various embodiments of the present disclosure. (200) is exemplified. In some embodiments, bulk O atoms 211 and/or surface O atoms 212 react with hydrogen atoms from thermally dissociated hydrogen gas (H ₂ ) as part of a thermal hydrogenation process, while In other embodiments, bulk O atoms 211 and/or surface O atoms 212 react with hydrogen atoms from a hydrogen containing plasma as part of a plasma hydrogenation process.

The thermal hydrogenation process may be performed in a suitable rapid thermal treatment chamber under specific processing conditions, including heating portion 200 to at least about 550°C to about 650°C. The plasma hydrogenation process can be performed in a suitable plasma processing chamber under specific processing conditions. Exemplary plasma processing chambers and plasma processing conditions for the plasma hydrogenation process are each described below. As shown, the hydrogenation process reduces or otherwise removes all or substantially all of the surface O atoms 212 from surface 201 , leaving voids 213 . Additionally, the plasma hydrogenation process may also remove some or all of the bulk O atoms 211 disposed below the surface 201 .

In FIG. 2E , portion 200 after undergoing a plasma nitridation process is illustrated, in accordance with various embodiments of the present disclosure. The plasma nitridation process can be performed in a suitable plasma processing chamber under specific processing conditions, and exemplary plasma processing chambers and plasma processing conditions for the plasma nitridation process are each described below. In some embodiments, the plasma nitridation process can be performed in the same plasma processing chamber that performs the plasma hydrogenation process. Additionally, no atmospheric breakdown occurs between the plasma or thermal hydrogenation process and the plasma nitridation process. That is, portion 200 is not exposed to air after the plasma or thermal hydrogenation process and prior to the plasma nitridation process.

As shown, the nitridation process causes vacancies 213 to be filled with N atoms, whereby surface 201 has little or no surface O atoms 212 disposed thereon. As a result, surface 201 can be saturated with N atoms, and as a result, subsequent oxidation of surface 201 is greatly reduced, even when surface 201 is re-exposed to air prior to deposition of capping layer 104. become or are removed Therefore, adhesion between the surface 201 of the metal nitride layer 103 and the capping layer 104 is improved. Additionally, some or all of the voids below the surface 201 may be filled with N atoms instead of bulk O atoms 211, and the metal nitride layer 103, the first metal layer 102, and the conductive layer as a whole Further improve the electrical conductivity of structure 100.

3 shows an X-ray photoelectron spectroscopy (XPS) spectrum 310 for a deposited and thermally annealed TiN film before treatment and an XPS spectrum for the same deposited and thermally annealed TiN film after treatment, according to an embodiment of the present disclosure. It is the graph of (320). The treatment includes a plasma or thermal hydrogenation process followed by a plasma nitridation process. The thermal annealing process is a rapid thermal process in a nitrogen gas (N ₂ ) or ammonium (NH ₃ ) environment at temperatures of about 550 °C to 600 °C. The plasma hydrogenation process has a temperature of about 340 °C to 500 °C, a process pressure of about 10 mTorr to 150 mTorr, a plasma power of about 250 W to 2000 W, a H ₂ flow rate of about 5 sccm to 100 sccm, and a process pressure of about 250 sccm to 100 sccm. It is performed on the substrate pedestal in an inductively coupled plasma (ICP) chamber with an argon (Ar) flow rate of 2000 sccm, for a duration of about 30 seconds to about 200 seconds. The plasma nitridation process has a temperature of about 350 °C to 500 °C, a process pressure of about 10 mTorr to 100 mTorr, a plasma power of about 250 W to 2000 W, an NH ₃ flow rate of about 5 sccm to 100 sccm, and a process pressure of about 300 sccm to 500 sccm. sccm nitrogen (N ₂ ) flow rate, and an argon (Ar) flow rate of about 20 sccm to 500 sccm, for a duration of about 30 seconds to about 200 seconds, on the substrate pedestal in the same ICP chamber.

As is well known in the art, an XPS spectrum of a TiN film can include multiple peaks, each representing a different relative concentration of different titanium-containing materials. For example, a Ti-O peak at a binding energy of approximately 458.5 eV generally indicates the presence of Ti-O bonds and, therefore, O atoms in the titanium-containing material; The Ti-O-N peak at a binding energy of approximately 457 eV generally indicates the presence of Ti-O-N bonds and, therefore, N atoms and O atoms in the titanium containing material; The Ti-N peak at a binding energy of approximately 454.9 eV generally indicates the presence of Ti-N bonds and, therefore, nitrogen (N) atoms in the titanium containing material.

XPS spectrum 310 is associated with the Ti 2p shell for the deposited TiN film after the thermal annealing process described above has been performed, and XPS spectrum 320 is associated with the Ti 2p shell for the deposited TiN film, following the plasma hydrogenation process described above. Ti 2p shell to deposited and thermally annealed TiN film after undergoing a plasma nitridation process. As shown, the peak indicating the presence of Ti-O bonds and the peak indicating the presence of Ti-O-N bonds are significantly lower in the XPS spectrum 320 than in the XPS spectrum 310, indicating the presence of O atoms in the TiN film. clearly indicates a decrease in their presence. Also, the peak indicating the presence of Ti—N bonds is significantly higher in XPS spectrum 320 than in XPS spectrum 310, clearly indicating an increase in the concentration of N atoms in the TiN film. Therefore, by performing hydrogenation and nitridation processes after the annealing process, the concentration of O atoms in the metal nitride film 103 can be significantly reduced, and the concentration of N atoms in the metal nitride film 103 can be significantly increased. .

2A-2E and 3 illustrate the effect of sequential hydrogenation and nitridation processes on metal nitride layer 103 after annealing. In some embodiments, employing a plasma or thermal hydrogenation process followed by a plasma nitridation process on portion 200 prior to a thermal annealing process may have similar beneficial effects. Specifically, since surface 201 can be mostly or completely saturated with N atoms due to the plasma nitridation process (as shown in FIG. 2E), subsequent air exposure and thermal annealing of surface 201 will reduce oxidation to a lesser extent. or not at all As a result, the concentration of bulk O atoms 211 found in portion 200 and the concentration of surface O atoms 212 on surface 201 are not significantly increased.

System Overview for Sequential Hydrogenation and Nitriding

4 is a schematic cross-sectional view of a plasma processing chamber 400 configured to implement one or more aspects of the present disclosure. Plasma processing chamber 400 may be any suitable plasma processing chamber, such as an inductively coupled plasma (ICP) processing chamber. As shown in FIG. 4 , the processing chamber 400 may include a chamber wall 406 , a chamber lid 408 , and a substrate support pedestal 404 disposed within the chamber wall 406 . Typically, chamber walls 406 are coupled to electrical ground 416 . Chamber cover 408 may be constructed of any suitable dielectric, such as quartz. In some embodiments, the dielectric cover 408 can take a different shape (eg, dome shape). In some embodiments, chamber lid 408 may be coated with a ceramic coating, such as an oxide containing yttrium, for protection from plasma species. In one embodiment, the ceramic coating is a high performance material (HPM) composed of a compound (Y ₄ Al ₂ O ₉ ) and a solid solution (Y _2-x Zr _x O ₃ ) (Y ₂ O _{3 -} ZrO ₂ solid solution). The ceramic coating may have a thickness in the range of about 100 microns to about 300 microns, such as about 200 microns.

Above the chamber lid 408, a radio frequency (RF) antenna comprising at least one induction coil element 410 may be disposed (two coaxial coil elements are shown). In some embodiments, induction coil elements 410 may be disposed around at least a portion of chamber wall 406 . As shown, one end of the induction coil element 410 can be coupled to an RF power source 414 through a first impedance matching network 412 and the other end can be connected to an electrical ground 417 . Power source 414 is typically capable of generating up to 10 kilowatts (kW) with an adjustable frequency ranging from 2 to 160 MHz, with 13.56 MHz being a typical operating frequency. The RF power supplied to the induction coil elements 410 can be power cycled (i.e., change the power input from a high level to a low level) or pulsed (i.e., on-state) with a frequency ranging from 1 to 100 kHz. and can be switched between the off state).

A shielding electrode 418 may be interposed between the induction coil elements 410 of the RF antenna and the chamber lid 408 . Alternatively, shield electrode 418 may be electrically coupled to or floated to electrical ground 419 via any suitable means for making and breaking electrical connections, such as switch 420 as illustrated in FIG. 4 . there is.

In some embodiments, a detector 422 may be attached to the chamber wall 406 to facilitate determining when a gas mixture within the chamber 400 has been activated into a plasma. Detector 422 may, for example, detect radiation emitted by the excited gases or may use optical emission spectroscopy (OES) to measure the intensity of one or more wavelengths of light associated with the generated plasma. .

The pedestal 404 can be coupled to the biasing power supply 426 through a second impedance matching network 424 . The biasing power supply 426 is generally capable of generating an RF signal having a tunable frequency ranging from 2 to 160 MHz and a power of 0 to 10 kW, similar to the RF power supply 414 . Optionally, the biasing power supply 426 may be a direct current (DC) or pulsed DC source.

In operation, a substrate 428, e.g., a semiconductor substrate, may be placed on the pedestal 404, and process gases pass through the entry ports 432 in an effort to form a gaseous mixture 434. It may be supplied from the gas panel 430 . Typical process gases that may be used in one or more of the processes described herein are described below. Entry ports 432 may be coated with a ceramic coating, such as HPM. The gaseous mixture 434 can be activated into a plasma 436 in the processing chamber 400 by applying power from an RF power source 414 . The pressure inside the processing chamber 400 may be controlled using a throttle valve 438 and a vacuum pump 440 . In some embodiments, the temperature of the chamber wall 406 is controlled by liquid-containing conduits (not shown) that run through the chamber wall 406, or embedded in the chamber wall 406 (eg, heating cartridges or Coils) may be controlled using heating elements wound (eg, heater wrap or tape) around the processing chamber 400 .

The temperature of the substrate 428 can be controlled by stabilizing the temperature of the pedestal 404 . In some embodiments, helium (He) gas from gas source 442 may be provided through gas conduit 444 to channels (not shown) formed in the pedestal surface beneath substrate 428. can Helium gas may facilitate heat transfer between the pedestal 404 and the substrate 428 . During processing, pedestal 404 may be heated to a steady state temperature, and then helium gas may facilitate uniform heating of substrate 428 . The pedestal 404 may include a heating element (not shown), such as a resistive heater embedded within the pedestal 404 or the pedestal or the substrate 428 if the substrate 428 is on the pedestal. can be so heated by a generally aimed lamp. Using such thermal control, the substrate 428 can be maintained at a temperature of about 20 to 350 degrees Celsius (°C).

A controller 446 may be provided to allow control of the components of the processing chamber 400 as described herein. The controller 446 may include a central processing unit (CPU) 448 , a memory 450 , and support circuits 452 for the CPU 448 . Controller 446 may interface with RF power supply 414 , switch 420 , detector 422 , and biasing power supply 426 .

The controller 446 may be any suitable type of general purpose computer processor that may be used in an industrial setting to control the various chambers and sub-processors. Memory 450 for CPU 448, or other computer readable media, may be any readily available memory forms, such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital storage. Support circuits 452 may be coupled to CPU 448 in an effort to support the processor in a conventional manner. These circuits may include cache, power supplies, clock circuits, input/output (I/O) circuits and subsystems, and the like. For some embodiments, the techniques disclosed herein for activating and maintaining a plasma may be stored in memory 450 as software routines. Software routines may also be stored and/or executed by a second CPU (not shown) located remotely from the hardware controlled by CPU 448.

According to some embodiments of the present disclosure, the thermal or plasma hydrogenation process is followed by a plasma nitridation process, hereinafter referred to as a "sequential hydrogenation/nitridation process", before a thermal annealing is performed on the substrate and/or later performed on the substrate. The sequential hydrogenation/nitridation process may include a capacitively coupled plasma process or an inductively coupled plasma process. In some embodiments, the plasma for the hydrogenation/nitridation process can be formed at a remote plasma source outside the processing chamber 400, and in other embodiments, the plasma for the plasma process is in-situ, i.e., processing may be formed in the chamber 400 . Hydrogenation and nitridation may be performed in the same step, referred to hereinafter as a "single step plasma hydrogenation and nitridation process". In some embodiments, the plasma for the single-step plasma hydrogenation and nitridation process may be formed at a remote plasma source external to the processing chamber 400, and in other embodiments, the plasma for the plasma process may be formed in-situ; That is, it may be formed in the processing chamber 400 .

In the plasma hydrogenation process, plasma excited H radicals and/or ions react with bulk O atoms 211 and/or surface O atoms 212 to create vacancies 213 . In the case of a thermal hydrogenation process, dissociated H atoms react with bulk O atoms 211 and/or surface O atoms 212 to create vacancies 213 . In the nitridation process, N radicals and/or ions occupy vacancies 213 .

During the plasma hydrogenation process, the processing environment within the processing chamber 400 is generally at a relatively lower concentration of O atoms due to the presence of H atoms, eg, dissociated H atoms, H radicals, and/or H ions. Note that it includes Thus, the processing environment within the processing chamber 400 during the plasma hydrogenation process has a lower concentration of O atoms than the processing environment within the processing chamber 400 during the nitridation process or the processing environment within the processing chamber during deposition of a metal nitride layer. can include However, for both hydrogenation or nitration, lower concentrations of O atoms are generally advantageous. Accordingly, in some embodiments, the processing chamber may be conditioned with a plasma process, eg, a H ₂ process, prior to the plasma hydrogenation process and/or nitridation process to remove any trace O species.

When the metal nitride layer to be processed in the hydrogenation/nitride process or single-step plasma hydrogenation and nitridation process described herein is a thin film having a thickness of about 200 Å or less, the ICP process generally removes the metal nitride layer during hydrogenation or nitridation. Less likely to damage it. Specifically, the plasma sheath in an ICP process is typically smaller than the plasma sheath in a CCP chamber, and therefore ions traveling through it typically have proportionally less energy, eg on the order of tens of eV, eg, It has an energy of 10 to 20 eV. In contrast, ions in a CCP chamber typically have energies on the order of hundreds of eV (eg, > 200-400 eV) and can consequently create significant damage to the metal nitride layer. In addition, the ICP process produces more ions, radicals, and other plasma excited species that are normally formed in close proximity to the substrate in an ICP processing chamber compared to CCP and remote plasma sources used in other types of processing chambers. Due to the high density, it can provide more oxygen removal from the metal nitride layer than by use of CCP or remote plasma processes. In comparison, the concentration of radicals from CCP and remote plasma sources is relatively low.

In embodiments where the plasma for the plasma process is formed in-situ, the plasma is formed by the induction coil elements 410, the first impedance matching network 412, the RF power supply 414, and in some embodiments the first 2 impedance matching network 424 and biasing power supply 426. In such embodiments, the plasma process may include introducing into the processing chamber 400 one or more process gases selected to generate a particular plasma species (ie, ions, neutral atoms, and/or radicals). there is. More specifically, for plasma hydrogenation processes, one or more process gases are selected to produce plasma excited hydrogen species, while for plasma nitridation processes, one or more process gases are selected to generate plasma excited nitrogen species. Thus, for a plasma hydrogenation process, the one or more process gases may include hydrogen (H ₂ ) and/or D ₂ , and for a plasma nitridation process, the one or more process gases may include nitrogen (N ₂ ) or ammonia (NH _{3 )} . ) may be included. Alternatively or additionally, the plasma process may include introducing one or more carriers and/or an inert gas, such as argon (Ar), into the processing chamber 400 . For single-step plasma hydrogenation and nitridation processes, the one or more process gases may include hydrogen (H ₂ ), D ₂ , nitrogen (N ₂ ), ammonia (NH ₃ ), or hydrazine (N ₂ H ₄ ).

In some embodiments, the plasma hydrogenation process primarily includes formation of a plasma comprising a process gas consisting essentially of hydrogen (H ₂ ) forming reactive species provided from the plasma. Formation of hydrogen-containing species using a plasma formed using H ₂ (eg, inductively coupled plasma) generates significantly more hydrogen-containing radicals and ions than a thermal hydrogenation process using a H ₂ -containing process gas. It will be noted that it will have, thus improving the effectiveness of the plasma hydrogenation process and reducing undesirable reactions found when using impure hydrogen containing reactive gases.

In some embodiments, one or more process gases are activated by an RF power source, eg, RF power source 414 . The RF power may be pulsed with a 2% to 70% duty cycle and may range from about 100 W to about 2500 W. The RF power can range from about 100 W to about 2500 W continuous wave. The process chamber may have a chamber pressure during the plasma process ranging from about 10 mTorr to about 200 mTorr, while the process temperature, e.g., the temperature of the pedestal 404, may range from 20 °C to about 500 °C. .

In an exemplary embodiment, the plasma hydrogenation process comprises a process temperature of about 400 °C to about 500 °C, a chamber pressure of about 5 mTorr to about 20 mTorr, an RF power of about 1000 W to about 2000 W, and about 175 V to about 250 V. with a biasing voltage of V, wherein the H ₂ flow is between about 20 sccm and about 40 sccm and the Ar flow is between about 400 sccm and about 500 sccm and the duration is between about 50 seconds and about 300 seconds. Plasma excited hydrogen species generated from the plasma inside the process chamber 400 are transferred to a metal nitride layer (eg, metal nitride layer 103) of a partially formed conductive structure (eg, conductive structure 100). Some or all of the oxides present on the exposed surface of may be reduced. In some embodiments, the plasma excited hydrogen species may also be some of the O atoms present in the bulk material of the metal nitride layer or other metal layers of the conductive structure, such as the first metal layer 102 of the conductive structure 100. or all can be reduced. Such reduction of O atoms is illustrated above in conjunction with FIGS. 2d and 3b.

In another exemplary embodiment, the plasma nitridation process is performed at a process temperature of about 400 °C to about 500 °C, a chamber pressure of about 5 mTorr to about 25 mTorr, an RF power of about 1000 W to about 2000 W, and about 175 V to about 175 V. at a biasing voltage of 250 V, wherein the NH ₃ flow is from about 20 sccm to about 40 sccm, the N ₂ flow is from about 400 sccm to about 600 sccm, the Ar flow is from about 400 sccm to about 500 sccm, and the duration is about 50 seconds to about 300 seconds. Plasma excited nitrogen species generated from the plasma inside the process chamber 400 will saturate the exposed surface of the partially formed conductive structured metal nitride layer (e.g., the surface 201 of the metal nitride layer 103). can In some embodiments, the plasma excited nitrogen species may also fill voids present in the bulk material of the metal nitride layer or other metal layers of the conductive structure. Such nitridation is described above in conjunction with FIGS. 2e and 3c.

In some embodiments, the single step plasma hydrogenation and nitridation process is performed at a process temperature of about 350° C. to about 500° C. (e.g., substrate pedestal temperature), an RF power of about 300 W to about 2000 W, a flow rate of NH ₃ of about 5 sccm to about 100 sccm, a flow rate of N ₂ of about 50 sccm to about 1000 sccm, a flow rate of about 1 to about 1000 sccm sccm of helium (He) flow rate, the substrate bias is applied at a frequency of about 2 MHz to about 160 MHz and a bias power of about 0 kW to about 10 kW.

In some embodiments, the single step plasma hydrogenation and nitridation process is performed at a chamber pressure of about 15 mTorr to about 25 mTorr, at a processing temperature of about 350 °C to about 500 °C, for a duration of about 85 seconds to about 95 seconds, at about An RF power of 300 W to about 1600 W, a flow rate of NH ₃ of about 10 sccm to about 40 sccm, a flow rate of N ₂ of about 200 sccm to about 550 sccm, and a flow rate of Ar of about 200 to about 550 sccm, No substrate bias power is applied.

In embodiments where the plasma for a plasma process is formed remotely, the plasma may be formed via any technically feasible remote plasma source. In such embodiments, the plasma process may include introducing into the remote plasma source one or more process gases selected to generate plasma excited hydrogen species or plasma excited nitrogen species. Alternatively or additionally, the remote plasma process may include introducing one or more carriers and/or an inert gas, such as argon (Ar), into the remote plasma source. The remotely generated plasma species then flow into the processing chamber 400 and treat the metal nitride layer of the conductive structure formed on the substrate disposed in the processing chamber 400 . As described above, depending on whether the plasma species is a plasma excited hydrogen species or a plasma excited nitrogen species, the interfacial and bulk O atoms of the metal nitride layer are reduced or the nitrification of the metal nitride layer is enhanced.

In some embodiments, a thermal hydrogenation process rather than a plasma hydrogenation process may be employed to expose the metal nitride layer to hydrogen atoms. In such embodiments, the thermal hydrogenation process generally occurs at an elevated temperature, for example from about 500 °C to about 650 °C. At such elevated temperatures, the H ₂ gas dissociates into individual atoms, which can then react with the O atoms of the metal nitride layer 103 to create vacancies 213 . Also, in such embodiments, the thermal hydrogenation process is generally performed in a process chamber different from process chamber 400 . For example, in some embodiments, the thermal hydrogenation process is performed in a rapid thermal treatment chamber. In such embodiments, the salicidation process may be performed concurrently with the thermal hydrogenation process, thereby eliminating the subsequent annealing process.

In embodiments where a thermal annealing process is employed to expose the metal nitride layer to hydrogen atoms, the plasma nitridation process is performed without atmospheric breakdown exposing the metal nitride layer 103 to air. For example, in such embodiments, one chamber of a multi-chamber processing system can be configured to perform a thermal hydrogenation process and another chamber of the same multi-chamber processing system can be configured to perform a plasma nitridation process. Thus, the substrate on which the metal nitride layer 103 is formed can be subjected to a thermal hydrogenation process and then transferred directly to a plasma nitridation chamber without exposure to air.

5 is a top view of a multi-chamber processing system 500 configured to implement one or more aspects of the present disclosure. Multi-chamber processing system 500 is configured to perform one or more fabrication processes on individual substrates, such as silicon wafers, to form semiconductor devices. The multi-chamber processing system 500 includes a transfer chamber 506, a buffer chamber 508, single wafer load locks 510 and 512, processing chambers 514, 516, 518, 520, 522, and 524, a preheat chamber. s 523 and 525, and some or all of robots 526 and 528. Single wafer load locks 510 and 512 may include heating elements 513 and are attached to buffer chamber 508 . Processing chambers 514 , 516 , 518 , and 520 are attached to transfer chamber 506 . Process chambers 522 and 524 are attached to buffer chamber 508 . The operation of multi-chamber processing system 500 is controlled by computer system 530. Computer system 530 may be any device or combination of devices configured to implement the operations of the invention presented herein. As such, computer system 530 may be a general purpose computer and/or controller or array of controllers composed of software that, when executed, performs the operations of the present invention. One example of ^a suitable multi-chamber processing system 500 is the Endura ^® RTM CL system manufactured by Applied Materials, Inc. of Santa Clara, Calif.

Each of the processing chambers 514, 516, 518, 520, 522, and 524 may be configured to perform one or more process steps of fabrication of a conductive structure in a semiconductor device, such as a contact structure for a field effect transistor (FET). there is. More specifically, processing chambers 514, 516, 518, 520, 522, and 524 include one or more metal deposition chambers, surface cleaning and preparation chambers, thermal annealing and/or thermal hydrogenation chambers, and plasma hydrogenation/nitridation chambers. can include

For a contact structure comprising, for example, a Ti-TiN-Co stack formed on a silicon source or drain structure, in some embodiments, multi-chamber processing system 500 may perform several process steps in the fabrication process of such a conductive structure. It can be configured to sequentially perform them. In such embodiments, processing chamber 514 may be configured to perform a surface cleaning and preparation process on an exposed surface of a silicon source or drain structure, and processing chamber 516 may be configured to perform a surface cleaning and preparation process on the prepared silicon source or drain structure. It can be configured to sequentially deposit Ti and TiN layers, with processing chambers 522 and/or 524 performing a rapid thermal treatment (RTP) or other thermal annealing process on the Ti/TiN layers and source or drain structure. may be configured to form a silicide, process chamber 518 may be configured to deposit a Co capping layer on the annealed Ti/TiN layers, and process chamber 520 may be configured to perform hydrogenation prior to or after a thermal annealing process. It may be configured to perform a nitridation process following the process. Thus, in such embodiments, a complete contact structure may be formed without atmospheric breakdown and consequent undesirable oxidation of one or more layers of the contact structure.

In alternative embodiments, not all process steps to form a complete contact structure are performed on a single multi-chamber processing system 500 . For example, in some embodiments, multi-chamber processing system 500 may include metal deposition processing chambers while the thermal annealing silicidation process may be performed on a different substrate processing system. In such embodiments, it is known that atmospheric destruction occurs prior to the thermal annealing process, and such atmospheric destruction can increase the presence of O atoms on the interfacial surface of the metal nitride layer and in the bulk material of the metal nitride layer of the contact structure. . However, prior to atmospheric destruction, a sequential plasma (or thermal) hydrogenation/plasma nitridation process or a single step plasma hydrogenation and nitridation process may be performed, wherein the multi-chamber processing system 500 includes metal deposition chambers and one or more plasma nitridation processes. This is because it can consist of both processing chambers. Thus, the multi-chamber processing system 500 processes the substrate after deposition of the first metal layer 102 and the metal nitride layer 103 but before the substrate is removed from the multi-chamber processing system 500 and exposed to air. It may be configured to perform a sequential hydrogenation/nitridation process or a single-step plasma hydrogenation and nitridation process. As discussed above, nitridation of the exposed surface of the metal nitride layer 103 prior to atmospheric destruction can greatly reduce oxidation of the exposed surface during atmospheric destruction and during a subsequent thermal annealing process.

In some embodiments, multi-chamber processing system 500 may include one or more thermal annealing and plasma processing chambers. In such embodiments, a sequential hydrogenation and nitridation process or a single step plasma hydrogenation and nitridation process may be performed after the thermal annealing process, thereby removing O atoms introduced by atmospheric destruction prior to the annealing and by the thermal annealing process itself. Remove. Typically, thermal annealing processes work on most advanced device nodes due to the high temperatures that processing components (eg, seals, process kit components, pumps, etc.) achieve during thermal treatment. cannot maintain the desirably low oxygen levels required for

Alternatively or additionally, a sequential hydrogenation/nitridation process or a single step plasma hydrogenation and nitridation process may be performed prior to the thermal annealing process. Thus, in such embodiments, the interfacial O atoms and O atoms present in the bulk portion of the metal nitride layer 103 are subjected to thermal annealing, even if atmospheric breakdown does not occur after deposition of the metal nitride layer and prior to the thermal annealing process. It can be reduced or eliminated prior to performing the process. Therefore, in some configurations, a sequential hydrogenation and plasma nitridation process or a single step plasma hydrogenation and nitridation process may be performed before the thermal annealing process and also after the thermal annealing process but before atmospheric breakdown occurs.

In some embodiments, multi-chamber processing system 500 includes one or more metal deposition chambers configured to deposit capping layer 104 and/or conductive layer 106, and a sequential hydrogenation and nitridation process or single step plasma hydrogenation and It may include one or more plasma processing chambers for performing the nitridation process. In such embodiments, a sequential hydrogenation and nitridation process or a single step plasma hydrogenation and nitridation process may be performed prior to deposition of the capping layer in the conductive structure, thereby forming silicide 105 and by atmospheric breakdowns. Remove the interfacial and bulk O atoms introduced by a thermal annealing process to Note that in such embodiments, no atmospheric breakdown occurs between the sequential hydrogenation and nitridation process and the deposition of capping layer 104 and/or conductive layer 106 . Accordingly, in such embodiments, interfacial O atoms and O atoms present in the bulk portion of the metal nitride layer may be reduced or eliminated when atmospheric breakdown occurs between the thermal annealing process and the deposition of the capping layer 104 .

Reduction of bulk and interfacial oxygen in the contact structure

6 presents a flow diagram of process steps for reducing bulk and interfacial oxygen of a contact structure, in accordance with some embodiments of the present disclosure. 7A-7E are schematic cross-sectional views of a semiconductor device corresponding to different stages of the process of FIG. 6, in accordance with various embodiments of the present disclosure. 7A-7E illustrate that first metal layer 102, metal nitride layer 103, and capping layer 104, which fill aperture 109, are selectively deposited (e.g., the layers are not conformally formed over aperture 109 as shown at 1), which is not intended to limit the scope of the disclosure set forth herein and, therefore, first metal layer 102, metal nitride layer 103 and capping layer 104 may be selectively or non-selectively formed and may include one or more additional layers.

Prior to step 601, a cleaning process or other surface preparation process may be performed on the surface of the semiconductor substrate on which contacts are to be formed, such as exposed surface 701 of source or drain structure 101 in FIG. 7A. . In some embodiments, a dry etch process may be performed to remove native oxide on surface 701 . For example, a conventional plasma etch, ^{or a remote plasma assisted dry etch process, such as the SiCoNi™ etch} process available from Applied Materials, Inc. of Santa Clara, Calif., may be performed. there is. In the Cicony ^™ etch process, the surface of the semiconductor substrate on which contacts are to be formed is exposed to H ₂ , NF ₃ , and/or NH ₃ plasma species, such as plasma excited hydrogen and fluorine species. For example, in some embodiments, such a surface can undergo simultaneous exposure to H ₂ , NF ₃ , and NH ₃ plasma. The Cicony ^TM etch process can be performed in a Cicony ^TM pre- ^clean chamber, which is one of a variety of multi-processing platforms including the Producer ^TM GT, Centura ^TM AP ^, and Endura platforms. can be incorporated into, all of which are available from Applied Materials.

Method 600 begins at step 601 where a first metal layer 102 and a metal nitride layer 103 are deposited on a semiconductor substrate, as shown in FIG. 7B. For example, in some embodiments, a Ti layer is deposited followed by a TiN barrier layer. Any suitable PVD, CVD, or ALD process may be employed to perform such deposition. Accordingly, the deposition process may be a selective process or a non-selective deposition process. In a selective deposition process, the first metal layer 102 and the metal nitride layer 103 are deposited on the surface 701 and not other surfaces of the semiconductor substrate 110, whereas in a non-selective process, the first metal layer ( 102) and metal nitride layer 103 may be deposited on all unmasked surfaces of the semiconductor substrate 110. In some embodiments, the deposition of step 601 is performed without atmospheric breakdown after the surface preparation process described above. That is, the semiconductor substrate is not exposed to the atmosphere between the surface preparation process and the deposition of step 601 . In such embodiments, the deposition and surface preparation processes of step 601 may each be performed by different chambers on the same multi-chamber processing system, eg, multi-chamber processing system 500 .

At step 603 , a thermal annealing process is performed on the semiconductor substrate 110 including the first metal layer 102 , the metal nitride layer 103 , and the source or drain structure 101 . The thermal annealing process forms silicide 105 as shown in FIG. 7C. For example, in some embodiments, a spike annealing process may be performed at step 603 to reach a peak temperature that is between about 500 °C and about 600 °C. Alternatively, any other suitable annealing process may be performed instead to form a silicide 105 between the source or drain structure 101 and the first metal layer 102 deposited in step 601 .

In some embodiments, the chamber for performing step 603 can be configured as the chamber of the same multi-chamber processing system in which the metal deposition of step 601 is performed. Accordingly, in such embodiments, the thermal annealing process of step 603 is performed without atmospheric breakdown after the metal deposition of step 601, whereby the interface present on the surface 702 of the metal nitride layer 103 further reduce O. However, such a configuration of a multi-chamber processing system is rare for the reasons discussed above, and typically atmospheric breakdown occurs between steps 601 and 603.

At step 604 , a sequential hydrogenation/plasma nitridation process is performed on the surface 702 of the metal nitride layer 103 . That is, surface 702 is exposed to hydrogen atoms and plasma excited nitrogen species 703, as shown in FIG. 7D. In some embodiments, the plasma hydrogenation process is followed by a plasma nitridation process at step 604 . In embodiments where the hydrogenation process is a plasma hydrogenation process, both the plasma hydrogenation process and the plasma nitridation process may be performed in processing chamber 400 using the process parameters described above in conjunction with FIG. 4 . Alternatively, the plasma hydrogen process can be performed in one of the process chambers 514, 516, 518, 520, 522, and 524 of the multi-chamber processing system 500, while the plasma nitridation process can be performed in the process chambers ( 514, 516, 518, 520, 522, and 524) may be performed in other chambers.

As previously mentioned, in some embodiments, surface 702 of metal nitride layer 103 is exposed to hydrogen atoms through a thermal hydrogenation process. In such embodiments, the thermal hydrogenation process of step 604 is performed in one of processing chambers 514, 516, 518, 520, 522, and 524 of multi-chamber processing system 500, e.g., as a process gas. It is performed in a rapid heat treatment chamber configured to use H ₂ gas. Further, in such embodiments, the plasma nitridation process is performed in another one of processing chambers 514, 516, 518, 520, 522, and 524, e.g., a processing chamber similar to plasma processing chamber 400 of FIG. do. Therefore, even if the thermal hydrogenation process and the plasma nitridation process are respectively performed in different processing chambers, no atmospheric breakdown occurs between these two processes.

In step 605, a capping layer 104 is deposited over the annealed first metal layer 102 and metal nitride layer 103, as shown in FIG. 7E. For example, in one embodiment, the metal capping layer is a Co layer or a layer of a cobalt containing alloy. Because interfacial O atoms that may be present on the surface 702 of the metal nitride layer 103 are removed during step 604, adhesion between the capping layer 104 and the metal nitride layer 103 is achieved through conventional techniques. It is improved compared to adhesion in formed contact structures. Also, removal of the O atoms in the metal nitride layer 103 reduces the electrical resistivity of the conductive structure 100 .

In some embodiments, steps 604 and 605 are performed on the same multi-chamber processing system so that no atmospheric breakdown occurs after the sequential hydrogenation and nitridation processes of step 604. As a result, oxidation of the metal nitride layer 103 that may occur during exposure to the atmosphere is avoided. In other embodiments, the process chamber for performing the sequential hydrogenation and nitridation process of step 604 may be configured on a different multi-chamber processing system than the process chamber for performing step 605 . In such embodiments, the nitridation process of step 604 completely nitrides the surface of the metal nitride layer 103, thereby minimizing oxidation that may occur during atmospheric breakdown between steps 604 and 605 or otherwise. Note that this is prevented in a way.

8 presents a flow diagram of process steps for reducing bulk and interfacial oxygen of a contact structure, in accordance with some embodiments of the present disclosure. Prior to step 801 , a cleaning process or other surface preparation process may be performed as described above in conjunction with FIG. 7 .

Method 800 begins at step 801 where a metal layer 102 and a metal nitride layer 103 are deposited over a source or drain structure 101 . Step 801 may be substantially similar to step 601 of method 600 .

At step 802 , a sequential hydrogenation/plasma nitridation process is performed on the surface 702 of the metal nitride layer 103 . That is, surface 702 is exposed to hydrogen atoms and plasma excited nitrogen species. Step 802 may be substantially similar to step 604 of method 600 . Note, however, that unlike step 604, the sequential hydrogenation/plasma nitridation process of step 802 is performed prior to the thermal annealing process. Further, in some embodiments, step 802 is performed in a chamber configured to be part of a multi-chamber processing system that includes a thermal anneal chamber for performing step 803, eg, a rapid thermal processing chamber. In such embodiments, the effect of the O atoms in the first metal layer 102 and metal nitride layer 103 deposited in step 801 is further reduced, since such O atoms may be removed prior to the annealing process in step 803. because it is removed.

In step 803 , a thermal annealing process is performed on the semiconductor substrate 110 including the first metal layer 102 , the metal nitride layer 103 , and the source or drain structure 101 . Step 803 may be substantially similar to step 603 of method 600 . Alternatively, in embodiments where a thermal hydrogenation process occurs in step 802, a thermal annealing process may be performed in step 802 and step 803 may be omitted. For example, in some embodiments, the thermal annealing process in which silicide 105 is formed is performed in the same processing chamber as the thermal hydrogenation process of step 802 . In such embodiments, the thermal annealing process may be performed simultaneously with the thermal hydrogenation process, immediately prior to the thermal hydrogenation process, or immediately after the thermal hydrogenation process.

In optional step 804, a plasma treatment process is performed on the surface 702 of the metal nitride layer 103. Step 804 may be substantially similar to step 604 of method 600 . Accordingly, in embodiments of method 800 in which step 804 is performed, a sequential hydrogenation/nitridation process is performed before and after the thermal annealing process of step 803. In some embodiments, the sequential hydrogenation/nitridation process performed at step 804 is substantially the same as the plasma treatment process performed at step 802 . In other embodiments, the sequential hydrogenation/nitridation process of step 804 may be different from the sequential hydrogenation/nitridation process of step 802 . For example, the process parameters of the sequential hydrogenation/nitridation process employed in step 802 may be different from the process parameters of the sequential hydrogenation/nitridation process employed in step 804.

In step 805 , capping layer 104 and/or conductive layer 106 is deposited over annealed first metal layer 102 and metal nitride layer 103 . Step 805 may be substantially similar to step 605 of method 600 . Similarly, in some embodiments, steps 804 and 805 can be performed on the same multi-chamber processing system so that atmospheric breakdown does not occur after the plasma treatment process of step 804. As a result, oxidation of the metal nitride layer 103 that may occur during exposure to air is avoided, and adhesion between the capping layer 104 and the metal nitride layer 103 is maintained in contact structures formed through conventional techniques. improved compared to adhesion.

9 presents a flow diagram of process steps for reducing bulk and interfacial oxygen of a contact structure, in accordance with some embodiments of the present disclosure. Prior to step 901 , a cleaning process or other surface preparation process may be performed as described above in conjunction with method 600 . As shown, the method 900 begins at step 901 where a first metal layer 102 and a metal nitride layer 103 are deposited over a source or drain structure 101 . Step 901 may be substantially similar to step 601 of method 600 . At step 902 , a sequential hydrogenation/nitride process is performed on the surface 702 of the metal nitride layer 103 . Step 902 may be substantially similar to step 802 of method 800 . In step 903 , a thermal annealing process is performed on the semiconductor substrate 110 including the first metal layer 102 , the metal nitride layer 103 , and the source or drain structure 101 . Step 903 may be substantially similar to step 603 of method 600 . In step 905 , a capping layer 104 is deposited over the annealed first metal layer 102 and metal nitride layer 103 . Step 905 may be substantially similar to step 605 of method 600 . Thus, in method 900, a sequential hydrogenation/nitridation process is performed prior to the thermal annealing process of step 903, but not after the thermal annealing process of step 903. Sequential hydrogenation/nitridation processes generally include plasma or thermal hydrogenation processes and plasma nitridation processes.

Although methods 600 and 800 are described for forming contact structures on a substrate, methods 600 and 800 may also be employed to form other conductive structures on a substrate. Accordingly, any conductive structure comprising a metal nitride layer can benefit from being formed by method 600 or 800.

Metal gate structure with reduced EOT

According to various embodiments of the present disclosure, a sequential hydrogenation and nitridation process is employed in the fabrication of a high-k dielectric/metal gate stack to reduce the effective oxide thickness (EOT) of the stack. In such embodiments, the EOT of the stack is a concomitant trade-off of increased leakage and flatband voltage shift known to occur when the high-k dielectric layer of the stack is simply reduced in thickness or otherwise scaled through conventional techniques. reduced regardless of One such stack is illustrated in FIG. 10 .

10 illustrates a cross-sectional view of a metal gate structure 1000 formed in accordance with an embodiment of the present disclosure. The metal gate structure 1000 is formed on the semiconductor substrate 1001 as part of a semiconductor device, eg, a MOSFET or other FET. The metal gate structure 1000 is a stack of a plurality of material layers formed on a semiconductor substrate 1001, for example, an interfacial layer 1002 disposed on the semiconductor substrate 1001, an interfacial layer 1002 disposed on the A high-k dielectric layer (1003) disposed on the high-k dielectric layer (1003), a metal nitride capping layer (1004) disposed on, and a metal gate electrode layer (1005) disposed on the metal nitride capping layer (1004). includes In the embodiment illustrated in FIG. 10 , the various layers of metal gate structure 1000 are shown as a simple film stack formed on a semiconductor substrate 1001 . In practice, metal gate structure 1000 may be formed in a contact well or other cavity formed of an insulating or dielectric material similar to insulating material 120 of FIG. 1 . Accordingly, one or more of interfacial layer 1002, high-k dielectric layer 1003, metal nitride capping layer 1004, and metal gate electrode layer 1005 may be material layers conformally deposited within such cavity.

Semiconductor substrate 1001 may be any suitable semiconductor substrate on which metal gate structure 1000 may be formed. Thus, the semiconductor substrate 1001 is Si (Si), Ge (germanium), silicon-germanium (Si-Ge), silicon-germanium-carbon (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), and any other III/V or II/VI compound semiconductors. Alternatively or additionally, the semiconductor substrate 1001 may be a layered semiconductor such as, for example, Si/Si-Ge, Semiconductor on Insulator (SOI) or Si-Ge on Insulator (SiGOI). Additionally, in some embodiments, the semiconductor substrate 1001 includes doped and/or undoped regions proximate to the interfacial oxide layer 1002, eg, n-doped or p-doped regions.

The interfacial oxide layer 1002 is disposed on the semiconductor substrate 1001, between the semiconductor substrate 1001 and the high-k dielectric layer 1003, and is configured as an interfacial oxide layer suitable for application in metal gate structures 1000. . In embodiments where the semiconductor substrate 1001 comprises a Si-containing material, the interfacial oxide 1002 layer may be silicon oxide (SiO _X ), silicon oxynitride (SiNO, Si ₂ NO, Si ₂ N ₂ O), and/or nitrated silicon oxide. In embodiments where the semiconductor substrate 1001 is other than a Si-containing semiconductor material, the interfacial oxide layer 1002 may include a semiconductor oxide, semiconducting oxynitride and/or nitrated semiconducting oxide.

Interfacial oxide layer 1002 may be formed via any suitable thermal or wet growth technique, such as oxidation or oxynitridation. For example, without limitation, the interfacial oxide layer 1002 can be formed by a wet chemical oxidation process comprising treating a cleaned surface of the semiconductor substrate 1001, e.g., a HF final treated semiconductor surface, with a mixture of ammonium hydroxide, hydrogen peroxide and water. can be formed by Alternatively, the interfacial oxide layer 1002 can be formed by treating an HF finished semiconductor surface in ozonized aqueous solutions. Alternatively, interfacial oxide layer 1002 may be formed by any suitable thermal oxidation technique.

The thickness of the interfacial oxide layer 1002 is a function of the semiconductor device of which the metal gate structure 1000 is a part. Additionally, interfacial oxide layer 1002 is significantly thinner than high-k dielectric layer 1003 , metal nitride capping layer 1004 , and metal gate electrode layer 1005 . Typically, the interfacial oxide layer 1002 has a thickness of about 0.5 to 2.0 nm, but in some embodiments the interfacial oxide layer 1002 may be thicker. In some embodiments, thermal processes for device fabrication that occur subsequent to formation of metal gate structure 1000 may further increase the thickness of interfacial oxide layer 1002 .

The high-k dielectric layer 1003 may be the gate dielectric layer of the metal gate structure 1000 or another dielectric layer and includes a so-called “high-k dielectric” material. More specifically, high-k dielectric layer 1003 includes one or more materials having a dielectric constant greater than that of SiO ₂ , such as materials having a dielectric constant of at least about 4.0, or ideally at least about 10.0. do. Additionally, the high-k dielectric material included in the high-k dielectric layer 1003 is suitable for use in integrated circuits. Thus, in addition to the high dielectric constant, the one or more high-k dielectric materials included in the high-k dielectric layer 1003 also ideally have a small number of electrical properties that can compromise the ability to prevent diffusion of dopants, breakdown performance. defects, good thermal stability, and high recrystallization temperature. Examples of such high-k dielectric materials suitable for use in high-k dielectric layer 1003 include, without limitation, silicon nitride, silicon oxynitride, metal oxides, metal nitrides, metal oxynitrides and/or metal silicates. do. In some embodiments, the high-k dielectric layer 1003 is hafnium oxide (Hf _x O _y ), zirconium oxide (ZrO ₂ ), hafnium silicate oxides (Hf _x Si _1-x O _y ) or other hafnium-based dielectric lanthanum oxides (La ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), strontium titanate (SrTiO ₃ ), lanthanum aluminate (LaAlO ₃ ), yttrium oxide (Y ₂ O ₃ ), hafnium silicate oxides (Hf _x Si _1-x O _y ), lanthanum oxides (La ₂ O ₃ ), and/or one or more of multilayer stacks thereof.

The high-k dielectric layer 1003 may be formed through any suitable deposition method including a thermal growth process such as, for example, an oxidation, nitridation or oxynitride process. Alternatively, the high-k dielectric layer 1003 may be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), evaporation, reactive sputtering, It may be formed by one or more deposition processes, including but not limited to chemical solution deposition and/or any combination thereof.

The thickness 1003A of the high-k dielectric layer 1003 is determined by the dielectric material included in the layer, the process used to form the high-k dielectric layer 1003, and the semiconductor device including the metal gate structure 1000. may vary depending on the geometry and operation of In some embodiments, the thickness 1003A of the high-k dielectric layer 1003 is between about 1.0 nm and about 20 nm.

The metal nitride capping layer 1004 is a metal layer disposed on the high-k dielectric layer 1003 that is typically configured as an electrically conductive protection layer on the high-k dielectric layer 1003 . Thus, in some embodiments, metal nitride capping layer 1004 is configured to prevent unwanted oxidation of semiconductor substrate 1001 and/or high-k dielectric layer 1003 . Additionally, in such embodiments, the metal nitride capping layer 1004 is also configured to allow diffusion of oxygen from the high-k dielectric layer 1003 during a thermal annealing process that occurs after deposition of the metal nitride capping layer 1004. It can be. In such embodiments, the metal nitride capping layer 1004 also diffuses oxygen from the interfacial layer 1009 formed between the high-k dielectric layer 1003 and the metal nitride capping layer 1004 during the thermal annealing process. can be configured to allow

In some embodiments, the metal nitride capping layer 1004 includes a metal nitride, such as TiN, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), or the like. In some embodiments, the deposition of the nitride capping layer 1004 on the high-k dielectric layer 1003 is the interfacial layer 1009 disposed at the interface between the high-k dielectric layer 1003 and the metal nitride capping layer 1004. ) can result in the formation of According to some embodiments, the interfacial layer 1009 is subsequently removed or reduced in thickness when a sequential plasma hydrogenation and nitridation process is applied to the exposed surface of the metal nitride capping layer 1004, as described herein. do.

The metal nitride capping layer 1004 can be formed by any suitable deposition method, including but not limited to a PVD process, CVD process, PECVD process, MOCVD process, ALD evaporation process, reactive sputtering, chemical solution deposition, and/or any combination thereof. can be formed through

In some embodiments, the metal nitride capping layer 1004 is significantly thinner than the high-k dielectric layer 1003 and the metal gate electrode layer 1005 . For example, high-k dielectric layer 1003 is a HfO ₂ layer having a thickness 1003A of about 20 nm to about 40 nm, and metal gate electrode layer 1005 having a thickness of about 20 nm to about 40 nm. In an embodiment of the metal gate structure 1000 that is a TiN layer having a thickness, the metal nitride capping layer 1004 may have a thickness 1004A of about 5 nm to about 15 nm.

In some embodiments, the thickness 1004A of the metal nitride capping layer 1004 is selected to facilitate diffusion of oxygen atoms from the high-k dielectric layer 1003 and/or interfacial layer 1009 . Specifically, in such embodiments, thickness 1004A is such that O atoms are removed from high-k dielectric layer 1003 and/or interfacial layer 1009 during a thermal annealing process that occurs after deposition of metal nitride capping layer 1004. selected to spread. In such embodiments, the thickness 1004A is selected to be less than the diffusion length of O atoms through the metal nitride capping layer 1004 during the thermal annealing process. In one example, one such thermal anneal process is a spike anneal process performed on the metal gate structure 1000 for a duration of 1-2 seconds and a peak temperature of about 700 to about 900 degrees Celsius.

The metal gate electrode layer 1005 is a metal layer formed on the metal nitride capping layer 1004 and includes one or more deposited metal layers. In some embodiments, metal gate electrode layer 1005 is configured as a gate electrode and/or work function metal of metal gate structure 1000 . In such embodiments, the one or more metal layers included in the metal gate electrode layer 1005 are collective gate electrodes that facilitate operation of the metal gate structure 1000 and of the semiconductor device in which the metal gate structure 1000 is incorporated. It is selected to have a work function value. The metal gate electrode 1005 may be formed via any suitable deposition method, including but not limited to CVD, PECVD, MOCVD, ALD, evaporation, reactive sputtering, chemical solution deposition, and/or any combination thereof. .

In some embodiments, the metal gate electrode layer 1005 is a p-metal gate material, such as TiN. Alternatively, in some embodiments, metal gate electrode layer 1005 is an n-metal gate. Suitable n-metals for use in the metal gate electrode layer 1005 include titanium aluminum carbide (Ti _x AlC).

Formation of metal gate structures with reduced EOT

During fabrication of metal gate structure 1000 , a sequential plasma hydrogenation and nitridation process is performed on metal nitride capping layer 1004 prior to deposition of metal gate electrode layer 1005 , according to various embodiments. In such embodiments, the EOT of the metal gate structure 1000 is reduced while the leakage current of the metal gate structure 1000 is increased to a less than expected magnitude. Also, in such embodiments, the metal gate structure 1000 exhibits little or no flatband voltage shift normally associated with reduced EOT.

For example, in one embodiment of the metal gate structure 1000, the interfacial oxide layer 1002 has a thickness of about 1-2 nm, and the high-k dielectric layer 1003 has a thickness of about 2-3 nm ( 1003A), and the metal nitride capping layer 1004 has a thickness 1004A of about 3-4 nm. In such an embodiment, one measurable effect of treating the metal nitride capping layer 1004 with the sequential plasma hydrogenation and nitridation process described herein is to reduce the measured EOT of the metal gate structure 1000 by approximately 1 Å (i.e. , from about 9 Å to about 8 Å). Another effect of such a treatment of the metal nitride capping layer 1004 is about 2.4 times (ie, from about 0.268 A/cm ² to about .658 A/cm ² ) (at a flatband voltage of -1 V). is the increase in leakage current. In contrast, according to well-established scaling trends known in the art, the EOT of metal gate structure 1000 is, instead, by conventional techniques, scaling thickness 1003A by about 1 Å, for example. When reduced by , the leakage current is expected to increase by approximately 10 times. Thus, treatment of the metal nitride capping layer 1004 using the sequential plasma hydrogenation and nitridation process described herein, as associated with simply scaling the thickness 1004A of the metal nitride capping layer 1004, increases leakage current. It has been found that has the effect of reducing the EOT of the metal gate structure 1000 by approximately 1/4 of .

Further, the flatband voltage shift measured at the metal gate structure 1000 remains substantially constant when the metal gate structure 1000 is formed in a sequential plasma hydrogenation and nitridation process, despite the reduction in EOT described above. appeared to be Thus, application of a sequential plasma hydrogenation and nitridation process to the metal nitride capping layer 1004 allows fabrication of a metal gate structure 1000 with reduced EOT without flatband voltage shift and without consequential impact on device design. make it possible

11 presents a flow diagram of process steps for reducing the EOT of a metal gate structure, in accordance with various embodiments of the present disclosure. 12A-12J are schematic cross-sectional views of a semiconductor device corresponding to different stages of the process of FIG. 11, in accordance with various embodiments of the present disclosure.

Method 1100 begins at step 1101 where a high-k dielectric layer 1003 is deposited over an interfacial oxide layer 1002 as shown in FIG. 12A. High-k dielectric layer 1003 may be formed via any suitable deposition method described above in conjunction with FIG. 10 .

In step 1102, a metal nitride capping layer 1004 is deposited over the high-k dielectric layer 1003, as shown in FIG. 12B. The metal nitride capping layer 1004 may be formed via any suitable deposition method described above in conjunction with FIG. 10 . In some embodiments, the deposition of the metal nitride capping layer 1004 results in the formation of an interfacial layer 1009 disposed at the interface between the high-k dielectric layer 1003 and the metal nitride capping layer 1004 . In such embodiments, the interfacial layer 1009 generally contains O atoms and/or voids (voids in FIG. 2A) incorporated by contaminants present in the processing environment during the deposition process of step 1102. (213)).

In optional step 1103, exposed surface 1201 shown in FIG. 12B is exposed to air. For example, in some embodiments, the metal nitride capping layer 1004 is deposited in one processing system, such as the multi-chamber processing system 500 of FIG. 5 , while the next step performed on the semiconductor substrate 1001 The processing steps are performed in different processing systems. Accordingly, in such embodiments, the semiconductor substrate 1001 is exposed to air after deposition of the metal nitride layer 1004. In embodiments where the metal nitride capping layer 1004 is deposited in one chamber of a multi-chamber processing system and step 1104 is performed in one or two other processing chambers of the same multi-chamber processing system, an optional step ( 1103) is not performed.

In embodiments where the metal nitride capping layer 1004 deposited in step 1102 is a sacrificial metal nitride layer that is subsequently removed, the method 1100 proceeds to step 1131 . In embodiments where the metal nitride capping layer 1004 deposited in step 1102 remains on the metal gate structure 1000, the method 1100 proceeds to step 1104. In some embodiments, the sacrificial metal nitride layer may be removed by use of a subsequent wet or dry etch process optional to the removal of the metal nitride capping layer 1004 .

In step 1104, a sequential plasma hydrogenation and nitridation process is performed on the surface 1201 of the metal nitride capping layer 1004, as shown in FIG. 12C. The plasma hydrogenation and nitridation process may be substantially similar to the plasma hydrogenation and nitridation process described above in conjunction with FIG. 4 . Further, the plasma hydrogenation process includes non-oxidizing plasma excited hydrogen species and does not include any oxidizing plasma excited hydrogen species.

In some embodiments, the plasma hydrogenation process of step 1104 is performed at a chamber pressure of about 20 mTorr to about 100 mTorr, for a duration of about 30 seconds to about 150 seconds, and at a processing temperature of about 400° C. to about 500° C. (eg, , substrate pedestal temperature), an RF power of about 500 W to about 1500 W, a flow rate of H ₂ of about 20 sccm to about 100 sccm, and a flow rate of Ar of about 900 sccm to about 980 sccm. In some embodiments, the flow rate of H ₂ is between about 1% and about 15% of the total process gases introduced into the chamber. In some embodiments, the plasma hydrogenation process of step 1104 is performed at a process temperature of about 425 °C to about 475 °C, at a chamber pressure of about 45 mTorr to about 55 mTorr, for a duration of about 85 seconds to about 95 seconds, RF power of about 700 W to about 800 W, a flow rate of H ₂ of about 45 sccm to about 55 sccm, and a flow rate of Ar of about 965 sccm to about 955 sccm.

In some embodiments, the plasma nitridation process of step 1104 is performed at a process temperature of about 400 °C to about 500 °C, at a chamber pressure of about 10 mTorr to about 50 mTorr, for a duration of about 30 seconds to about 150 seconds, RF power from about 500 W to about 1500 W, a flow rate of NH ₃ from about 1% to about 10% of the total process gas flow rate, a flow rate of N ₂ from about 45% to about 55% of the total process gas flow rate, and a process gas It is carried out with a flow rate of Ar selected to be equal to the rest of the flow. In some embodiments, the plasma nitridation process of step 1104 is performed at a process temperature of about 425 °C to about 475 °C, at a chamber pressure of about 15 mTorr to about 25 mTorr, for a duration of about 85 seconds to about 95 seconds, RF power of about 700 W to about 800 W, a flow rate of NH _{3 from about 2% to about 3% of the total process gas flow rate, a flow rate of N 2 from} about 45% to about 55% of the total process gas flow rate, and a process gas It is carried out with a flow rate of Ar selected to be equal to the rest of the flow.

In summary, at step 1104, surface 1201 is exposed to plasma excited hydrogen species generated in a plasma hydrogenation process, and some or all of the oxides present on surface 1201 are reduced. Additionally, in some embodiments, such plasma excited hydrogen species may also reduce some or all of the oxygen (O) atoms present in the bulk material of the metal nitride capping layer 1004 . Also, at step 1104, surface 1201 is exposed to plasma excited nitrogen species generated in a plasma nitridation process, thereby saturating surface 1201 with N atoms and, in some embodiments, metal. Voids present in the bulk material of the nitride capping layer 1004 are filled with N atoms. Thus, in some embodiments, as shown in FIG. 12D , the interfacial layer 1009 is removed or significantly reduced.

In some embodiments, the plasma hydrogenation process of step 1104 is performed in the same processing chamber as the plasma nitridation process of step 1104, eg, process chamber 400 of FIG. Alternatively, the plasma hydrogenation process of step 1104 is performed in a first process chamber of a multi-chamber processing system, while the plasma nitridation process of step 1104 is performed in a second process chamber of the same multi-chamber processing system. In either case, note that surface 1201 is not exposed to air between the plasma hydrogenation and plasma nitridation processes of step 1104 . Thus, in either embodiment, surface 1201 is not exposed to air after exposure to plasma excited hydrogen species and before exposure to plasma excited nitrogen species.

In some embodiments, an anoxic conditioning process is performed in the process chamber prior to performing the plasma hydrogenation process in the process chamber, eg, to reduce trace oxygen contaminants in the process chamber. In such embodiments, the processing chamber is treated with an oxygen-free plasma before the substrate is processed through the plasma hydrogenation process described above, with no substrate placed in the chamber. Such plasma treatment of a process chamber prior to introduction of a substrate into the chamber is often referred to as a plasma wafer-by-wafer (PEW) process or PEW treatment.

In some embodiments, such a PEW process involves introducing one or more oxygen-free gases, such as N ₂ , NH ₃ , Ar, H ₂ , or any suitable combination thereof, into the process chamber, and oxygen-free gases. and activating one or more gases to form a plasma. Alternatively, the PEW process may include introducing plasma containing radicals and/or ions of N, H, or NH ₃ , or any suitable combination thereof, into the process chamber, where the plasma is outside the process chamber. is formed at a remote plasma source of In one embodiment, NH ₃ gas or a combination of NH ₃ and Ar gases is introduced into the process chamber. In another embodiment, H ₂ gas or a combination of H ₂ and Ar gases is introduced into the process chamber. In another embodiment, N ₂ gas or a combination of N ₂ and Ar gases is introduced into the process chamber.

Typically, plasma treatment of a processing chamber prior to introduction of a substrate involves forming or introducing a plasma containing hydrogen and/or nitrogen into the process chamber. In some embodiments, radicals generated from plasma inside the processing chamber during the PEW process, eg, N ^* , NH ^* , and/or H ^*, react with trace O atoms within the processing chamber.

In some embodiments, during the PEW process, one or more gases introduced into the processing chamber are activated by an RF power source, such as RF power source 414 in FIG. 4 . The RF power may be pulsed with a 2% to 70% duty cycle and may range from about 100 W to about 2500 W. The RF power can range from about 100 W to about 2500 W continuous wave. In such embodiments, the PEW process of step 1104 is performed at a chamber pressure of about 10 mTorr to about 200 mTorr, at a process temperature of about 400 °C to about 500 °C, for a duration of about 20 seconds to about 100 seconds, at about RF power of 250 W to about 750 W, a flow rate of H ₂ of about 50 sccm to about 200 sccm, and a flow rate of O ₂ of about 450 sccm to about 550 sccm.

In optional step 1105, exposed surface 1201 is exposed to air. For example, in some embodiments, the sequential hydrogenation and nitridation process described above is performed in one processing system, while the next processing step to be performed on the semiconductor substrate 1001 is performed in a different processing system. Accordingly, in such embodiments, the semiconductor substrate 1001 is exposed to air after deposition of the metal nitride layer 1004. In embodiments where the sequential hydrogenation and nitridation process is performed in one chamber of a multi-chamber processing system and step 1106 is performed in another process chamber of the same multi-chamber processing system, optional step 1105 is not performed.

In embodiments in which a sacrificial silicon-containing layer is subsequently deposited and removed as part of the formation of metal gate structure 1000, method 1100 proceeds from step 1105 to step 1121. In embodiments in which a sacrificial silicon layer is not deposited in forming the metal gate structure 1000, the method 1100 proceeds to step 1106. The sacrificial silicon-containing layer may be formed using a CVD or ALD process that uses one or more silicon-containing precursor gases to form the deposited layer.

At step 1106, a thermal annealing process, e.g., post-cap annealing, is performed on the semiconductor substrate 1001, interfacial layer 1002, high-k dielectric layer 1003, and metal nitride capping layer 1004. . For example, in some embodiments, a spike annealing process is performed at step 1106 to reach a peak temperature of about 600-900 °C. A post-cap annealing is performed on the partially formed metal gate structure 1000 to smooth the interface, restore unsaturated bonds, and inject thermal energy into the metal nitride capping layer.

In step 1107, a metal gate electrode layer 1005 is deposited on the processed metal nitride capping layer 1004, as shown in FIG. 12E, thereby completing the formation of the metal gate structure 1000. . Metal gate electrode 1005 may be formed via any suitable deposition method described above in conjunction with FIG. 10 .

In step 1121, a sacrificial silicon layer 1202 is deposited over the metal nitride capping layer 1004, as shown in FIG. 12F. Step 1121 is performed after the surface 1201 of the metal nitride capping layer 1004 has been treated by the sequential plasma hydrogenation and nitridation process of step 1104 and optional air exposure of step 1105 .

The sacrificial silicon layer 1202 may include any suitable silicon-containing material, such as amorphous silicon, and may be deposited using any suitable deposition process known in the art, such as a CVD process. The sacrificial silicon layer 1202 is formed by the metal nitride capping layer 1004, the interfacial layer 1009 (if still present), and the high-k dielectric layer 1003 during a subsequent thermal annealing process, e.g., a so-called post-cap annealing process. ) is deposited on the metal nitride capping layer 1004 to reduce the formation of oxides in . In some embodiments, the post-cap annealing process includes an air thermal annealing process. As a result, additional oxidation of the very thin layers of the metal gate structure 1000, including the interfacial layer 1002, the high-k dielectric layer 1003, and the metal nitride capping layer 1004, may occur, whereby , increases the EOT of the metal gate structure 1000. However, the presence of the sacrificial silicon layer 1202 may shield the layers of the metal gate structure 1000 from atmospheric O atoms during the pre-cap annealing process. Additionally, the sacrificial silicon layer 1202 interacts with O atoms that diffuse from the high-k dielectric layer 1003, the interfacial layer 1009 (if still present), and the metal nitride capping layer 1004 during the thermal annealing process. can react, thereby retaining the O atoms. Thus, the sacrificial silicon layer 1202 minimizes or eliminates the potential for unwanted oxidation of portions of the metal gate structure 1000 during a subsequent thermal annealing process.

In step 1122, a thermal annealing process, e.g., post-cap annealing, is performed on the semiconductor substrate 1001, the interfacial layer 1002, the high-k dielectric layer 1003, the metal nitride capping layer 1004, and the sacrificial silicon layer. 1202 is performed. The thermal annealing process of step 1122 may be substantially similar to the thermal annealing process of step 1106, described above.

At step 1123 , the sacrificial silicon layer 1202 is removed from the metal gate structure 1000 . Any technically feasible removal process may be employed at step 1123 and may include a selective wet etch process, a plasma based dry etch process, a chemical mechanical polishing process, or any combination thereof. Method 1100 then proceeds to step 1107, where the final layer of metal gate structure 1000 is deposited.

In step 1131, a sacrificial silicon layer 1203 is deposited over the metal nitride capping layer 1004, as shown in FIG. 12G. Sacrificial silicon layer 1203 may be substantially similar to sacrificial silicon layer 1202 deposited in step 1131 . Note, however, that in step 1131, the metal nitride capping layer 1004 has not been treated with a sequential plasma hydrogenation and nitridation process. Consequently, the metal nitride capping layer 1004 may still include the interfacial layer 1009 as shown.

In step 1132, a thermal annealing process, e.g., post-cap annealing, is performed on the semiconductor substrate 1001, interfacial layer 1002, high-k dielectric layer 1003, metal nitride capping layer 1004, interfacial layer 1009. ), and the sacrificial silicon layer 1203. The thermal annealing process of step 1132 may be substantially similar to the thermal annealing process of step 1106, described above.

In step 1133, sacrificial silicon layer 1203, metal nitride capping layer 1004 and interfacial layer 1009 are removed from metal gate structure 1000, as shown in FIG. 12H. Any technically feasible removal process or combination of processes may be employed in step 1123 and may include a selective wet etch process, a plasma-based dry etch process, a chemical mechanical polishing process, or any combination thereof. . Method 1100 then proceeds to step 1134 .

In step 1134, a final metal nitride capping layer 1204 is deposited over the high-k dielectric layer 1003, as shown in FIG. 12I. The final metal nitride capping layer 1204 may be substantially similar to the metal nitride capping layer 1004 and may include an interfacial layer 1009 .

In optional step 1135, exposed surface 1205 shown in FIG. 12I is exposed to air. For example, in some embodiments, the final metal nitride capping layer 1204 is deposited in one processing system, while the next processing step to be performed on the semiconductor substrate 1001, namely step 1136, is a different processing. performed on the system. Thus, in such embodiments, the semiconductor substrate 1001 is exposed to air after deposition of the final metal nitride layer 1204. Optional step in embodiments in which the final metal nitride capping layer 1204 is deposited in one chamber of a multi-chamber processing system and step 1136 is performed in one or two other processing chambers of the same multi-chamber processing system. (1135) is not executed.

In step 1136, a sequential plasma hydrogenation and nitridation process is performed on the surface 1205 of the final metal nitride capping layer 1204, as shown in FIG. 12J. The sequential plasma hydrogenation and nitridation process performed in step 1136 may be substantially similar to that employed in step 1104. Consequently, the interfacial layer 1009 may be removed or reduced during step 1136, whereby the final metal nitride capping layer 1204, the interfacial layer 1009, and, in some embodiments, the high-k dielectric O atoms present in layer 1003 are removed. As a result, the EOT of the metal gate structure 1000 is reduced without scaling the thickness 1003A of the high-k dielectric layer 1003.

After the sequential plasma hydrogenation and nitridation process is performed in step 1136, the method 1100 proceeds to step 1107, where the final layer of the metal gate structure 1000 is deposited. In embodiments in which steps 1136 and 1107 are performed in different processing systems, the semiconductor substrate 1001 is essentially exposed to air. However, since the plasma nitridation process of step 1136 may completely or nearly completely nitridize the exposed surface 1205 of the final metal nitride capping layer 1204, during this air exposure there is typically little or no oxidation of the surface. It doesn't happen at all.

Single-step nitridation-hydrogenation treatment

The method 1300 begins at step 1301 where a high-k dielectric layer 1003 is deposited over the interfacial oxide layer 1002 as shown in FIG. 14A. The interfacial oxide layer 1002 may be deposited by any suitable method, such as chemical oxidation of the underlying semiconductor substrate 1001, thermal oxidation of the underlying substrate, atomic layer deposition (ALD), chemical vapor deposition (CVD), and the like. there is. High-k dielectric layer 1003 may be formed via any suitable deposition method described above in conjunction with FIG. 10 . The high-k dielectric layer 1003 can include any high-k material that can be oxidized. According to one embodiment, the high-k dielectric layer 1003 includes silicon dioxide (SiO ₂ ) or hafnium oxide (HfO ₂ ).

In step 1302, a capping layer 1404 is deposited over the high-k dielectric layer 1003, as shown in FIG. 14B. The capping layer 1404 may be formed via any suitable deposition method described above in conjunction with FIG. 10 . The capping layer 1404 may include a metal nitride. According to one embodiment, the capping layer may include a metal nitride, such as titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), or titanium silicon nitride (TiSiN). In some embodiments, the deposition of the capping layer 1404 results in the formation of an interfacial layer 1409 disposed at the interface between the high-k dielectric layer 1003 and the capping layer 1404 . In such embodiments, the interfacial layer 1409 generally contains defects, such as O atoms and/or voids (Fig. may be similar to empty spaces 213 in 2a). Defects can allow unwanted charge transfer due to electron hopping from defect to defect. Charge transfer can cause current leakage or dielectric breakdown and reduce the electrical reliability of the metal gate structure 1000 .

In optional step 1303, exposed surface 1401 shown in FIG. 14B is exposed to air. For example, in some embodiments, capping layer 1404 is deposited in one processing system, such as multi-chamber processing system 500 of FIG. 5 , while the next processing step to be performed on semiconductor substrate 1001 are performed in different processing systems. Thus, in such embodiments, the semiconductor substrate 1001 is exposed to air after deposition of the capping layer 1404. In embodiments where the capping layer 1404 is deposited in one chamber of a multi-chamber processing system and step 1304 is performed in one or two other processing chambers of the same multi-chamber processing system, optional step 1303 is not performed

In embodiments where the capping layer 1404 deposited in step 1302 is a sacrificial layer that is subsequently removed, the method 1400 proceeds to step 1331 . In embodiments where the capping layer 1404 deposited in step 1302 remains on the metal gate structure 1000, the method 1300 proceeds to step 1304. In some embodiments, the sacrificial layer may be removed by use of a subsequent wet or dry etch process optional to the removal of the capping layer 1404 .

In step 1304, a single step plasma hydrogenation and nitridation process is performed on the surface 1401 of the capping layer 1404, as shown in FIG. 14C. Single-step plasma hydrogenation and nitridation processes include exposing a workpiece, eg, metal gate structure 1000, to a process plasma, the process plasma comprising a nitrogen-containing gas and a hydrogen-containing gas. In some embodiments, the hydrogen-containing gas essentially comprises a gas containing both nitrogen and hydrogen, such as ammonia (NH ₃ ), hydrazine (N ₂ H ₄ ), or hydrogen azide (HN ₃ ). . In one example, the hydrogen-containing gas includes ammonia (NH ₃ ) and the nitrogen-containing gas includes (N ₂ ). According to one embodiment, the process plasma may include a single gas containing both hydrogen and nitrogen, such as hydrazine (N ₂ H ₄ ) or ammonia (NH ₃ ). According to one embodiment, the process plasma may include an additional neutral carrier gas, such as argon (Ar) or helium (He). In one example, the process gases contained in the process plasma essentially include ammonia (NH ₃ ), nitrogen (N ₂ ), and a neutral carrier gas such as argon (Ar) or helium (He). Additionally, a bias may be applied to the substrate by biasing power supply 426 during the single step plasma hydrogenation and nitridation process of step 1304 . The biasing power supply 426, similar to the RF power supply 414, can generally generate an RF signal having a tunable frequency ranging from about 2 MHz to about 160 MHz and a power of about 0 kW to about 10 kW. . The bias power improves the conformality of the grown film by rearranging the deposited atoms.

In some embodiments, the single-step plasma hydrogenation and nitridation process of step 1304 is between about 350° C. and about 500° C., with a chamber pressure between about 10 mTorr and about 100 mTorr, for a duration of about 30 seconds to about 150 seconds. at a processing temperature (eg, substrate pedestal temperature), an RF power of about 300 W to about 2000 W, a flow rate of NH ₃ of about 5 sccm to about 100 sccm, a flow rate of N ₂ of about 50 sccm to about 1000 sccm, A helium (He) flow rate of about 1 to about 1000 sccm is performed, and the substrate bias is applied at a frequency of about 2 MHz to about 160 MHz and a bias power of about 0 kW to about 10 kW.

In some embodiments, the single step plasma hydrogenation and nitridation process of step 1304 is between about 425° C. and about 475° C., with a chamber pressure between about 15 mTorr and about 25 mTorr, for a duration of about 85 seconds to about 95 seconds. At processing temperature, an RF power of about 900 W to about 1100 W, a flow rate of NH ₃ of about 15 sccm to about 35 sccm, a flow rate of N ₂ of about 450 sccm to about 550 sccm, an Ar of about 450 sccm to about 500 sccm , and no substrate bias power is applied.

In summary, at step 1304, surface 1401 is exposed to plasma excited hydrogen and nitrogen species generated in the plasma process, and some or all of the oxides present on surface 1401 are converted to nitrides. Thus, in some embodiments, interfacial layer 1409 thickening is eliminated or the thickening is significantly reduced, as shown in FIG. 14D. The interfacial layer 1409 still remains, but no thickening of the layer occurs. Nitriding or reducing the interfacial layer 1409 reduces the EOT and changes the work function of the metal gate structure 1000.

In some embodiments, prior to performing the single step plasma hydrogenation and nitridation process of step 1304, an anoxic conditioning process is performed in the process chamber, eg, to reduce trace oxygen contaminants in the process chamber. In such embodiments, the processing chamber is treated with an oxygen-free plasma before the substrate is processed through the single-step plasma hydrogenation and nitridation process described above, with no substrate placed in the chamber.

In optional step 1305, exposed surface 1401 is exposed to air. For example, in some embodiments, the single-step plasma hydrogenation and nitridation process described above of step 1304 is performed in one processing system, while the next processing step to be performed on the semiconductor substrate 1001 is a different process. performed on the system. Thus, in such embodiments, the semiconductor substrate 1001 is exposed to air after deposition of the layer 1404. In embodiments where the single step plasma hydrogenation and nitridation process of step 1304 is performed in one chamber of a multi-chamber processing system and step 1306 is performed in another process chamber of the same multi-chamber processing system, optional step 1305 ) is not performed.

In embodiments in which a sacrificial silicon-containing layer is subsequently deposited and removed as part of the formation of metal gate structure 1000, method 1300 proceeds from step 1305 to step 1321. In embodiments in which a sacrificial silicon layer is not deposited in forming the metal gate structure 1000, the method 1300 proceeds to step 1306. The sacrificial silicon-containing layer may be formed using a CVD or ALD process that uses one or more silicon-containing precursor gases to form the deposited layer.

At step 1306 , a thermal annealing process, such as a post-cap annealing, is performed on the semiconductor substrate 1001 , the interfacial layer 1002 , the high-k dielectric layer 1003 , and the capping layer 1404 . For example, in some embodiments, a spike annealing process is performed in step 1306 to reach a peak temperature of about 600 to about 900 degrees Celsius. A post-cap anneal is performed on the partially formed metal gate structure 1000 to smooth the interface, restore unsaturated bonds, and inject thermal energy into the capping layer 1404 .

In step 1307, a metal gate electrode layer 1005 is deposited on the processed capping layer 1404, as shown in FIG. 14E, thereby completing the formation of the metal gate structure 1000. Metal gate electrode 1005 may be formed via any suitable deposition method described above in conjunction with FIG. 10 .

In step 1321 , a sacrificial silicon layer 1202 is deposited over the capping layer 1404 , as shown in FIG. 14F . Step 1321 is performed after surface 1401 of capping layer 1404 has been treated by the single step plasma hydrogenation and nitridation process of step 1304 and optional air exposure of step 1305 .

In step 1322, a thermal annealing process, e.g., post-cap annealing, is performed on the semiconductor substrate 1001, interfacial layer 1002, high-k dielectric layer 1003, capping layer 1404, and sacrificial silicon layer 1202. ) is performed for The thermal annealing process of step 1322 can be substantially similar to the thermal annealing process of step 1306, described above.

At step 1323 , the sacrificial silicon layer 1202 is removed from the metal gate structure 1000 . Any technically feasible removal process may be employed at step 1323 and may include a selective wet etch process, a plasma based dry etch process, a chemical mechanical polishing process, or any combination thereof. Method 1300 then proceeds to step 1307, where the final layer of metal gate structure 1000 is deposited.

In step 1331 , a sacrificial silicon layer 1203 is deposited over the capping layer 1404 , as shown in FIG. 14G . Sacrificial silicon layer 1203 may be substantially similar to sacrificial silicon layer 1202 deposited in step 1331 . Note, however, that in step 1331, capping layer 1404 has not been treated in a single step plasma hydrogenation and nitridation process. Consequently, capping layer 1404 may still include interfacial layer 1409, as shown.

In step 1332, a thermal annealing process, e.g., post-cap annealing, is performed on the semiconductor substrate 1001, interfacial layer 1002, high-k dielectric layer 1003, capping layer 1404, interfacial layer 1409, and the sacrificial silicon layer 1203. The thermal annealing process of step 1332 can be substantially similar to the thermal annealing process of step 1306, described above.

In step 1333 , the sacrificial silicon layer 1203 , the capping layer 1404 and the interfacial layer 1409 are removed from the metal gate structure 1000 , as shown in FIG. 14H . Any technically feasible removal process or combination of processes may be employed at step 1333, including a selective wet etch process, a plasma-based dry etch process, a chemical mechanical polishing process, or any combination thereof. Method 1300 then proceeds to step 1334 .

In step 1334, a final capping layer 1404f is deposited over the high-k dielectric layer 1003, as shown in FIG. 14I. The final capping layer 1404f may be composed of the same material as the capping layer 1404, and the final capping layer may also include an interfacial layer 1409.

In optional step 1335, exposed surface 1405 shown in FIG. 14I is exposed to air. For example, in some embodiments, the final capping layer 1404f is deposited in one processing system, while the next processing step to be performed on the semiconductor substrate 1001, namely step 1336, is performed in a different processing system. is carried out Thus, in such embodiments, the semiconductor substrate 1001 is exposed to air after deposition of the final capping layer 1404f. In embodiments where the final capping layer 1404f is deposited in one chamber of a multi-chamber processing system and step 1336 is performed in one or two other processing chambers of the same multi-chamber processing system, optional step 1335 ) is not performed.

In step 1336, a single step plasma hydrogenation and nitridation process is performed on the surface 1405 of the final capping layer 1404, as shown in FIG. 14J. The single step plasma hydrogenation and nitridation process performed in step 1336 may be substantially similar to that employed in step 1304. Consequently, the interfacial layer 1409 thickening may be removed or reduced during step 1336, whereby the final capping layer 1404f, the interfacial layer 1009, and, in some embodiments, the high-k dielectric O atoms present in layer 1003 are removed. As a result, the EOT of the metal gate structure 1000 is reduced without scaling the thickness 1003A of the high-k dielectric layer 1003.

After the single step plasma hydrogenation and nitridation process is performed in step 1336, the method 1300 proceeds to step 1307, where the final layer of the metal gate structure 1000 is deposited. In embodiments in which steps 1336 and 1307 are performed in different processing systems, the semiconductor substrate 1001 is essentially exposed to air. However, since the plasma nitridation process of step 1336 may completely or nearly completely nitrid the exposed surface 1405 of the final capping layer 1404f, little or no oxidation of the surface typically occurs during this air exposure. I never do that.

In embodiments disclosed herein, a sequential hydrogenation and nitridation process, or a single step hydrogenation and nitridation process, is employed to enable formation of a metal gate structure with a reduced EOT relative to similar structures formed through conventional methods. . Following the plasma hydrogenation process, a plasma nitridation process is performed on the metal nitride layer of the film stack, thereby removing, in some embodiments, O atoms disposed within the layers of the film stack and, in some embodiments, within the film stack. Reduce or prevent thickening of the disposed oxygen-containing interfacial layer and, in some embodiments, add N atoms to the layers of the film stack. As a result, the EOT of the metal gate structure is reduced with little or no accompanying flatband voltage shift. In addition, the metal gate structure operates with an increased leakage current that is less than 1/4 of the increase in leakage current associated with a similar metal gate structure formed through conventional techniques.

While the foregoing relates to embodiments of the present disclosure, other and additional embodiments of the present disclosure may be devised without departing from its basic scope, which scope is determined by the claims that follow.

Claims (20)

A method of forming a structure in a semiconductor device comprising:
depositing a sacrificial layer on a high-k dielectric layer formed over a surface of a semiconductor substrate;
depositing a silicon-containing layer on the sacrificial layer;
performing a thermal annealing process on the sacrificial layer and the silicon-containing layer;
removing the sacrificial layer and the silicon-containing layer;
depositing a metal nitride capping layer on the high-k dielectric layer; and
Exposing the exposed surface of the deposited metal nitride capping layer to a plasma comprising a first gas comprising a hydrogen containing species and a second gas comprising a nitrogen containing species - the hydrogen containing species of the first gas A method of forming a structure in a semiconductor device comprising: comprising nitrogen. delete delete According to claim 1,
The method of claim 1 , wherein the metal nitride capping layer comprises titanium and nitrogen, the hydrogen-containing species comprises ammonia, and the nitrogen-containing species comprises nitrogen gas (N ₂ ). According to claim 1,
The method of claim 1 , wherein the hydrogen-containing species comprises ammonia and the nitrogen-containing species comprises nitrogen gas (N ₂ ). According to claim 5,
wherein exposing the exposed surface to the hydrogen-containing species and the nitrogen-containing species further comprises exposing the exposed surface to argon (Ar). A method of forming a structure in a semiconductor device comprising:
depositing a high-k dielectric layer on the semiconductor substrate;
depositing a sacrificial layer on the high-k dielectric layer;
depositing a silicon-containing layer on the sacrificial layer;
performing a tertiary thermal annealing process on the sacrificial layer and the silicon-containing layer;
removing the sacrificial layer and the silicon-containing layer;
depositing a capping layer on the high-k dielectric layer;
exposing the exposed surface of the capping layer to plasma excited hydrogen species and plasma excited nitrogen species;
exposing the exposed surface to air; and
A method of forming a structure in a semiconductor device comprising performing a thermal annealing process on the high-k dielectric layer and the capping layer at a specified temperature for a specified time period. According to claim 7,
prior to depositing the high-k dielectric layer, forming an interfacial layer containing silicon dioxide on which the high-k dielectric layer is subsequently formed. delete delete According to claim 7,
prior to exposing the exposed surface to the plasma excited hydrogen species and the plasma excited nitrogen species, performing an oxygen-free plasma treatment process to a process chamber in which the exposed surface is exposed to the plasma excited hydrogen species. A method of forming a structure in a semiconductor device, further comprising. According to claim 7,
wherein a substrate bias is applied to the semiconductor substrate while exposing the exposed surface to the plasma excited hydrogen species and the plasma excited nitrogen species. According to claim 7,
The method of claim 1 , wherein the plasma excited hydrogen species comprises ammonia and the plasma excited nitrogen species comprises nitrogen gas (N ₂ ). A method of forming a structure in a semiconductor device comprising:
depositing a high-k dielectric layer on the semiconductor substrate;
depositing a sacrificial layer on the high-k dielectric layer;
depositing a silicon-containing layer on the sacrificial layer;
performing a thermal annealing process on the sacrificial layer and the silicon-containing layer;
removing the sacrificial layer and the silicon-containing layer;
depositing a capping layer on the high-k dielectric layer to form a portion of the structure, the portion including the capping layer and the high-k dielectric layer, the deposited capping layer covering an exposed surface. have -; and
exposing the exposed surface to plasma excited hydrogen species and plasma excited nitrogen species, the plasma excited hydrogen species comprising ammonia and the plasma excited nitrogen species comprising nitrogen gas (N ₂ ); A method of forming a structure in a semiconductor device comprising: According to claim 14,
wherein a substrate bias is applied to the semiconductor substrate while exposing the exposed surface to the plasma excited hydrogen species and the plasma excited nitrogen species. According to claim 1,
wherein the metal nitride capping layer comprises a metal selected from the group consisting of titanium, tantalum and tungsten. According to claim 1,
A method of forming a structure in a semiconductor device, wherein a substrate bias is applied to the semiconductor substrate while exposing the exposed surface to the plasma. According to claim 1,
further comprising forming an interfacial layer containing silicon dioxide on the surface of the semiconductor substrate;
wherein the high-k dielectric layer is formed on the interfacial layer containing silicon dioxide formed in the semiconductor substrate. According to claim 1,
prior to exposing the exposed surface to the plasma excited hydrogen species and the plasma excited nitrogen species, for at least one surface of a process chamber to which the exposed surface is exposed to the plasma excited hydrogen species, the semiconductor substrate and performing an oxygen-free plasma treatment process when not disposed within the process chamber. According to claim 7,
The method of claim 1 , wherein the capping layer comprises nitrogen and a metal.

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