JP2006060155A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately and simply form gate insulating films of different electric film thicknesses using a High-k film on the front surface of the same semiconductor substrate under high reproducibility. <P>SOLUTION: An n well layer 2 surface part of a silicon substrate 1 is partitioned by an element isolation region 3. In the MISFET of a peripheral circuit part, a first gate insulating film 6 having a multilayer film of a base oxide film 4 of 4-6 nm of film thickness, a nitride layer 4a of its modified layer, a High-k film 5 and a nitride layer 5a of its modified layer is formed. In the MISFET of an internal circuit part, a second gate insulating film 13 having a multilayer film of a ground film 12 of about 1 nm of film thickness, a nitride layer 12a of its modified layer, the High-k layer 5 and a nitride layer 5a of its modified layer is formed. The High-k film 5 becomes suitably an insulating film of HfSiOx, ZrSiOx, HfAlOx or ZrAlOx. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically, an insulated gate field effect transistor having a plurality of types of gate insulating films made of a high dielectric constant insulating film (High-k film) formed on the semiconductor device ( MISFET) and a method for forming the same on a semiconductor substrate.

  Although semiconductor elements such as MISFETs constituting a semiconductor device have been miniaturized in accordance with a scaling law, in recent years, it has become common to use different driving voltages for the peripheral circuit portion and the internal circuit portion of the semiconductor device. In the former, since a relatively high voltage is applied, a thick gate insulating film is formed, and in the latter, a thin gate insulating film is used for speeding up operation or reducing power consumption. It is formed.

  Recently, as referred to as “System on Chip” (SoC), a large number of semiconductor devices are obtained by mounting digital circuits (for example, logic circuits, memory circuits) or analog circuits on a silicon semiconductor chip. Functionalization or systematization is energetically advanced. In such a semiconductor device, the semiconductor device is driven with a plurality of types of voltages. Then, gate insulating films having different electrical thicknesses are formed in the silicon semiconductor chip, and MISFETs having the different gate insulating films are used in the respective constituent circuit portions of the semiconductor device. For example, a gate insulating film with a different equivalent film thickness of a silicon oxide film is formed in the logic circuit portion, and a gate insulating film with a reduced equivalent thickness is formed in the memory circuit portion or the analog circuit portion. Here, the gate insulating films having different electrical thicknesses are gate insulating films having the same material and different film thicknesses, or gate insulating films having different materials or relative dielectric constants. It is also referred to as a gate insulating film having a different converted film thickness, which is described by the converted film thickness of the oxide film.

  A conventional manufacturing method for forming the above-described gate insulating films having different thicknesses will be specifically described with reference to FIG. 9 (hereinafter, this case is referred to as a first conventional example). This prior art is used as a mass production technique for semiconductor device products whose design criteria for semiconductor elements are about 130 nm.

  As shown in FIG. 9A, an element isolation region 102 by shallow trench isolation (STI; Shallow Trench Isolation) is formed on the surface portion of the silicon substrate 101 by a well-known method, and the entire surface of the substrate is thickened by thermal oxidation. A first silicon oxide film 103 having a thickness of about 6 nm is formed. Here, although not shown, ion implantation is performed on the surface of the silicon substrate 101 to form a well region or a channel region.

  Next, as shown in FIG. 9B, a resist mask 104 is formed by photolithography, and wet etching is performed with a hydrofluoric acid (HF) chemical solution using the resist mask 104 as an etching mask. The first silicon oxide film 103 is removed to expose the surface of the silicon substrate 101. Subsequently, as shown in FIG. 9C, the resist mask 104 is removed, and the first silicon oxide film 103 is left only in a predetermined region on the surface of the silicon substrate 101.

  After this, the silicon substrate 101 is thermally oxidized again to form a thin second silicon oxide film 105 having a thickness of about 3 nm, for example. At this time, the thickness of the first silicon oxide film 103 is slightly increased, and the thickness becomes slightly over 7 nm. In this way, the first silicon oxide film 103 and the second silicon oxide film 105 having different thicknesses formed on the surface of the silicon substrate 101 are used as gate insulating films. By forming a gate electrode on the film and further forming a source / drain diffusion layer, a MISFET having a gate insulating film with a different electrical film thickness as described above is formed.

  Another conventional manufacturing method (hereinafter referred to as a second conventional example) for forming the above-described gate insulating films having different thicknesses will be described with reference to FIGS. 9 and 10 (see, for example, Patent Document 1). . This second conventional example can be applied to a semiconductor device having a semiconductor element design standard of about 90 nm.

  In the step shown in FIG. 9A, as described above, the element isolation region 102 is formed on the silicon substrate 101, and the first silicon oxide film 103 of about 10 nm is formed on the entire surface of the substrate by thermal oxidation. However, in the case of this conventional technique, the first silicon oxide film 103 is completely removed later and becomes a sacrificial oxide film that does not remain in the product. Then, ion implantation is performed through the first silicon oxide film 103 to form a well layer and a channel region (not shown). Subsequently, through the steps shown in FIGS. 9B and 9C, exactly the same as in the first conventional example, one region of the surface of the silicon substrate 101 is exposed and the first silicon oxide film 103 is exposed only in the other region. Leave.

Next, as shown in FIG. 10A, annealing (thermal oxynitridation) is performed in an NO gas or N ₂ O gas atmosphere to form a silicon oxynitride film 106 in the exposed region of the silicon substrate 101. In this thermal oxynitridation, the first silicon oxide film 103 is also oxynitrided, but since the thickness of the first silicon oxide film 103 is relatively large, the amount of nitrogen introduced into the film is small.

  Next, as shown in FIG. 10B, wet etching is performed on the entire surface so as to remove the first silicon oxide film 103 by dilute hydrofluoric acid treatment, so that the first silicon oxide film 103 is completely removed. In this dilute hydrofluoric acid treatment, since the silicon oxynitride film 106 contains a high concentration of nitrogen in the film, the etching rate is lower than that of the first silicon oxide film 103. As a result, the silicon oxynitride film All of the film 106 remains as a thin silicon oxynitride film 106a without being etched.

  And after doing in this way, as shown in FIG.10 (c), thermal oxidation is performed again. By this thermal oxidation, the first silicon oxide film 103 is removed and an exposed surface of the silicon substrate 101 has a high oxidation rate and a high-quality thick second silicon oxide film 108 is formed. In contrast, in the region where the thin silicon oxynitride film 106a exists, the oxidation rate is low, and the thin oxynitride film 107 containing nitrogen is formed in the film. The thin oxynitride film 107 and the second silicon oxide film 108 thus obtained are used as the gate insulating film of the MISFET.

  In this method, since the first silicon oxide film 103 directly covered with the resist mask 104 is not used as a gate insulating film as in the first conventional example, the quality of the gate insulating film of the MISFET Is going to improve.

As a conventional manufacturing method for forming gate insulating films having different thicknesses, a method of introducing nitrogen atoms into the silicon substrate surface (hereinafter referred to as a third conventional example) has been proposed. This method is a technique utilizing the fact that the thermal oxidation rate on the surface of the silicon substrate is lowered by introducing nitrogen atoms. Specifically, after selectively introducing nitrogen atoms into the surface region of the silicon substrate by ion implantation or the like, a thin silicon oxide film is formed on the surface of the silicon substrate into which nitrogen atoms are introduced by thermally oxidizing the silicon substrate. In this method, a thick silicon oxide film is simultaneously formed on the surface of a silicon substrate into which nitrogen atoms are not introduced. Furthermore, by varying the amount of nitrogen atoms introduced into each region of the silicon substrate surface, silicon oxide films having various film thicknesses corresponding to the nitrogen atom amounts are simultaneously formed on the substrate surface.
JP 2002-110812 (paragraphs [0044] to [0050], FIG. 1)

  Miniaturization of semiconductor elements constituting a semiconductor device is the most important technical matter for improving the performance and SoC of a semiconductor device, and includes semiconductors including microfabrication technology such as photolithography technology and dry etching technology, and thin film formation technology. Various manufacturing techniques used for manufacturing have been researched and developed, and the design standard is being energetically advanced from the current mass production level of 130 nm to 90 nm toward the 65 nm or 45 nm manufacturing technique. Here, in the manufacturing technique with a design standard of 65 nm, the thinnest gate insulating film used in the digital circuit region with a driving voltage of 0.9 V has a converted film thickness of about 1.2 nm or less.

  As the semiconductor element is miniaturized and the equivalent gate insulating film thickness is reduced, nitrogen-containing silicon such as the silicon oxide film or oxynitride film described in the first, second, and third prior arts is used. In the gate insulating film made of an oxide film, the leakage current in the gate insulating film, that is, the gate leakage current becomes very large in driving the MISFET, which increases the power consumption of the semiconductor device and causes a large malfunction. In order to suppress and reduce the leakage current value in the gate insulating film, it is essential to apply a high-k film such as a metal oxide film to the gate insulating film. In addition, in a gate insulating film to which a high-k film is applied, it is essential to form gate insulating films having different equivalent film thicknesses in the same chip. Here, the High-k film is an insulating film having a relative dielectric constant larger than that of the silicon dioxide film (relative dielectric constant 3.9), and is an insulating film of various metal oxide films, metal silicates, and metal aluminates.

  However, no specific proposal has been made so far in which a high-k film is used as a gate insulating film of a MISFET and gate insulating films having different equivalent film thicknesses can be applied to the same chip at a practical level. The first reason is that since the thermal stability of the high-k film is generally small, the composition of the film is likely to change during the thermal process in the manufacturing process of the semiconductor device, and the consistency with the manufacturing process of the semiconductor device is taken. It is difficult. The second reason is that the High-k film easily causes an interface reaction with the polycrystalline silicon film constituting the silicon substrate or the gate electrode, and the film thickness control becomes difficult. The third reason is that so-called boron penetration in the High-k film is likely to occur, and in particular, threshold control of the p-channel MISFET becomes difficult.

  The present invention has been made in view of the above circumstances. A semiconductor in which a high-k film is applied to a gate insulating film of a MISFET and a gate insulating film having a different electrical film thickness on a practical level is formed on a silicon semiconductor chip. An object of the present invention is to provide an apparatus and a manufacturing method thereof.

  In order to solve the above problems, a first invention relating to a semiconductor device is a semiconductor device including an insulated gate field effect transistor in which gate insulating films having different electrical thicknesses are formed on the same semiconductor substrate. A structure in which a first oxide film whose surface is modified to a nitrogen-containing layer and a high dielectric constant insulating film whose surface is modified to a nitrogen-containing layer are stacked in this order on the semiconductor substrate. And an insulated gate field effect transistor having a first gate insulating film comprising: a first oxide film formed on the semiconductor substrate, wherein the first oxide film is thinner than the first oxide film and the surface thereof is modified to a nitrogen-containing layer. An insulating gate field effect transistor having a second gate insulating film comprising a structure in which the oxide film of 2 and the high dielectric constant insulating film whose surface is modified to a nitrogen-containing layer are stacked in this order, It becomes composition including There.

  Alternatively, the invention according to the semiconductor device is a semiconductor device including an insulated gate field effect transistor in which gate insulating films having different electrical film thicknesses are formed on the same semiconductor substrate, and formed on the semiconductor substrate, A first oxide film whose surface is modified to a nitrogen-containing layer, a high dielectric constant insulating film whose surface is modified to a nitrogen-containing layer, and a second film thicker than the film thickness of the first oxide film An insulated gate field effect transistor having a first gate insulating film including a structure in which oxide films are laminated in this order, a structure in which the first oxide film and the high dielectric constant insulating film are laminated in this order. And an insulated gate field effect transistor having a second gate insulating film.

In the above invention, the high dielectric constant insulating film is made of hafnia (HfO ₂ ), zirconia (ZrO ₂ ), hafnium silicate (HfSiOx), zirconium silicate (ZrSiOx), hafnium aluminate (HfAlOx), or zirconium aluminate (ZrAlOx). And at least one insulating film selected from the group consisting of:

  According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device including an insulated gate field effect transistor in which gate insulating films having different electrical thicknesses are formed on the same semiconductor substrate. A step of forming a first oxide film on the surface of the semiconductor substrate, and protecting the first oxide film in a region where the first gate insulating film is to be formed with a mask to form a region where the second gate insulating film is to be formed. Selectively etching away the first oxide film; and after removing the mask, a second oxide film having a thickness smaller than that of the first oxide film is formed in a region where the second gate insulating film is to be formed. A step of forming a film, a step of nitriding the first oxide film and the second oxide film, and modifying the surface of the first oxide film and the surface of the second oxide film into a nitrogen-containing layer, , The first oxide film and the second oxide film Forming a high dielectric constant insulating film covering the oxide film; and nitriding the high dielectric constant insulating film to reform the surface of the high dielectric constant insulating film into a nitrogen-containing layer, A first gate insulating film is formed by a laminated film of the first oxide film and the high dielectric constant insulating film, and a second gate insulating film is formed by the laminated film of the second oxide film and the high dielectric constant insulating film. It is the structure which forms.

  Alternatively, the invention relating to a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device comprising an insulated gate field effect transistor in which gate insulating films having different electrical film thicknesses are formed on the same semiconductor substrate, wherein the semiconductor Forming a first oxide film on the surface of the substrate; nitriding the first oxide film to modify the surface of the first oxide film to a nitrogen-containing layer; and Forming a high dielectric constant insulating film to be coated; nitriding the high dielectric constant insulating film to reform the surface of the high dielectric constant insulating film into a nitrogen-containing layer; and A step of forming a second oxide film to be coated; and the second oxide film in a region where the first gate insulating film is to be formed is protected with a mask, and the second region in which the second gate insulating film is to be formed is protected. Selectively removing the oxide film by etching; A first gate insulating film is formed of a stacked film of the first oxide film, the high dielectric constant insulating film, and the second oxide film, and the first oxide film and the high dielectric constant insulating film The second gate insulating film is formed using a stacked film.

  According to the present invention, gate insulating films having different electrical thicknesses using a High-k film for reducing gate leakage current of a MISFET constituting a semiconductor device can be formed on the same semiconductor substrate with high reproducibility. Accurate and simple formation.

Hereinafter, some of the embodiments of the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
FIG. 1 is a cross-sectional view of the main part of the semiconductor device according to the first embodiment of the present invention, and FIGS. Here, a technology generation in which the design standard of the semiconductor element is 65 nm to 45 nm is shown. In this generation, a MISFET that operates at a voltage of 1 V or less is formed in the internal circuit of the semiconductor device, and the thickness of the gate insulating film is about 1.2 nm or less in terms of a silicon oxide film. A peripheral circuit of the semiconductor device, for example, an input / output circuit, is formed with a MISFET operating at a (power supply) voltage of 1.5 V to 3.3 V, and the thickness of the gate insulating film is 3 nm to 6 nm in terms of silicon oxide film. It will be about. Here, since the peripheral circuit differs greatly depending on the semiconductor device, there is a range in the usage range of the driving voltage and the film thickness of the gate insulating film.

  In the following description, a p-channel type MISFET will be described, but an n-channel type MISFET is formed in the same manner. As shown in FIG. 1, for example, at least two types of MISFETs having gate insulating films having different equivalent film thicknesses in a region corresponding to a peripheral circuit portion on a p-conductivity type silicon substrate 1 and a region corresponding to an internal circuit portion are provided. It is formed.

That is, an n well layer 2 is formed on the surface portion of the silicon substrate 1, and the surface portion of the n well layer 2 is partitioned by an element isolation region 3 by STI. In the MISFET in the peripheral circuit portion, the base oxide film 4 having a thickness of 4 to 6 nm and the nitride layer 4a whose surface is modified to a nitrogen-containing layer, the High-k film 5 and the surface thereof are modified to a nitrogen-containing layer. A first gate insulating film 6 made of a laminated film of the nitrided layer 5a is formed. Then, a gate electrode 9 is constituted by the polycrystalline silicon layer 7 containing the p-conductivity type or n-conductivity type impurity formed on the first gate insulating film 6 and the silicide layer 8, and the first gate insulating film 6. A sidewall insulating film 10 is provided on the side wall of the gate electrode 9. Here, the base oxide film 4 is formed of a silicon oxide film, and the high-k film 5 is formed of hafnia (HfO ₂ ), zirconia (ZrO ₂ ), hafnium silicate (HfSiOx), zirconium silicate (ZrSiOx), hafnium aluminate ( An insulating film having a thickness of 2 to 3 nm made of HfAlOx) or zirconium aluminate (ZrAlOx) is preferable. Alternatively, the High-k film 5 may be configured by an insulating film having a stacked structure in which two or more types of insulating films are selected from the high dielectric constant insulating films and stacked. A source / drain region including a source / drain diffusion layer 11 and a silicide layer 8 is provided on the surface of the n well layer 2.

  On the other hand, in the MISFET of the internal circuit portion, the base film 12 with a film thickness of about 1 nm and the nitride layer 12a whose surface is modified to a nitrogen-containing layer, the High-k film 5 and the nitride layer which is a modified layer on the surface thereof A second gate insulating film 13 is formed by the laminated film 5 a, and the above-described polycrystalline silicon layer 7 and silicide layer 8 are provided on the second gate insulating film 13. Sidewall insulating films 10 are provided on the side walls of the second gate insulating film 13 and the gate electrode 9, and source / drain regions including the source / drain diffusion layers 11 and the silicide layers 8 are provided on the surface of the n-well layer 2. It has been. In the second gate insulating film 13 of the MISFET, the base film 12 has a silicon oxide film structure as a basic structure, and is interposed between the high-k film 5 and the silicon substrate 1 on the surface of the n-well layer 2. It has functions such as preventing boron penetration and improving the surface mobility of carrier charges (holes).

  Next, a method for manufacturing the semiconductor device according to the present invention will be described with reference to FIGS. Here, the same components as those in FIG. 1 are denoted by the same reference numerals.

  An n-well layer 2 is formed on the surface portion of the p-conductivity type silicon substrate 1, an STI element isolation region 3 is formed on the surface portion of the n-well layer 2, and a base oxide film 4 of about 5 nm is formed on the surface of the silicon substrate 1. It is formed by thermal oxidation. (FIG. 2 (a)).

  Next, a resist mask 14 is formed in a region corresponding to the peripheral circuit portion of the semiconductor device by a known photolithography technique, and the resist mask 14 is used as an etching mask, and wet etching with dilute hydrofluoric acid diluted by 2 vol% with pure water is performed. Processing is performed to remove the base oxide film 4 formed in the region corresponding to the internal circuit portion, thereby exposing the surface of the n-well layer 2 of the silicon substrate 1 serving as the region where the internal circuit is formed (FIG. 2 ( b)).

Subsequently, the resist mask 14 is removed and the surface of the silicon substrate 1 is cleaned. In this cleaning process, particles on the surface of the silicon substrate 1 need to be removed, so that chemicals such as a mixed liquid (APM) of ammonia (NH ₄ OH) water, hydrogen peroxide (H ₂ O ₂ ) water, and pure water are required. It is recommended to perform cleaning in chemicals. Alternatively, a mixed solution (SPM) of a sulfuric acid (H ₂ SO ₄ ) solution, hydrogen peroxide (H ₂ O ₂ ) water and pure water, a hydrochloric acid (HCl) solution, hydrogen peroxide (H ₂ O ₂ ) water and pure water Cleaning using a chemical solution such as a liquid mixture (HPM) with water may also be used.

  Next, the silicon substrate 1 is immersed in 0.1 vol% dilute hydrofluoric acid for about 1 second to coat the surface of the silicon substrate 1 with hydrogen atoms. By this coating treatment, the natural oxidation of the surface of the silicon substrate 1 in the air becomes difficult to proceed. However, since the hydrogen atoms are peeled off with the storage time of the silicon substrate 1 and a natural oxide film is formed on the exposed surface of the silicon substrate 1, the storage of the silicon substrate 1 is like nitrogen gas after the cleaning or coating process. It is preferable to avoid the contact between the silicon substrate 1 and air as much as possible in a space filled with an inert gas.

  Then, without leaving time, thermal oxidation in a dilute oxygen atmosphere or plasma oxidation at a low temperature (for example, 300 ° C. temperature) is performed to form the base film 12 having a film thickness of about 1 nm. Here, the base film 12 is a silicon oxide film (FIG. 2C).

Next, the surfaces of the base oxide film 4 and the base film 12 are nitrided by plasma nitriding, and the silicon oxide film surfaces are modified to form nitride layers 4a and 12a as nitrogen-containing layers (FIG. 2D). . In this plasma nitriding method, N ₂ gas, N ₂ O, NO, N ₂ H ₂ and NH ₃ gas, which are raw material gases, are excited by plasma in ECR (Electron Cyclotron Resonance), ICP (Inductively Coupled Plasma), (magnetron type) ) Active species of nitrogen are generated by excitation with RF plasma or helicon wave plasma, and the active species are exposed to the surface of the silicon oxide film. The active species include nitrogen atom ions, molecular ions, neutral radicals, and the like. Here, it is preferable that only the nitrogen neutral radicals are extracted from the active species to form the nitride layers 4a and 12a. For example, among the active species of nitrogen formed in the plasma excitation chamber, neutral radicals having a relatively long lifetime are extracted by the downflow method, and the neutral oxides are irradiated onto the surface of the base oxide film 4 and the base film 12. In this manner, the nitride layers 4a and 12a are preferably formed by the reaction between neutral radicals and the surface of the silicon oxide film.

  In the plasma nitriding method using nitrogen neutral radicals, the nitrogen active species and the depth of the nitride layer in the nitride layers 4a and 12a to be formed are limited because the active species of nitrogen are controlled to one kind. It becomes possible to control with high accuracy. Further, this method is a so-called remote plasma method, and since the ion irradiation or plasma emission irradiation can be prevented, irradiation damage in the base oxide film 4 and the base film 12 is greatly reduced, and a high-quality gate insulating film is obtained. Can be secured.

Here, when the active species is generated by plasma excitation of a source gas containing hydrogen such as N ₂ H ₂ or NH ₃ gas, a large amount of hydrogen is mixed into the nitride layer and the silicon oxide film to deteriorate the film quality. . Therefore, in this case, it is preferable to desorb hydrogen in the film by performing a heat treatment in an inert gas after the plasma nitridation.

In the plasma nitriding method described above, the amount or depth of nitrogen introduced into the base oxide film 4 and the base film 12 can be easily controlled by the plasma processing conditions or processing time such as the power power of plasma excitation. FIG. 4 shows an example of nitrogen distribution in the nitride layer 12a. Here, the plasma nitridation was performed by irradiating the surface of the underlayer 12 with nitrogen neutral radicals in a downflow manner by exciting the N ₂ gas with ECR. FIG. 4 is a nitrogen distribution diagram obtained by XPS (Xray Photoelectron Spectroscopy) analysis of the nitride layer 12a. As can be seen from FIG. 4, the nitrogen concentration on the surface of the nitride layer 12a is 15 at. % To 20 at. The nitrogen concentration decreases as the depth from the surface decreases, and nitrogen does not exist in a region deeper than 1 nm. Therefore, there is almost no nitrogen at the interface between the base film 12 and the n-well layer 2.

Next, a High-k film 5 is deposited on the entire surface so as to cover the base oxide film 4 and the base film 12. As the High-k film 5, for example, a thin film of HfAlOx, HfSiOx or HfO ₂ having a relative dielectric constant of 10 to 20 is formed. It is preferable to use an ALD (Atomic Layer Deposition) method or an MOCVD (Metal Organic Chemical Vapor Deposition) method for the growth of such a High-k film. For example, when HfAlOx is formed as the high-k film by using the ALD method, the substrate temperature is 300 ° C., and hafnium tetrachloride (HfCl ₄ ) and trimethylaluminum (TMA) are used as the film forming raw materials. A thin film of HfAlOx having a film thickness of 2 nm to 3 nm is formed using water vapor (H ₂ O) or ozone (O ₃ ) as an oxidant (FIG. 3A). In the formation of the high-k film 5, the thin base film 12 prevents an interface reaction between the high-k film 5 and the silicon substrate 1 on the surface of the n-well layer 2.

  Note that after the formation of the High-k film 5, heat treatment in a very small amount of oxygen atmosphere may be performed. In the case of using the above-described thin film material of HfAlOx, heat treatment is performed for several seconds at a temperature of, for example, about 1000 ° C. by a lamp type rapid temperature increase and decrease annealing (RTA) apparatus. By this heat treatment, oxygen vacancies in the High-k film 5 are compensated, and at the same time, the concentration of the conductive impurities contained in the High-k film 5 can be reduced. The film quality of the HfAlOx thin film is improved, and the gate leakage current can be further reduced.

  Next, in the same manner as described with reference to FIG. 2D, the surface of the high-k film 5 is nitrided by plasma nitriding, and the surface of the high-k film 5 is modified to form a nitride layer 5a as a nitrogen-containing layer. It forms (FIG.3 (b)). In the plasma nitriding in this case, the plasma processing conditions such as the power of plasma excitation or the processing time may be substantially the same as described with reference to FIG. Here, the depth of the nitride layer 5a formed by plasma nitridation of the High-k film 5 is 1 nm or less, and the nitride layers 4a and 12a formed by plasma nitridation of the silicon oxide film of the base oxide film 4 or the base film 12. Shallow than the depth of. The nitrogen concentration on the surface of the nitride layer 5a is 20 at. %.

Next, a silicon film 15 is deposited on the high-k film 5 that has been plasma nitrided. The silicon film 15 is formed by using a low pressure chemical vapor deposition (LPCVD) method, which is a chemical vapor deposition (CVD) method, and a reactive gas such as monosilane (SiH ₄ ) gas or nitrogen thereof. Use dilution gas. Then, for example, film formation is performed for about 40 minutes under conditions where the film formation temperature is 600 ° C. and the film formation pressure is 2 Pa. In this way, a polycrystalline silicon film having a thickness of 150 nm is formed (FIG. 3C). In the formation of the silicon film 15, disilane (Si ₂ H ₆ ) gas may be used as the reaction gas. Alternatively, the film may be formed by a thermal catalytic decomposition CVD (Cat-CVD) method or a plasma CVD method.

In the formation of a silicon film by a CVD method using a silicon (Si) compound gas such as monosilane gas or disilane gas as described above, an intermediate product such as SiH ₂ is usually thermally decomposed on its surface to generate an intermediate product. This causes dissociative adsorption and generation of hydrogen of active Si species. Then, an intermediate product such as Si active species that has been activated on the surface of the High-k film 5 in the silicon film formation or the generated hydrogen, particularly in the initial stage where the silicon film starts to grow on the film, is High- The k film 5 is reduced, or the dissociatively adsorbed Si that has been activated on the surface thereof reacts with oxygen in the film to form a low dielectric constant layer containing SiOx having a relative dielectric constant smaller than that of the film. Or However, when the surface of the High-k film 5 is modified to form the nitride layer 5a, the formation of the low dielectric constant layer is lost. Here, the nitrogen concentration on the surface of the nitride layer 5a is 15 at. % To 20 at. % Is preferred.

  Next, after introducing n-type or p-type conductivity impurities into the silicon film 15 by ion implantation and heat treatment (about 850 ° C.), the silicon film 15, the high-k film 5, and the base are used by using a known photolithography technique and etching technique. The oxide film 4, the base film 12 and the like are sequentially patterned to form the polycrystalline silicon layer 7, the first gate insulating film 6 and the second gate insulating film 13 constituting the gate portion of the MISFET (FIG. 3D). ).

  Thereafter, as described with reference to FIG. 1, boron is ion-implanted in a self-aligning manner using the polycrystalline silicon layer 7 as a mask to form extension layers in the source / drain regions. Then, a sidewall insulating film 10 made of a silicon oxide film or a silicon nitride film is formed by a well-known method, and boron is ion-implanted in a self-aligning manner using the polycrystalline silicon layer 7 and the sidewall insulating film 10 as a mask, and a heat treatment (850). And the source / drain diffusion layer 11 is formed. Thereafter, a silicide layer 8 is formed on the polycrystalline silicon layer 7 and the source / drain diffusion layer 11 using a known self-aligned silicide formation technique called a salicide technique. Hereinafter, although not shown, an interlayer insulating film and wiring are formed. In this manner, a p-channel type MISFET is formed.

  In the MISFET constituting the input / output circuit of the semiconductor device manufactured as described above, the first gate insulating film 6 having a converted film thickness of about 5 nm is formed. In the MISFET forming the internal circuit of the semiconductor device, the converted film thickness is formed. A second gate insulating film 13 having a thickness of about 1 nm is formed. Then, MISFETs having gate insulating films having different electrical thicknesses are formed on the silicon substrate 1.

  In the first embodiment, in particular, in the base film 12 of the second gate insulating film 13 of the MISFET constituting the internal circuit, as described with reference to FIG. Less near the interface. For this reason, the surface mobility of holes is higher than that in the case of forming an oxynitride film between a high-k film and a silicon substrate as in the prior art. This will be described with reference to FIG. Here, the vertical axis shows the surface mobility of holes, and the horizontal axis shows the strength of the gate electric field applied to the gate insulating film of the MISFET. Usually, when the mobility becomes higher than the electric field strength which increases with the increase of the gate electric field strength, the value becomes saturated. As shown in FIG. 5, in the saturation region, the surface mobility of holes is improved by 25 to 30% in the embodiment of the present invention compared to the conventional technique. This increase in the surface mobility of holes improves the operating speed of the internal circuit of the semiconductor device by about 30%.

  In the first embodiment, since the nitride layer 5a is formed on the surface of the high-k film 5, the composition change of the surface of the high-k film 5 during the formation of the silicon film 15 is prevented. In order to improve the thermal stability of the high-k film 5 by the plasma nitridation described above, the film is also formed in the thermal process in the manufacturing process of the semiconductor device, particularly in the heat treatment (for example, 850 ° C. temperature) for activating the impurities. No composition change occurs. Moreover, the plasma nitridation method for forming the nitride layer 5a is a very simple method. Therefore, it becomes easy to control the film thickness of the gate insulating film, and it becomes possible to form gate insulating films having different electric film thicknesses with good reproducibility.

  Further, the nitride layer 5a on the surface of the High-k film 5, the nitride layer 4a on the surface of the base oxide film 4, or the nitride layer 12a on the surface of the base film 12 introduces boron impurities into the polycrystalline silicon layer 7 of the p-channel type MISFET. That occurs when the boron impurity penetrates the gate insulating film and reaches the channel region to change the threshold value of the MISFET, or the impurity concentration in the polycrystalline silicon layer 7 decreases, so that the depletion layer is formed in the interface region of the polycrystalline silicon layer 7. The problem that the drive capability of the MISFET is reduced due to the formation of the MISFET can be solved.

  In the first embodiment, after the MISFET base oxide film 4 constituting the peripheral circuit of the semiconductor device is formed, the gate insulating film in the internal circuit portion and the gate insulating film in the peripheral circuit portion are all formed by the same process. Is done. For this reason, the manufacture of a semiconductor device composed of MISFETs having gate insulating films with different equivalent film thicknesses is simplified, and the manufacturing cost can be reduced.

(Embodiment 2)
FIG. 6 is a cross-sectional view of the main part of the semiconductor device according to the second embodiment of the present invention, and FIGS. Here, the present invention can also be applied to a technology generation in which the design standard of the semiconductor element is 65 nm or less, for example, 45 nm, and the film thickness of the gate insulating film of the MISFET constituting the logic circuit of the semiconductor device is 1 in terms of silicon oxide film. The thickness of the gate insulating film of the MISFET constituting the memory circuit of the semiconductor device is about 2 nm in terms of silicon oxide film.

  The following MISFET may be either a p-channel type or an n-channel type, and it is sufficient to use a conductivity type impurity corresponding thereto. As shown in FIG. 6, at least two types of MISFETs having gate insulating films having different equivalent film thicknesses are formed in a region corresponding to the memory circuit portion and a logic circuit portion on the silicon substrate 21.

That is, the surface portion of the silicon substrate 21 is partitioned by the element isolation region 22 by STI, and in the MISFET of the memory circuit portion, the base film 23 having a film thickness of 1 nm or less and the nitride layer 23a which is a modified layer on the surface thereof, High-k A first gate insulating film 26 composed of a laminated film of the film 24 and a nitride layer 24a as a modified layer on the surface thereof and an upper oxide film 25 is formed. A gate electrode 29 is constituted by the impurity-containing polycrystalline silicon layer 27 formed on the first gate insulating film 26 and the silicide layer 28, and side walls of the first gate insulating film 26 and the gate electrode 29 are provided on the side walls. A wall insulating film 30 is provided. Here, the base film 23 may be a material film similar to the base film 12 described in the first embodiment. The High-k film 24 has a film thickness of 2 consisting of hafnia (HfO ₂ ), zirconia (ZrO ₂ ), hafnium silicate (HfSiOx), zirconium silicate (ZrSiOx), hafnium aluminate (HfAlOx), and zirconium aluminate (ZrAlOx). An insulating film of ˜3 nm is preferable. The upper oxide film 25 may be a silicon oxide film formed by CVD. A source / drain region including a source / drain diffusion layer 31 and a silicide layer 28 is provided on the surface of the silicon substrate 21.

  On the other hand, in the MISFET of the logic circuit portion, the base film 23 having a film thickness of 1 nm or less and the nitride layer 23a which is a modified layer on the surface thereof, the High-k film 24 and the nitride layer 24a which is a modified layer on the surface thereof. A second gate insulating film 32 is formed, and the polycrystalline silicon layer 27 and the silicide layer 28 described above are provided on the second gate insulating film 32. Sidewall insulating films 30 are provided on the side walls of the second gate insulating film 32 and the gate electrode 29, and source / drain regions including a source / drain diffusion layer 31 and a silicide layer 28 are provided on the surface of the silicon substrate 21. ing.

  Next, a method for manufacturing the semiconductor device according to the present invention will be described with reference to FIGS. Here, the same components as those in FIG. 6 are denoted by the same reference numerals.

  An STI element isolation region 22 is formed on the surface portion of the silicon substrate 21, and a base film 23 of 1 nm or less is formed on the surface of the silicon substrate 21 by a thermal oxidation or plasma oxidation method similar to that described with reference to FIG. Form. (FIG. 7A).

  Next, the surface of the base film 23 is nitrided by the plasma nitriding method described in Embodiment 1, and the surface is modified to form a nitride layer 23a as a nitrogen-containing layer (FIG. 7B). Here, it is preferable to form the nitride layer 23a by taking out only nitrogen neutral radicals from active species generated by plasma excitation.

  Next, a high-k film 24 having a film thickness of 2 nm to 3 nm is deposited on the entire surface. Here, the High-k film 24 is formed in the same manner as in the first embodiment (FIG. 7C).

  Then, as described above, the surface of the high-k film 24 is nitrided by plasma nitriding, and the surface of the high-k film 24 is modified to form a nitride layer 24a as a nitrogen-containing layer (FIG. 7D). In the plasma nitridation in this case, the plasma excitation power is increased and the processing time is longer than in the case described with reference to FIG. Here, the depth of the nitride layer 5a formed by plasma nitriding of the high-k film 5 is about 1.5 nm, and the nitrogen concentration on the surface of the nitride layer 24a is 30 at. As high as%.

Next, a silicon oxide film having a film thickness of about 2 nm is formed by, for example, a CVD method using silane gas and nitrous oxide (N ₂ O) gas as source gases, and the upper oxide film 25 is nitrided to the high-k film 24. It is formed on the layer 24a (FIG. 8A). In this silicon oxide film formation step, the composition of the nitride layer 24a is partially changed to a SiO film in the same manner as described in the formation of the silicon film 15 described in FIG. It has a function to prevent this.

  Next, a resist mask 26 is formed in the entire region corresponding to the memory circuit portion of the semiconductor device by a known photolithography technique. The resist mask 26 is used as an etching mask, and diluted with 0.2 vol% diluted hydrofluoric acid with pure water. The upper oxide film 25 formed in a region corresponding to the internal circuit portion is removed by exposing the surface of the nitride layer 24a of the internal circuit portion (FIG. 8B). Here, as described above, the nitrogen concentration on the surface of the nitride layer 24a is 30 at. When it is approximately%, the etching resistance to the diluted hydrofluoric acid is high, and the nitride layer 24a completely protects the High-k film 24 from etching in the wet etching process.

  Subsequently, the resist mask 26 is removed and the silicon substrate 21 is cleaned. In this cleaning process, it is preferable to use a chemical solution such as APM, SPM, or HPM described above.

  Next, a silicon film is deposited on the entire surface in the same manner as described in FIG. 3C of the first embodiment, and after introducing conductive impurities into the silicon film by ion implantation and heat treatment, a known photolithography technique and The silicon film, the upper oxide film 25, the high-k film 24, the base film 23, and the like are sequentially patterned by using an etching technique to form a polycrystalline silicon layer 27 constituting the gate portion of the MISFET, and the first gate insulating film 26. Then, the second gate insulating film 32 is formed (FIG. 8C).

  Thereafter, as described with reference to FIG. 6, ions of desired impurities are implanted in a self-aligning manner using the polycrystalline silicon layer 27 as a mask to form extension layers in the source / drain regions. Then, a sidewall insulating film 30 made of a silicon oxide film or a silicon nitride film is formed by a well-known method, and desired impurities are ion-implanted in a self-aligning manner using the polycrystalline silicon layer 27 and the sidewall insulating film 30 as a mask. To form a source / drain diffusion layer 31. Thereafter, the silicide layer 28 is formed on the polycrystalline silicon layer 27 and the source / drain diffusion layer 31 using the salicide technique.

  Hereinafter, although not shown, an interlayer insulating film and wiring are formed to form an n-channel or p-channel MISFET. In the MISFET constituting the memory circuit of the semiconductor device manufactured as described above, the first gate insulating film 26 having a converted film thickness of about 2 nm is formed. In the MISFET forming the logic circuit of the semiconductor device, the converted film thickness is reduced. A second gate insulating film 32 of 1 nm or less is formed. Then, MISFETs having gate insulating films having different electrical thicknesses are formed on the silicon substrate 21.

  In the second embodiment, instead of the upper oxide film 25, a high dielectric constant insulating film different from the high-k film 24 may be stacked on the high-k film 24. Alternatively, a metal nitride film or a silicon nitride film may be formed in place of the upper oxide film 25. Here, examples of the metal nitride film include an HfON film and an AlN film.

  In the second embodiment, unlike the first embodiment, gate insulating films having different equivalent film thicknesses are formed by depositing the upper oxide film 25. Here, since it becomes easy to use an insulating film having a high relative dielectric constant as the upper oxide film 25, a MISFET having a gate insulating film having a smaller equivalent film thickness than that of the first embodiment can be easily manufactured. . The effects described in the first embodiment are produced in exactly the same way.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and design changes and the like within a scope not departing from the gist of the present invention are possible. Even if it exists, it is included in this invention. For example, the method of the present invention may be applied to a MISFET having a so-called damascene gate electrode structure in which the gate electrode is buried in the opening of the interlayer insulating film after the source / drain diffusion layer of the MISFET is formed.

  The gate insulating films having different electrical thicknesses may be three or more types of gate insulating films having different electrical thicknesses. In the case of forming three or more types of gate insulating films, in the first embodiment, the base oxide film 4 can be easily formed by forming two or more types of film thicknesses. In the second embodiment, the same problem can be dealt with by using two or more types of upper oxide films 25.

As the metal oxide film used for the High-k film, oxide films of lanthanoid elements such as La ₂ O ₃ and Y ₂ O ₃ , tantalum oxide films, hafnium oxide films, zirconium oxide films, strontium titanate films (STO) Film), a high dielectric constant insulating film such as a barium strontium titanate film (BST film), or a ferroelectric film such as a lead zirconate titanate film (PZT film).

As the metal silicate film used for the high-k film, in addition to the hafnium silicate film or the zirconium silicate film described in the embodiment, a silicate film of a lanthanoid element such as La ₂ O ₃ or Y ₂ O ₃ or a high A silicate film of a melting point metal, or a silicate film in which these silicate films are combined may be used.

As the metal aluminate film used for the high-k film, in addition to the hafnium aluminate film or the zirconium aluminate film described in the embodiment, aluminum of a lanthanoid element such as La ₂ O ₃ or Y ₂ O _{3 is used.} An aluminate film or a refractory metal aluminate film, or a composite film of these aluminate films may be used. Alternatively, a composite film of a silicate film and an aluminate film can be used.

  Furthermore, in addition to the case where a semiconductor device is formed on a silicon substrate, the present invention can be similarly applied to the case where a MISFET is formed on a compound semiconductor substrate such as a GaAs substrate or a GaN substrate.

It is sectional drawing of the semiconductor device concerning Embodiment 1 of this invention. It is element sectional drawing according to process which shows the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. FIG. 3 is a cross-sectional view by process following the process illustrated in FIG. 2. FIG. 6 is a concentration distribution diagram of nitrogen in the base film formed in the embodiment of the present invention. It is a graph for demonstrating the effect of embodiment of this invention. It is sectional drawing of the semiconductor device concerning the 2nd Embodiment of this invention. It is element sectional drawing according to process which shows the manufacturing method of the semiconductor device concerning the 2nd Embodiment of this invention. FIG. 8 is a cross-sectional view by process following the process illustrated in FIG. 7. It is element sectional drawing according to process which shows the manufacturing method of the semiconductor device for demonstrating the prior art. It is element sectional drawing according to process which shows the manufacturing method of the semiconductor device for demonstrating the prior art.

Explanation of symbols

1, 21 Silicon substrate 2 N well layer 3, 22 Element isolation region 4 Base oxide film 4a, 5a, 12a, 23a, 24a Nitride layer 5, 24 High-k film 6, 26 First gate insulating film 7, 27 Polycrystal Silicon layer 8, 28 Silicide layer 9, 29 Gate electrode 10, 30 Side wall insulating film 11, 31 Source / drain diffusion layer 12, 23 Base film 13, 32 Second gate insulating film 14, 26 Resist mask 15 Silicon film 25 Upper part Oxide film

Claims (5)

A semiconductor device comprising an insulated gate field effect transistor in which gate insulating films having different electrical thicknesses are formed on the same semiconductor substrate,
A structure in which a first oxide film whose surface is modified to a nitrogen-containing layer and a high dielectric constant insulating film whose surface is modified to a nitrogen-containing layer are stacked in this order on the semiconductor substrate. An insulated gate field effect transistor having a first gate insulating film comprising;
A second oxide film formed on the semiconductor substrate, the surface of which is thinner than the thickness of the first oxide film, and whose surface is modified to a nitrogen-containing layer; An insulated gate field effect transistor having a second gate insulating film comprising a structure in which a dielectric constant insulating film is laminated in this order;
A semiconductor device comprising: A semiconductor device comprising an insulated gate field effect transistor in which gate insulating films having different electrical thicknesses are formed on the same semiconductor substrate,
A first oxide film formed on the semiconductor substrate, the surface of which is modified to a nitrogen-containing layer, a high dielectric constant insulating film whose surface is modified to a nitrogen-containing layer, and the first oxide film An insulated gate field effect transistor having a first gate insulating film including a structure in which a second oxide film thicker than the first oxide film is stacked in this order;
An insulated gate field effect transistor having a second gate insulating film comprising a structure in which the first oxide film and the high dielectric constant insulating film are stacked in this order;
A semiconductor device comprising: The pre-high dielectric constant insulating film is selected from the group consisting of hafnia (HfO ₂ ), zirconia (ZrO ₂ ), hafnium silicate (HfSiOx), zirconium silicate (ZrSiOx), hafnium aluminate (HfAlOx), and zirconium aluminate (ZrAlOx). 3. The semiconductor device according to claim 1, wherein the semiconductor device is at least one kind of insulating film. A method of manufacturing a semiconductor device comprising an insulated gate field effect transistor in which gate insulating films having different electrical thicknesses are formed on the same semiconductor substrate,
Forming a first oxide film on the surface of the semiconductor substrate;
Protecting the first oxide film in the region where the first gate insulating film is to be formed with a mask and selectively etching away the first oxide film in the region where the second gate insulating film is to be formed;
Forming a second oxide film having a thickness smaller than that of the first oxide film in a region where the second gate insulating film is to be formed after removing the mask;
Nitriding the first oxide film and the second oxide film to reform the first oxide film surface and the second oxide film surface into a nitrogen-containing layer;
Forming a high dielectric constant insulating film covering the first oxide film and the second oxide film;
Nitriding the high dielectric constant insulating film and modifying the surface of the high dielectric constant insulating film to a nitrogen-containing layer;
Have
A first gate insulating film is formed by a laminated film of the first oxide film and the high dielectric constant insulating film, and a second gate insulating film is formed by the laminated film of the second oxide film and the high dielectric constant insulating film. Forming a semiconductor device. A method of manufacturing a semiconductor device comprising an insulated gate field effect transistor in which gate insulating films having different electrical thicknesses are formed on the same semiconductor substrate,
Forming a first oxide film on the surface of the semiconductor substrate;
Nitriding the first oxide film to modify the surface of the first oxide film into a nitrogen-containing layer;
Forming a high dielectric constant insulating film covering the first oxide film;
Nitriding the high dielectric constant insulating film and modifying the surface of the high dielectric constant insulating film to a nitrogen-containing layer;
Forming a second oxide film covering the high dielectric constant insulating film;
Protecting the second oxide film in a region where the first gate insulating film is to be formed with a mask and selectively etching away the second oxide film in the region where the second gate insulating film is to be formed;
Have
A first gate insulating film is formed by a laminated film of the first oxide film, the high dielectric constant insulating film, and the second oxide film, and the laminated film of the first oxide film and the high dielectric constant insulating film is used. A method for manufacturing a semiconductor device, comprising forming a second gate insulating film.

Images