CN113396470A

CN113396470A - Hydrogenation and nitridation processes for improving the effective oxide thickness of a film

Info

Publication number: CN113396470A
Application number: CN201980088031.8A
Authority: CN
Inventors: 厚达·格兰欧; 约翰内斯·F·斯温伯格; 刘炜; 史蒂文·C.H·洪
Original assignee: Applied Materials Inc
Current assignee: Applied Materials Inc
Priority date: 2019-01-09
Filing date: 2019-10-18
Publication date: 2021-09-14
Also published as: KR20230120647A; JP2022518386A; TW202145372A; WO2020146030A1; KR102553773B1; JP7439101B2; TWI777717B; TWI739176B; TW202027171A; KR20210102465A

Abstract

Embodiments described herein generally relate to the ability to form metal gate structures having reduced effective oxide thicknesses compared to similar structures formed via conventional methods. A plasma hydrogenation process followed by a plasma nitridation process, or a single-step plasma hydrogenation and nitridation process, is performed on the metal nitride layer in the film stack, thereby removing oxygen atoms disposed within the layers of the film stack, and in some embodiments, adding nitrogen atoms to the layers of the film stack, according to some embodiments. Thus, the effective oxide thickness of the metal gate structure is reduced with little or no attendant flat band voltage shift.

Description

Hydrogenation and nitridation processes for improving the effective oxide thickness of a film

Technical Field

Embodiments described herein relate generally to a method and apparatus for processing a semiconductor substrate and, more particularly, to a hydrogenation and nitridation process that improves the effective oxide thickness of a film.

Background

In integrated circuits, there is a great need for smaller transistors such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). First, smaller transistors enable more transistors to be formed in a given chip area, thereby reducing chip size. Second, smaller transistors can generally switch faster than larger transistors, thereby improving chip performance.

One approach for reducing the size of MOSFETs is scaling, where important device dimensions, such as transistor length, transistor width, and oxide (or dielectric) thickness, are scaled down. In this approach, the transistor channel resistance does not change as the transistor size decreases, while the transistor gate capacitance and RC delay decrease proportionally as the size decreases.

However, while the reduction of dielectric thickness in MOSFETs is critical to scaling MOSFETs to the dimensions required for future technology nodes, there is also an important trade-off. In particular, as the thickness of conventional oxide/oxynitride dielectric layers in MOSFETs linearly decreases, there is an exponential increase in gate leakage, resulting in increased power consumption. Furthermore, the thickness of the dielectric layer is now close to a few atomic layers, creating reliability problems. Therefore, any way in which the oxide thickness or Effective Oxide Thickness (EOT) in a transistor can be reduced without an exponential increase in gate leakage is highly desirable. This need and other needs are addressed in the present disclosure.

Disclosure of Invention

Embodiments described herein generally relate to sequential hydrogenation and nitridation processes for reducing interfacial and bulk O atoms in conductive structures in semiconductor devices. In one embodiment, a method of forming a structure in a semiconductor device is provided, the method comprising: depositing a high dielectric constant dielectric layer on a semiconductor substrate; depositing a capping layer over the high-k dielectric layer to form a portion of the structure, the deposited capping layer having an exposed surface; and exposing the exposed surface to plasma excited hydrogen species and plasma excited nitrogen species. Portions of the substrate include a capping layer and a high dielectric constant dielectric.

In one embodiment, a method of forming a structure in a semiconductor device includes: depositing a high dielectric constant dielectric layer on a semiconductor substrate; depositing a metal nitride layer on the high-k metal dielectric layer to form a portion of the structure, wherein the portion comprises the metal nitride layer and the high-k metal dielectric layer and has a first effective oxide thickness, and wherein the deposited metal nitride layer has an exposed surface; the exposed surface is sequentially exposed to non-oxidizing plasma-excited hydrogen species followed by plasma-excited nitrogen species to reduce the first effective oxide thickness to a second effective oxide thickness.

In another embodiment, a method of forming a structure in a semiconductor device includes: depositing a high dielectric constant dielectric layer on a semiconductor substrate; depositing a metal nitride layer on the high-dielectric-constant metal dielectric layer; sequentially exposing the exposed surface to plasma-excited hydrogen species followed by plasma-excited nitrogen species; exposing the exposed surface to air after sequentially exposing the exposed surface to plasma-excited hydrogen species followed by plasma-excited nitrogen species; and performing a thermal annealing process on the high-k dielectric layer and the metal nitride layer at a specific temperature for a specific time after exposing the exposed surface to air.

In another embodiment, a method of forming a structure in a semiconductor device includes: depositing a high dielectric constant dielectric layer on a semiconductor substrate; depositing a metal nitride layer on the high-k metal dielectric layer to form a portion of the substrate, wherein the portion comprises the metal nitride layer and the high-k metal dielectric layer and has a first effective oxide thickness, and wherein the deposited metal nitride layer has an exposed surface; the first effective oxide thickness is reduced to a second effective oxide thickness by sequentially exposing the exposed surface to a non-oxidizing plasma-excited hydrogen species followed by a plasma-excited nitrogen species.

In another embodiment, a method of forming a structure in a semiconductor device is provided, the method comprising: depositing a high dielectric constant dielectric layer on a semiconductor substrate; depositing a cover layer on the high-dielectric-constant metal dielectric layer; exposing the exposed surface of the capping layer to plasma-excited hydrogen species and plasma-excited nitrogen species; exposing the exposed surface to air; and performing a thermal annealing process on the high-k dielectric layer and the capping layer at a specific temperature for a specific time.

In another embodiment, a method of forming a structure in a semiconductor device is provided, the method comprising: depositing a high dielectric constant dielectric layer on a semiconductor substrate; depositing a capping layer on a high-k dielectric layer to form a structureA portion wherein the deposited capping layer has an exposed surface; and exposing the exposed surface to plasma excited hydrogen species and plasma excited nitrogen species, wherein the plasma excited hydrogen species comprise ammonia and the plasma excited nitrogen species comprise nitrogen gas (N)₂). The portion of the structure includes a capping layer and a high dielectric constant dielectric.

In another embodiment, a method of forming a structure in a semiconductor device is provided, comprising: depositing a metal nitride capping layer on the high-k dielectric layer formed over the substrate surface; and exposing the exposed surface of the deposited metal nitride cap layer to a plasma comprising a first gas comprising a hydrogen-containing species and a second gas comprising a nitrogen-containing species, wherein the hydrogen-containing species in the first gas comprises nitrogen.

In another embodiment, a method of forming a structure in a semiconductor device is provided, comprising: depositing a high dielectric constant dielectric layer on a semiconductor substrate; depositing a capping layer on the high-k dielectric layer; exposing the exposed surface of the capping layer to plasma-excited hydrogen species and plasma-excited nitrogen species; exposing the exposed surface to air; and performing a thermal annealing process on the high-k dielectric layer and the capping layer at a specific temperature for a specific time.

In another embodiment, a method of forming a structure in a semiconductor device is provided, comprising: depositing a high dielectric constant dielectric layer on a semiconductor substrate; depositing a capping layer on the high-k dielectric layer to form a portion of the structure, wherein the portion comprises the capping layer and the high-k dielectric layer, and wherein the deposited capping layer has an exposed surface; and exposing the exposed surface to plasma excited hydrogen species and plasma excited nitrogen species, wherein the plasma excited hydrogen species comprise ammonia and the plasma excited nitrogen species comprise nitrogen gas (N)₂)。

Drawings

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

Fig. 1 illustrates a cross-sectional view of a contact structure formed on a substrate as part of a semiconductor device according to an embodiment of the present disclosure.

Fig. 2A-2E are schematic diagrams of a metal nitride layer within the contact structure of fig. 1 at various stages of fabricating the contact structure, according to an embodiment of the present disclosure.

Fig. 3 is an X-ray Photoelectron Spectroscopy (XPS) spectrum 310 for a TiN film deposited and thermally annealed before processing and an XPS spectrum 320 for the same TiN film deposited and thermally annealed after processing, according to an embodiment of the present disclosure.

Fig. 4 is a cross-sectional side view of a processing chamber configured to implement one or more aspects of the present disclosure.

Fig. 5 is a top plan view of a multi-chamber processing system configured to implement one or more aspects of the present disclosure.

Fig. 6 illustrates a flow chart of process steps for reducing bulk and interfacial oxygen in a contact structure, according to some embodiments of the present disclosure.

Fig. 7A-7E are schematic cross-sectional views of a semiconductor device corresponding to different stages of the process of fig. 6, in accordance with various embodiments of the present disclosure.

Fig. 8 illustrates a flow chart of process steps for reducing bulk and interfacial oxygen in a contact structure, according to some embodiments of the present disclosure.

Fig. 9 illustrates a flow chart of process steps for reducing bulk and interfacial oxygen in a contact structure, according to some embodiments of the present disclosure.

Figure 10 illustrates a cross-sectional view of a metal gate structure formed in accordance with an embodiment of the present disclosure.

Figure 11 sets forth a flow chart of process steps for reducing Effective Oxide Thickness (EOT) in a metal gate structure according to various embodiments of the present disclosure.

Fig. 12A-12J are schematic cross-sectional views of a semiconductor device corresponding to different stages of the process of fig. 11, in accordance with various embodiments of the present disclosure.

Figure 13 illustrates a flow chart of processing steps for processing a metal gate structure with a single step hydrogenation and nitridation process according to various embodiments of the present disclosure.

Fig. 14A-14J are schematic cross-sectional views of a semiconductor device corresponding to different stages of the process of fig. 13, in accordance with various embodiments of the present disclosure.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

Detailed Description

Embodiments described herein generally relate to methods and apparatus for a nitride layer in a structure within a semiconductor device formed on a substrate. The single-step plasma hydrogenation and nitridation process may be performed on a metal layer or a stack of metal layers included in the conductive structure, such as a metal layer that is thermally annealed prior to depositing the metal cap layer. In various embodiments, a single-step plasma hydrogenation and nitridation process may be performed before the thermal annealing process, after the thermal annealing process, or both before and after the thermal annealing process. In various embodiments, the concentration of nitrogen atoms in the conductive structure is advantageously increased, thereby reducing the resistance in the conductive structure. One such conductive structure is shown in fig. 1.

Conductive structures with reduced interfacial and bulk oxygen

Fig. 1 illustrates a cross-sectional view of a conductive structure 100 or contact structure formed on a semiconductor substrate 110 as part of a semiconductor device, according to an embodiment of the present disclosure. The conductive structure 100 may be any portion of a semiconductor device configured to conduct current and thereby benefit from reduced resistance. In the embodiment shown in fig. 1, the conductive structure 100 is depicted as a contact structure for providing electrical contact to the source or drain structure 101, and is illustrated after the conductive structure 100 has been formed, and a planarization process, such as chemical-mechanical polishing (CMP), has been completed on the semiconductor substrate 110. For example, the conductive structure 100 may be a contact structure for a Field Effect Transistor (FET).

The conductive structure 100 is disposed in a contact well 109 or a hole, which is a cavity formed in an insulating material 120. The insulating material 120 (alternatively referred to as Shallow Trench Isolation (STI)) may include one or more dielectric materials, such as silicon dioxide (SiO)₂) Silicon nitride (Si)₃N₄) Or multiple layers of each of the foregoing. The insulating material 120 may be formed by high-density plasma (HDP), Flowable Chemical Vapor Deposition (FCVD), Tetraethylorthosilicate (TEOS), or the like. The conductive structure 100 may include a stack of multiple metal layers, for example, a first metal layer 102, a metal nitride layer 103, and at least one conductive portion disposed over the first metal layer 102 and the metal nitride layer 103. The conductive portion may include a cover layer 104 and/or a conductive layer 106.

The source or drain structure 101 may be formed from the semiconductor substrate 110 or from a different semiconductor material deposited on the semiconductor substrate 110. In the latter case, the different semiconductor material may include silicon germanium, a group III-V compound semiconductor material, or the like. For example, in some embodiments, an epitaxial process may be performed to grow the source or drain structure 101.

A first metal layer 102 is formed on the source or drain structure 101 and comprises one or more metals selected to form a silicide 105 at the interface with the source or drain structure 101 after an appropriate thermal annealing process. For example, in some embodiments, first metal layer 102 comprises or consists entirely of titanium (Ti), and may have a thickness of about

To about

Is measured. Metal nitride layer 103 is formed on first metal layer 102 and comprises a metal nitride, for example, to serve as a diffusion barrier in conductive structure 100. In some embodiments, the metal nitride layer 103 includes titanium nitride (TiN), tantalum nitride (TaN), and/or tungsten nitride (W)₃N₂) And may have an approximate

To

Is measured. A capping layer 104 is typically formed on the metal nitride layer 103 after a thermal annealing process by which a silicide 105 is formed in the conductive structure 100 and comprises one or more metals. In some embodiments, the conductive structure 100 can include a separately formed conductive layer 106, which can include a metal, such as cobalt, copper, ruthenium, nickel, tungsten, aluminum, or other useful metals, or combinations thereof. In some embodiments, the capping layer 104 comprises Co, and may have a thickness of about

To

Is measured. In other embodiments, the capping layer 104 comprises a metal (e.g., cobalt) that completely fills the remaining portion of the contact well 109.

As previously mentioned, the presence of O atoms in the first metal layer 102 and/or the metal nitride layer 103 adversely affects the effective conductivity of the conductive structure 100. First, oxides in any metal layer increase the bulk conductivity of the formed metal layer. Second, interfacial oxides (i.e., metal oxides formed at the interface between the metal nitride layer 103 and the capping layer 104) exacerbate poor adhesion between the metal nitride layer 103 and the capping layer 104, potentially resulting in voids that significantly reduce the effective cross-sectional area of the conductive structure 100. Unfortunately, a somewhat low concentration of O atoms is almost always present in the bulk portion of the metal layer of the conductive structure 100. In addition, in many cases, oxides can form at higher concentrations on metal surfaces that are exposed to air between fabrication steps. According to embodiments of the present disclosure, the presence of bulk and interfacial O atoms in the conductive structure 100 may be reduced via sequential hydrogenation and plasma nitridation processes. A solid model of the degree to which bulk and interfacial O atoms in the conductive structure 100 are reduced for sequential processing is shown in fig. 2A-2E and 3A-3D.

Solid model for reducing interface and bulk oxygen

Fig. 2A-2E are schematic diagrams of the metal nitride layer 103 within the contact structure 100 at various stages of fabricating the contact structure 100, according to an embodiment of the present disclosure. It should be noted that fig. 2A to 2E only show one possible surface end of the metal nitride layer 103 and only represent a typical TiN structure. In some embodiments, the metal nitride layer 103 may have any other possible surface termination or crystal structure associated with a TiN layer.

In fig. 2A, a portion 200 of the metal nitride layer 103 is schematically shown immediately after the metal nitride layer 103 has been deposited on the first metal layer 102 and before exposing the portion 200 to air. Portion 200 includes a surface 201 of portion 200 on which capping layer 104 will ultimately be deposited. As shown, portion 200 has a NACl cubic structure and is composed primarily of Ti and N atoms. Further, portion 200 includes a low concentration of bulk O atoms 211 (cross-hatched) disposed generally in the bulk region of portion 200 below surface 201. The bulk O atoms 211 may be entrained by contamination found in the processing environment during the deposition process used to form the portion 200. In addition, the portion 200 generally includes vacancies 213, which are sites within the crystal lattice of the portion 200 in which atoms are being lost. Vacancies 213 are sites where additional oxidation may occur within portion 200 when nitride layer 103 is exposed to air. It is noted that when the metal nitride layer 103 is formed by an Atomic Layer Deposition (ALD) process, the vacancy 213 is relatively common with respect to a conventional Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) process due to film nucleation and growth mechanisms found in the ALD process. Thus, one or more embodiments of the disclosure provided herein may provide significant benefits when used on films formed by ALD processes relative to conventional PVD or CVD type processes.

In fig. 2B, the portion 200 is shown after removal from the processing system that deposited the metal nitride layer 103. For example, in preparation for the thermal annealing process, the semiconductor substrate 110 on which the portion 200 is formed may be exposed to air. Typically, conventional thermal processing chambers (e.g., annealing processing chambers) are implemented in processing systems different from those used to form the first metal layer 102 and the metal nitride layer 103 due to differences in required cleanliness, thermal management control, and vacuum requirements required to form most of the current advanced device node applications. Thus, in fig. 2B, the portion 200 is shown after exposure to air. As shown, surface 201 has been partially oxidized, with surface O atoms 212 occupying most or all of the vacancies 213 disposed on surface 201. In some cases, some of the vacancies 213 disposed within portion 200 are occupied by bulk O atoms 211 as a result of exposing portion 200 to air.

In fig. 2C, the portion 200 is shown after undergoing a thermal annealing process to form the silicide 105 (shown in fig. 1). Some or all of the remaining vacancies 213 are filled with bulk O atoms 211 or surface O atoms 212. In some embodiments, the bulk O atoms 211 may also displace (place) a portion of the N atoms disposed within the portion 200. Thus, the annealing process generally increases the number of both bulk O atoms 211 and surface O atoms 212 in the portion 200. Even when the depth of the surface O atoms 212 on the surface 201 is only one or two monolayers, the effect on the resistivity of the conductive structure 100 can be significant, particularly for smaller device structures, such as those associated with advanced device nodes (e.g., 65nm technology nodes and below).

In fig. 2D, the portion 200 is shown after exposure to hydrogen atoms that react with the bulk O atoms 211 and/or the surface O atoms 212 included in the portion 200, according to various embodiments of the present disclosure. In some embodiments, the bulk O atoms 211 and/or surface O atoms 212 are reacted with hydrogen (H) from thermal dissociation as part of a thermal hydrogenation process₂) While in other embodiments, the bulk O atoms 211 and/or surface O atoms 212 react with hydrogen atoms from a hydrogen-containing plasma as part of the plasma hydrogenation process.

The thermal hydrogenation process may be performed in a suitable rapid thermal processing chamber under certain processing conditions, including heating the portion 200 to at least about 550 ℃ to about 650 ℃. The plasma hydrogenation process may be performed in a suitable plasma processing chamber under certain processing conditions. Each of the exemplary plasma processing chambers and plasma processing conditions are described below with respect to a plasma hydrogenation process. As shown, the hydrogenation process reduces or otherwise removes all or substantially all of the surface O atoms 212 from the surface 201, leaving vacancies 213. In addition, the plasma hydrogenation process may also remove some or all of the bulk O atoms 211 disposed below the surface 201.

In fig. 2E, portion 200 is shown after undergoing a plasma nitridation process in accordance with various embodiments of the present disclosure. The plasma nitridation process may be performed in a suitable plasma processing chamber under certain processing conditions, and exemplary plasma processing chambers and plasma processing conditions are each described below with respect to the plasma nitridation process. In some embodiments, the plasma nitridation process may be performed in the same plasma processing chamber in which the plasma hydrogenation process is performed. Furthermore, no air break (air break) occurs between the plasma or thermal hydrogenation process and the plasma nitridation process. That is, portion 200 is not exposed to air after the plasma or thermal hydrogenation process and prior to the plasma nitridation process.

As shown, the nitridation process results in filling vacancies 213 with N atoms such that there are very few or no surface O atoms 212 disposed on surface 201. Thus, the surface 201 may reach N atom saturation, and thus, subsequent oxidation of the surface 201 is substantially reduced or eliminated, even when the surface 201 is again exposed to air prior to depositing the capping layer 104. Thereby, the adhesion between the surface 201 of the metal nitride layer 103 and the capping layer 104 is improved. Furthermore, some or all of the vacancies below the surface 201 may be filled with N atoms instead of the bulk O atoms 211, thereby further improving the conductivity of the metal nitride layer 103, the first metal layer 102, and the conductive structure 100 as a whole.

Fig. 3 is an X-ray photoelectron spectroscopy (XPS) spectrum 310 for a deposited and thermally annealed TiN film before processing and an XPS spectrum 320 for the same deposited and thermally annealed TiN film after processing, according to an embodiment of the present disclosure. The treatment includes a plasma or thermal hydrogenation process followed by a plasma nitridation process. The thermal annealing process is conducted at a temperature between about 550 ℃ and 600 ℃ in nitrogen (N)₂) Or ammonia (NH)₃) Rapid thermal process in the environment. H between about 5sccm and 100sccm at a temperature between about 340 ℃ and 500 ℃, at a process pressure between about 10mTorr and 150mTorr, at a plasma power between about 250W and 2000W₂The plasma hydrogenation process is performed in an Inductively Coupled Plasma (ICP) chamber on the substrate pedestal at a flow rate (flow rate) and at an argon (Ar) flow of between about 250sccm and 2000sccm for a duration of between about 30 seconds and about 200 seconds. NH between about 5sccm and 100sccm on a substrate pedestal at a temperature between about 350 ℃ and 500 ℃, at a process pressure between about 10mTorr and 100mTorr, at a plasma power between about 250W and 2000W, at a temperature between about 5sccm and 100sccm₃Nitrogen gas (N) at a flow rate between about 300sccm and 500sccm₂) The plasma nitridation process may be performed in the same ICP chamber at a flow rate of between about 20 seem and 500 seem of argon (Ar) for a duration of between about 30 seconds and about 200 seconds.

As is well known in the art, the XPS spectrum of a TiN film may include multiple peaks, each indicating a different relative concentration of different titanium-containing materials. For example, a Ti-O peak having a binding energy of about 458.5eV generally indicates the presence of Ti-O bonds, and thus, the presence of O atoms in the titanium-containing material; the Ti-O-N peak having a binding energy of about 457eV generally indicates the presence of Ti-O-N bonds and, thus, the presence of N atoms and O atoms in the titanium-containing material; and a Ti-N peak having a binding energy of about 454.9eV generally indicates the presence of Ti-N bonds, and thus, the presence of nitrogen (N) atoms in the titanium-containing material.

The XPS spectrum 310 is associated with the Ti 2p shell for TiN deposited films after the thermal annealing process described above is performed thereon, and the XPS spectrum 320 is associated with the Ti 2p shell for TiN deposited and thermally annealed films after undergoing the plasma hydrogenation process described above, followed by the plasma nitridation process described above. As shown, the peak indicating the presence of Ti-O bonds and the peak indicating the presence of Ti-O-N bonds were significantly lower in XPS spectrum 320 than in XPS spectrum 310, clearly indicating a reduction in the presence of O atoms in the TiN film. Further, the peak indicating the presence of Ti — N bonds was significantly higher in XPS spectrum 320 than in XPS spectrum 310, clearly indicating an increase in the concentration of N atoms in the TiN film. Therefore, by performing the hydrogenation and nitridation processes after the annealing process, the concentration of O atoms in the metal nitride film 103 may be significantly reduced, and the concentration of N atoms in the metal nitride film 103 may be significantly increased.

Fig. 2A to 2E and fig. 3 show the effect of the continuous hydrogenation and nitridation process on the metal nitride layer 103 after annealing. In some embodiments, employing a plasma or thermal hydrogenation process on portion 200 prior to the thermal annealing process, followed by a plasma nitridation process may have similar beneficial effects. Specifically, because the surface 201 may be mostly or entirely saturated with N atoms due to the plasma nitridation process (as shown in fig. 2E), the subsequent air exposure and thermal annealing of the surface 201 results in little or no oxidation. Thus, the concentration of bulk O atoms 211 and the concentration of surface O atoms 212 on surface 201 found in portion 200 are not significantly increased.

Overview of the System for sequential hydrogenation and nitridation

FIG. 4 is a block diagram configured to implement the present disclosureA schematic cross-section of a plasma processing chamber 400 in one or more aspects. The plasma processing chamber 400 may be any suitable plasma processing chamber, such as an Inductively Coupled Plasma (ICP) processing chamber. As shown in fig. 4, the processing chamber 400 may include chamber walls 406, a chamber lid 408, and a substrate support pedestal 404 disposed within the chamber walls 406. Typically, the chamber wall 406 is coupled to an electrical ground 416. The chamber lid 408 may be constructed of any suitable dielectric, such as quartz. For some embodiments, the dielectric cover 408 may assume a different shape (e.g., a dome shape). In some embodiments, chamber lid 408 may be coated with a ceramic coating (e.g., yttrium-containing oxide) for protection against plasma species. In one embodiment, the ceramic coating is a High Performance Material (HPM) composed of Y₄Al₂O₉Compound and solid solution Y_2-xZr_xO₃(Y₂O₃-ZrO₂Solid solution). The ceramic coating may have a thickness in a range from about 100 microns to about 300 microns, such as about 200 microns.

Above the chamber lid 408, a Radio Frequency (RF) antenna (two coaxial coil elements are illustrated) may be provided that includes at least one inductive coil element 410. In some embodiments, the inductive coil element 410 may be disposed around at least a portion of the chamber wall 406. One end of the inductive coil element 410 may be coupled to an RF power source 414 via a first impedance match network 412 and the other end may be connected to an electrical ground 417 as shown. The power supply 414 is typically capable of generating up to 10 kilowatts (kW) of power at a tunable frequency ranging from 2 to 160MHz, with 13.56MHz being a typical operating frequency. The RF power supplied to the inductive coil element 410 may be pulsed (i.e., switched between on and off states) or power cycled (i.e., varying the power input from a high level to a low level) with a frequency in the range from 1 to 100 kHz.

The shield electrode 418 may be inserted between the inductive coil element 410 and the chamber wall 408 of the RF antenna. The shield electrode 418 may alternately be electrically floating or coupled to an electrical ground 419 via any suitable means for making and breaking an electrical connection, such as the switch 420 shown in fig. 4.

For some embodiments, a detector 422 may be attached to the chamber wall 406 to facilitate determining when to excite the gas mixture within the chamber 400 into a plasma. For example, the detector 422 may detect radiation emitted by the excited gas or use Optical Emission Spectroscopy (OES) to measure the intensity of one or more wavelengths of light associated with the generated plasma.

The base 404 may be coupled to a bias power supply 426 via a second impedance matching network 424. Similar to the RF power supply 414, the bias power supply 426 is generally capable of generating an RF signal having a tunable frequency in the range from 2 to 160MHz and a power between 0 and 10 kW. Alternatively, the bias power supply 426 may be a Direct Current (DC) or pulsed DC source.

In operation, a substrate 428 (e.g., a semiconductor substrate) may be placed on the pedestal 404, and process gases may be supplied from the gas panel 430 via the inlet port 432 in an effort to form a gas mixture 434. Typical process gases that may be used in one or more of the processes described herein are described below. The inlet port 432 may be coated with a ceramic coating (e.g., HPM). The gas mixture 434 may be excited into a plasma 436 in the process chamber 400 by applying power from the RF power source 414. The pressure within the interior volume of the processing chamber 400 may be controlled using the throttle valve 438 and the vacuum pump 440. In some embodiments, the temperature of the chamber walls 406 may be controlled using liquid-containing tubing (not shown) that travels through the chamber walls 406 or heating elements embedded in the chamber walls 406 (e.g., heating cartridges or coils) or wrapped around the process chamber 400 (e.g., heater wrap or tape).

The temperature of the substrate 428 may be controlled by stabilizing the temperature of the pedestal 404. In some embodiments, helium (He) gas from a gas source 442 may be provided to a channel (not shown) formed in a pedestal surface below the substrate 428 via a gas conduit 444. The helium gas may facilitate heat transfer between the base 404 and the substrate 428. During processing, the pedestal 404 may be heated to a steady state temperature, and the helium gas may then facilitate uniform heating of the substrate 428. The base may be so heated by a heating element (not shown), such as a resistive heater embedded within the base 404, or a lamp generally aimed at the base 404 or a substrate 428 thereon. With such thermal control, the substrate 428 may be maintained at a temperature between about 20 degrees Celsius and 350 degrees Celsius (C.).

To allow control of the components of the process chamber 400 as described herein, a controller 446 may be provided. The controller 446 may include a Central Processing Unit (CPU) 448, a memory 450, and support circuits 452 for the CPU 448. The controller 446 may interface with the RF power supply 414, the switch 420, the detector 422, and the bias power supply 426.

The controller 446 may be any suitable type of general purpose computer processor that may be used in an industrial environment for controlling various chambers and sub-processors. Memory 450, or other computer-readable medium for CPU 448, may be one or more of any readily available form of memory, such as Random Access Memory (RAM), Read Only Memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The support circuits 452 can be coupled to the CPU 448 in an effort to support the processor in a conventional manner. These circuits may include cache (cache), power supplies, clock circuits, input/output (I/O) circuitry and subsystems, and the like. For some embodiments, the techniques for energizing and sustaining a plasma disclosed herein may be stored in memory 450 as a software program. The software routine may also be stored and/or executed by a second CPU (not shown) that is remotely located from the hardware being controlled by CPU 448.

According to some embodiments of the present disclosure, the thermal or plasma hydrogenation process is followed by a plasma nitridation process, hereinafter referred to as a "sequential hydrogenation/nitridation process," performed on the substrate before and/or after the thermal anneal is performed on the substrate. The sequential hydrogenation/nitridation process may include a capacitively coupled plasma process or an inductively coupled plasma process. In some embodiments, the plasma for the hydrogenation/nitridation process may be formed in a remote plasma source outside of the processing chamber 400, and in other embodiments, the plasma for the plasma process may be formed in situ, i.e., in the processing chamber 400. The hydrogenation and nitridation may be performed in the same step, hereinafter referred to as a "single-step plasma hydrogenation and nitridation process". In some embodiments, the plasma for the single-step plasma hydrogenation and nitridation processes may be formed in a remote plasma source external to the processing chamber 400, and in other embodiments, the plasma for the plasma processes may be formed in situ, i.e., in the processing chamber 400.

In the plasma hydrogenation process, plasma excited H radicals and/or ions react with the bulk O atoms 211 and/or the surface O atoms 212 to create vacancies 213. In the case of the thermal hydrogenation process, the dissociated H atoms react with the bulk O atoms 211 and/or the surface O atoms 212 to create vacancies 213. During the nitridation process, N radicals and/or ions occupy vacancies 213.

It is noted that during the plasma hydrogenation process, the processing environment within the processing chamber 400 typically includes a relatively low concentration of O atoms due to the presence of H atoms, such as dissociated H atoms, H radicals, and/or H ions. Thus, the processing environment within the processing chamber 400 during the plasma hydrogenation process may include a lower concentration of O atoms than the processing environment within the processing chamber 400 during the nitridation process or the processing environment within the processing chamber during the deposition of the metal nitride layer. However, for both hydrogenation or nitridation, lower concentrations of O atoms are generally advantageous. Thus, in some embodiments, the processing chamber may be used with a plasma process (e.g., H) prior to the plasma hydrogenation process and/or nitridation process₂Process) to remove any trace O species.

The metal nitride layer to be treated by the hydrogenation/nitridation process or the single-step plasma hydrogenation and nitridation process described herein has a thickness of about

Or less thick films, ICP processes are generally less prone to damage of the metal nitride layer during hydrogenation or nitridation. In particular, in ICP processes, the plasma sheath (plasma sheath) is typically smaller than in CCP chambers, and thus ions traveling therethrough typically have proportionally smaller energies, e.g., on the order of 10 eV, such as 10 to 20 eV. In contrast, ions in CCP chambers typically have energies on the order of 100 times eV (e.g., > 200-400eV), and can subsequently cause significant damage to the metal nitride layer. Furthermore, ICP processes may provide more oxygen removal from a metal nitride layer than by using CCP or remote plasma processes due to higher densities of ions, radicals, and other plasma excited species that are typically formed in ICP processing chambers and near the substrate relative to CCP and remote plasma sources used in other types of processing chambers. In contrast, the concentration of radicals from the CCP and the remote plasma source is relatively low.

In embodiments in which the plasma is formed in situ for the plasma process, the plasma may be formed via the inductive coil element 410, the first impedance match network 412, the RF power supply 414, and in some embodiments, via the second impedance match network 424 and the bias power supply 426. In such an embodiment, the plasma process may include introducing one or more process gases into the processing chamber 400, the process gases being selected to generate certain plasma species (i.e., ions, neutral atoms, and/or radicals). More specifically, in the case of a plasma hydrogenation process, the one or more process gases are selected to produce plasma excited hydrogen species, while in the case of a plasma nitridation process, the one or more process gases are selected to produce plasma excited nitrogen species. Thus, for a plasma hydrogenation process, the one or more process gases may include hydrogen (H)₂) And/or D₂And for a plasma nitridation process, the one or more process gases may include nitrogen (N)₂) Or ammonia (NH)₃). Alternatively or additionally, the plasma process may include introducing one or more carriers and/or inert gases, such as argon (Ar), into the processing chamber 400. For single step plasma hydrogenIn the nitridation and nitridation processes, the one or more process gases may include hydrogen (H)₂)、D₂Nitrogen (N)₂) Ammonia (NH)₃) Or hydrazine (N)₂H₄)。

In some embodiments, the plasma hydrogenation process consists essentially of forming a plasma comprising substantially hydrogen (H) gas₂) A process gas of composition that forms reactive species provided by the plasma. It will be noted that with the use of a catalyst containing H₂Compared to the thermal hydrogenation process of the process gas, a plasma (e.g., an inductively coupled plasma) using H is used₂Form) the hydrogen-containing species will have significantly more hydrogen-containing radicals and ions, thus improving the effectiveness of the plasma hydrogenation process and reducing the undesirable reactions found when using impure hydrogen-containing reactant gases.

In some embodiments, one or more process gases are energized by an RF power source (e.g., RF power source 414). The RF power may be pulsed at a duty cycle of 2% to 70% and may range from about 100W to about 2500W. The RF power may be a continuous wave ranging from about 100W to about 2500W. The processing chamber may have a chamber pressure ranging from about 10mTorr to about 200mTorr during the plasma process, while the processing temperature (e.g., the temperature of the pedestal 404) may range from 20 ℃ to about 500 ℃.

In an exemplary embodiment, the process temperature is between about 400 ℃ and about 500 ℃, the chamber pressure is between about 5mTorr and about 20mTorr, the RF power is between about 1000W and about 2000W, and the bias voltage is between about 175V and about 250V, where H is₂The plasma hydrogenation process is performed at a flow rate between about 20sccm and about 40sccm and an Ar flow rate between about 400sccm and about 500sccm for a duration between about 50 seconds and about 300 seconds. The hydrogen species excited by the plasma generated by the plasma inside the processing chamber 400 may reduce some or all of the oxide present on the exposed surfaces of the metal nitride layer (e.g., metal nitride layer 103) of the partially formed conductive structure (e.g., conductive structure 100). In some embodiments, plasma excited hydrogen species may also be reducedSome or all of the O atoms are present in less than the bulk material of the metal nitride layer (e.g., first metal layer 102 of conductive structure 100) or other metal layers of the conductive structure. Such reduction of O atoms is described above in connection with fig. 2D and 3B.

In another exemplary embodiment, the process temperature is between about 400 ℃ and about 500 ℃, the chamber pressure is between about 5mTorr and about 25mTorr, the RF power is between about 1000W and about 2000W, and the bias pressure is between about 175V and about 250V, wherein NH₃A flow rate between about 20sccm and about 40sccm, N₂The plasma nitridation process is performed at a flow rate of between about 400 seem and about 600 seem and an Ar flow rate of between about 400 seem and about 500 seem for a duration of between about 50 seconds and about 300 seconds. Nitrogen species excited by the plasma generated by the plasma inside the processing chamber 400 may saturate exposed surfaces of the metal nitride layer of the partially formed conductive structure (e.g., surface 201 of metal nitride layer 103). In some embodiments, the plasma-excited nitrogen species may also fill vacancies present in the host material of the metal nitride layer or other metal layer of the conductive structure. Such nitridation is described above in connection with fig. 2E and 3C.

In some embodiments, the NH is performed at a chamber pressure of between about 10mTorr and about 100mTorr, at a process temperature (e.g., substrate pedestal temperature) of between about 350 ℃ and about 500 ℃, with an RF power of between about 300W and about 2000W₃At a flow rate of between about 5sccm and about 100sccm, N₂Is at a flow rate of between about 50sccm and about 1000sccm, a helium (He) flow rate of between about 1 to about 1000sccm, performing a single-step plasma hydrogenation and nitridation process for a duration of between about 30 seconds and about 150 seconds, and applying a substrate bias, wherein the frequency is from about 2MHz to about 160MHz and the bias power is between about 0kW and about 10 kW.

In some embodiments, the process temperature is between about 350 ℃ and about 500 ℃ at a chamber pressure of between about 15mTorr and about 25mTorr, with RF power between about 300W and about 1600W, NH₃At a flow rate of between about 10sccm and about 40sccm, N₂With a flow rate of about 200sccm to about 550sccm, ArFrom about 200sccm to about 550sccm, perform a single-step plasma hydrogenation and nitridation process for a duration of between about 85 seconds and about 95 seconds, and apply no substrate bias power.

In embodiments where the plasma for the plasma process is formed remotely, the plasma may be formed via any technically feasible remote plasma source. In such embodiments, the plasma process may include introducing one or more process gases into the remote plasma source, the process gases selected to produce plasma-excited hydrogen species or plasma-excited nitrogen species. Alternatively or additionally, the remote plasma process may include introducing one or more carriers and/or an inert gas, such as argon (Ar), into the remote plasma source. The remotely generated plasma species then flow into the processing chamber 400 and process the metal nitride layer of the conductive structure formed on the substrate disposed in the processing chamber 400. As described above, interface and bulk O atoms in the metal nitride layer are reduced or nitridation of the metal nitride layer is enhanced depending on whether the plasma species is a plasma-excited hydrogen species or a plasma-excited nitrogen species.

In some embodiments, unlike a plasma hydrogenation process, a thermal hydrogenation process may be employed to expose the metal nitride layer to hydrogen atoms. In such embodiments, the thermal hydrogenation process typically occurs at an elevated temperature (e.g., between about 500 ℃ and about 650 ℃). At such high temperatures, H₂The gas dissociates into individual atoms that can subsequently react with O atoms in the metal nitride layer 103 and create vacancies 213. Furthermore, in such embodiments, the thermal hydrogenation process is typically performed in a different process chamber than process chamber 400. For example, in some embodiments, the thermal hydrogenation process is performed in a rapid thermal processing chamber. In such an embodiment, the silicidation process may be performed concurrently with the thermal hydrogenation process, thereby eliminating the subsequent annealing process.

In embodiments where a thermal annealing process is employed to expose the metal nitride layer to hydrogen atoms, the plasma nitridation process is performed without a break that exposes the metal nitride layer 103 to air. For example, in such an embodiment, one chamber of a multi-chamber processing system may be configured to perform a thermal hydrogenation process and another chamber of the same multi-chamber processing system may be configured to perform a plasma nitridation process. Thus, the substrate on which the metal nitride layer 103 is formed may undergo a thermal hydrogenation process and then be directly transferred to a plasma nitridation chamber without exposure to air.

Fig. 5 is a top plan view of a multi-chamber processing system 500 configured to implement one or more aspects of the present disclosure. The multi-chamber processing system 500 is configured to perform one or more fabrication processes on a separate substrate, such as a silicon wafer, for forming semiconductor devices. The multi-chamber processing system 500 includes some or all of the transfer chamber 506, the buffer chamber 508, the single

wafer load locks

510 and 512, the

processing chambers

514, 516, 518, 520, 522, and 524, the

pre-heat chambers

523 and 525, and the

robots

526 and 528. The single

wafer load locks

510 and 512 may include heating elements 513 and are attached to the buffer chamber 508. Processing

chambers

514, 516, 518, and 520 are attached to transfer chamber 506. The

process chambers

522 and 524 are attached to the buffer chamber 508. The operation of the multi-chamber processing system 500 is controlled by a computer system 530. Computer system 530 may be any device or combination of devices configured to perform the operations of the invention provided herein. Thus, the computer system 530 may be a controller or an array of controllers and/or a general purpose computer configured with software that, when executed, performs the operations of the present invention. One example of a suitable multi-chamber processing system 500 is manufactured by applied materials, Inc., Santa Clara, Calif

RTM CL system.

Each of the

process chambers

514, 516, 518, 520, 522, and 524 may be configured to perform one or more process steps in fabricating conductive structures, such as contact structures for Field Effect Transistors (FETs), in a semiconductor device. More specifically, the

processing chambers

514, 516, 518, 520, 522, and 524 may include one or more metal deposition chambers, surface cleaning and preparation chambers, thermal annealing and/or thermal hydrogenation chambers, and plasma hydrogenation/nitridation chambers.

For example, for contact structures comprising Ti-TiN-Co stacks formed on silicon source or drain structures, in some embodiments, the multi-chamber processing system 500 may be configured to perform several processing steps sequentially in the fabrication process of such conductive structures. In such embodiments, the process chamber 514 may be configured to perform a surface cleaning and preparation process on exposed surfaces of silicon source or drain structures, the process chamber 516 may be configured to sequentially deposit Ti and TiN layers on prepared silicon source or drain structures, the process chambers 522 and/or 524 may be configured to form silicides by performing a Rapid Thermal Processing (RTP) or other thermal annealing process on the Ti/TiN layers and the source/drain structures, the process chamber 518 may be configured to deposit a Co cap layer on the annealed Ti/TiN layers, and the process chamber 520 may be configured to perform a hydrogenation process and a subsequent nitridation process before or after the thermal annealing process. Thus, in such embodiments, a complete contact structure can be formed without voiding and undesirable oxidation of the resulting one or more layer contact structures.

In an alternative embodiment, not all of the processing steps used to form the complete contact structure are performed on a single multi-chamber processing system 500. For example, in some embodiments, the multi-chamber processing system 500 may include a metal deposition processing chamber, while a thermal annealing silicidation process may be performed on a different substrate processing system. In such embodiments, the vacancy occurs prior to the thermal annealing process, and such vacancy is known to increase the presence of O atoms at the interfacial surface of the metal nitride layer and in the bulk material of the metal nitride layer of the contact structure. However, prior to the air break, since the multi-chamber processing system 500 may be configured with both a metal deposition chamber and one or more plasma processing chambers, a sequential plasma (or thermal) hydrogenation/plasma nitridation process or a single-step plasma hydrogenation and nitridation process may be performed. Thus, the multi-chamber processing system 500 may be configured to perform a sequential hydrogenation/nitridation process or a single-step plasma hydrogenation and nitridation process on the substrate after depositing the first metal layer 102 and the metal nitride layer 103 but before removing the substrate from the multi-chamber processing system 500 and exposing the substrate to air. As discussed above, the nitridation of the exposed surface of the metal nitride layer 103 prior to the break may substantially reduce oxidation of the exposed surface during the break and during subsequent thermal annealing processes.

In some embodiments, the multi-chamber processing system 500 may include one or more thermal annealing and plasma processing chambers. In such embodiments, a sequential hydrogenation and nitridation process or a single-step plasma hydrogenation and nitridation process may be performed after the thermal annealing process, thereby removing the O atoms introduced by the pre-anneal breaks and by the thermal annealing process itself. Typically, due to the high temperatures reached by process components (e.g., seals, process kit parts, pumps, etc.) during heat treatment, the thermal annealing process cannot maintain the desired low oxygen levels required by most advanced device nodes.

Alternatively or additionally, a sequential hydrogenation/nitridation process or a single-step plasma hydrogenation and nitridation process may be performed prior to the thermal annealing process. Thus, in such embodiments, even if no air break occurs after the deposition of the metal nitride layer 103 and before the thermal annealing process, interfacial O atoms and O atoms present in the bulk portion of the metal nitride layer may be reduced or eliminated before the thermal annealing process is performed. Thus, in some configurations, a sequential hydrogenation and plasma nitridation process or a single-step plasma hydrogenation and nitridation process may be performed before the thermal annealing process and also after the thermal annealing process but before the air break occurs.

In some embodiments, the multi-chamber processing system 500 may include one or more metal deposition chambers and one or more plasma processing chambers configured to deposit the capping layer 104 and/or the conductive layer 106 to perform a sequential hydrogenation and nitridation process or a single-step plasma hydrogenation and nitridation process. In such an embodiment, a sequential hydrogenation and nitridation process or a single-step plasma hydrogenation and nitridation process may be performed prior to depositing a capping layer in the conductive structure, thereby removing the interface and bulk O atoms introduced by the vacancies and by the thermal annealing process used to form the silicide 105. Note that in such an embodiment, no break occurs between the sequential hydrogenation and nitridation processes and the deposition of capping layer 104 and/or conductive layer 106. Thus, in such embodiments, when a vacancy occurs between the thermal annealing process and the deposition of the capping layer 104, interfacial O atoms and O atoms present in the bulk portion of the metal nitride layer may be reduced or eliminated.

Reduction of bulk and interfacial oxygen in contact structures

Fig. 6 illustrates a flow chart of process steps for reducing bulk and interfacial oxygen in a contact structure, according to some embodiments of the present disclosure. Fig. 7A-7E are schematic cross-sectional views of a semiconductor device corresponding to different stages of the process of fig. 6, in accordance with various embodiments of the present disclosure. Although fig. 7A-7E illustrate the first metal layer 102, the metal nitride layer 103, and the capping layer 104 filling the hole 109 as being selectively deposited (e.g., as shown in fig. 1, the layers are not conformally formed over the hole 109), this is not intended to be limiting to the scope of the disclosure described herein, and thus the first metal layer 102, the metal nitride layer 103, and the capping layer 104 may be selectively formed or non-selectively formed, and include one or more additional layers.

Prior to step 601, a cleaning process or other surface preparation process may be performed on the surface of the semiconductor substrate on which the contacts are to be formed, such as the exposed surface 701 of the source or drain structure 101 in fig. 7A. In some embodiments, a dry etch process may be performed to remove the original oxide on the surface 701. For example, a conventional plasma etch, or a remote plasma assisted dry etch process, such as SiCoNi available from applied materials, Inc. of Santa Clara, USA, may be performed^TMAnd (5) etching process. In SiCoNi^TMIn the etching process, the surface of the semiconductor substrate on which the contact is to be formed is exposed to H₂、NF₃And/or NH₃Plasma species, such as plasma excited hydrogen and fluorine species. For example, in some embodiments, such a surface may undergo simultaneous exposure to H₂、NF₃And NH₃Plasma is generated. SiCoNi^TMThe etching process can be performed on SiCoNi^TMPerformed in a pre-clean chamber that may be integrated into one of a variety of multi-processing platforms, including a Producer available from applied materials, Inc^TM GT、Centura^TMAP and Endura platforms.

As shown in fig. 7B, the method 600 begins at step 601, where a first metal layer 102 and a metal nitride layer 103 are deposited on a semiconductor substrate. For example, in some embodiments, a Ti layer is deposited followed by a TiN barrier layer. Any suitable PVD, CVD, or ALD process may be employed to perform such deposition. Thus, the deposition process may be a selective process or a non-selective deposition process. In a selective deposition process, the first metal layer 102 and the metal nitride layer 103 are deposited on the surface 701, but not on other surfaces of the semiconductor substrate 110, whereas in a non-selective process, the first metal layer 102 and the metal nitride layer 103 may be deposited on all unmasked surfaces of the semiconductor substrate 110. In some embodiments, the deposition of step 601 is performed without an air break after the surface preparation process described above. That is, the semiconductor substrate is not exposed to the atmosphere between the surface preparation process and the deposition of step 601. In such an embodiment, the deposition and surface preparation processes of step 601 may each be performed by different chambers on the same multi-chamber processing system (e.g., multi-chamber processing system 500).

In step 603, a thermal annealing process is performed on the semiconductor substrate 110, which includes the first metal layer 102, the metal nitride layer 103, and the source or drain structure 101. As shown in fig. 7C, a thermal annealing process forms silicide 105. For example, in some embodiments, a spike annealing process to a peak temperature between about 500 ℃ and about 600 ℃ may be performed in step 603. Alternatively, any other suitable annealing process may alternatively be performed to form the silicide 105 between the source or drain structure 101 and the first metal layer 102 deposited in step 601.

In some embodiments, the chamber used to perform step 603 may be configured as the chamber of the same multi-chamber processing system that performs the metal deposition of step 601. Thus, in such an embodiment, after the metal deposition of step 601, the thermal annealing process of step 603 is performed without an interruption, thereby further reducing the presence of interface O on the surface 702 of the metal nitride layer 103. However, for the reasons discussed above, such a configuration of a multi-chamber processing system is uncommon, and a break between

steps

601 and 603 typically occurs.

In step 604, a sequential hydrogenation/plasma nitridation process is performed on the surface 702 of the metal nitride layer 103. That is, as shown in fig. 7D, the surface 702 is exposed to hydrogen atoms and to plasma excited nitrogen species 703. In some embodiments, a plasma hydrogenation process is performed in step 604, followed by a plasma nitridation process. In embodiments where the hydrogenation process is a plasma hydrogenation process, both the plasma hydrogenation process and the plasma nitridation process may be performed in the processing chamber 400 and using the processing parameters described above in connection with fig. 4. Alternatively, the plasma hydrogenation process may be performed in one of the

processing chambers

514, 516, 518, 520, 522, and 524 of the multi-chamber processing system 500, while the plasma nitridation process may be performed in another one of the

processing chambers

514, 516, 518, 520, 522, and 524.

As previously mentioned, in some embodiments, the surface 702 of the metal nitride layer 103 is exposed to hydrogen atoms via a thermal hydrogenation process. In such an embodiment, the thermal hydrogenation process of step 604 is performed in one of the

process chambers

514, 516, 518, 520, 522, and 524 of the multi-chamber processing system 500, e.g., configured using H₂The gas serves as a rapid thermal processing chamber for the process gas. Further, in such embodiments, the plasma nitridation process is performed in another of the

processing chambers

514, 516, 518, 520, 522, and 524, such as a processing chamber similar to the plasma processing chamber 400 of fig. 4. Thus, although the thermal hydrogenation process and the plasma nitridation process are each performed in different processing chambers, no break occurs between the two processes.

In step 605, as shown in fig. 7E, a capping layer 104 is deposited over the annealed first metal layer 102 and metal nitride layer 103. For example, in one embodiment, the metal overlayer is a Co layer or a cobalt-containing alloy layer. Because interfacial O atoms that may be present on the surface 702 of the metal nitride layer 103 are removed in step 604, adhesion between the capping layer 104 and the metal nitride layer 103 is improved over adhesion in contact structures formed via conventional techniques. Further, removing the O atoms within the metal nitride layer 103 reduces the resistivity of the conductive structure 100.

In some embodiments,

steps

604 and 605 are performed on the same multi-chamber processing system such that no air break occurs after the sequential hydrogenation and nitridation processes of step 604. Subsequently, oxidation of the metal nitride layer 103, which may occur during exposure to the atmosphere, is avoided. In other embodiments, the processing chamber used to perform the sequential hydrogenation and nitridation processes of step 604 may be configured on a different multi-chamber processing system than the processing chamber used to perform step 605. Note that in such an embodiment, the nitridation process of step 604 thoroughly nitrifies the surface of metal nitride layer 103, thereby minimizing or otherwise preventing oxidation that may occur during the air break between

steps

604 and 605.

Fig. 8 illustrates a flow chart of process steps for reducing bulk and interfacial oxygen in a contact structure, according to some embodiments of the present disclosure. Prior to step 801, a cleaning process or other surface preparation process may be performed as described above in connection with fig. 7.

The method 800 begins at step 801, where a metal layer 102 and a metal nitride layer 103 are deposited on a source or drain structure 101. Step 801 may be substantially similar to step 601 in method 600.

In step 802, a sequential hydrogenation/plasma nitridation process is performed on the surface 702 of the metal nitride layer 103. That is, the surface 702 is exposed to hydrogen atoms and to plasma excited nitrogen species. Step 802 may be substantially similar to step 604 in method 600. Note, however, that unlike step 604, the sequential hydriding/plasma nitridation process of step 802 is performed prior to the thermal annealing process. Further, in some embodiments, step 802 is performed in a chamber configured as part of a multi-chamber processing system including a thermal annealing chamber (e.g., a rapid thermal processing chamber) for performing step 803. In such an embodiment, the influence of O atoms within the first metal layer 102 and the metal nitride layer 103 deposited in step 801 is further reduced, since such O atoms are removed prior to the annealing process of step 803.

In step 803, a thermal annealing process is performed on the semiconductor substrate 110, which includes the first metal layer 102, the metal nitride layer 103, and the source or drain structure 101. Step 803 may be substantially similar to step 603 in method 600. Alternatively, in embodiments where the thermal hydrogenation process occurs in step 802, a thermal annealing process is performed in step 802, and step 803 may be skipped. For example, in some embodiments, the thermal annealing process by which the silicide 105 is formed is performed in the same processing chamber as the thermal hydrogenation process of step 802. In such embodiments, the thermal annealing process may be performed simultaneously with the thermal hydrogenation process, immediately prior to the thermal hydrogenation process, or immediately after the thermal hydrogenation process.

In optional step 804, a plasma treatment process is performed on the surface 702 of the metal nitride layer 103. Step 804 may be substantially similar to step 604 in method 600. Thus, in an embodiment of the method 800 in which step 804 is performed, a sequential hydrogenation/nitridation process is performed before and after the thermal annealing process of step 803. In some embodiments, the sequential hydrogenation/nitridation process performed in step 804 is substantially the same as the plasma treatment process performed in step 802. In other embodiments, the sequential hydrogenation/nitridation process of step 804 may be different from the sequential hydrogenation/nitridation process of step 802. For example, the processing parameters of the sequential hydrogenation/nitridation process employed in step 802 may be different from the processing parameters of the sequential hydrogenation/nitridation employed in step 804.

In step 805, a capping layer 104 and/or a conductive layer 106 is deposited over the annealed first metal layer 102 and metal nitride layer 103. Step 805 may be substantially similar to step 605 in method 600. Similarly, in some embodiments,

steps

804 and 805 may be performed on the same multi-chamber processing system such that no air break occurs after the plasma processing process of step 804. Subsequently, oxidation of the metal nitride layer 103, which may occur during exposure to air, is avoided and the adhesion between the capping layer 104 and the metal nitride layer 103 is improved, which is superior to the adhesion in contact structures formed via conventional techniques.

Fig. 9 illustrates a flow chart of process steps for reducing bulk and interfacial oxygen in a contact structure, according to some embodiments of the present disclosure. Prior to step 901, a cleaning process or other surface preparation process may be performed as described above in connection with method 600. As shown, the method 900 begins at step 901, where a first metal layer 102 and a metal nitride layer 103 are deposited on a source or drain structure 101. Step 901 may be substantially similar to step 601 in method 600. In step 902, a sequential hydrogenation/nitridation process is performed on the surface 702 of the metal nitride layer 103. Step 902 may be substantially similar to step 802 in method 800. In step 903, a thermal annealing process is performed on the semiconductor substrate 110, which includes the first metal layer 102, the metal nitride layer 103, and the source or drain structure 101. Step 903 may be substantially similar to step 603 in method 600. In step 905, a capping layer 104 is deposited over the annealed first metal layer 102 and metal nitride layer 103. Step 905 may be substantially similar to step 605 in method 600. Thus, in the method 900, a sequential hydrogenation/nitridation process is performed before the thermal annealing process of step 903 and not after the thermal annealing process of step 903. The sequential hydrogenation/nitridation process typically includes a plasma or thermal hydrogenation process and a plasma nitridation process.

Although

methods

600 and 800 are described for forming contact structures on a substrate,

methods

600 and 800 may also be used to form other conductive structures on a substrate. Thus, any conductive structure including a metal nitride layer may benefit from being formed by the

method

600 or 800.

Metal gate structure with reduced EOT

In accordance with various embodiments of the present disclosure, sequential hydrogenation and nitridation processes are employed in the fabrication of high-k dielectric/metal gate stacks to reduce the Effective Oxide Thickness (EOT) of the stack. In such an implementation, the EOT of the stack is reduced without loss in terms of leakage increase and flatband (flatband) voltage shift, which are known to occur when the thickness of the high-k dielectric layers in the stack are only reduced or otherwise scaled down via conventional techniques. One such stack is shown in fig. 10.

Figure 10 illustrates a cross-sectional view of a metal gate structure 1000 formed in accordance with an embodiment of the present disclosure. The metal gate structure 1000 is formed on a semiconductor substrate 1001 as part of a semiconductor device (e.g., a MOSFET or other FET). The metal gate structure 1000 is a stack of a plurality of material layers formed on a semiconductor substrate 1001, and includes, for example, an interface layer 1002 provided on the semiconductor substrate 1001, a high-dielectric-constant dielectric layer 1003 provided on the interface layer 1002, a metal nitride cap layer 1004 provided on the high-dielectric-constant dielectric layer 1003, and a metal gate electrode layer 1005 provided on the metal nitride cap layer 1004. In the embodiment shown in fig. 10, the various layers of the metal gate structure 1000 are illustrated as a simple film stack formed on a semiconductor substrate 1001. In practice, the metal gate structure 1000 may be formed in a contact well or other cavity formed in an insulating or dielectric material similar to the insulating material 120 in fig. 1. Thus, one or more of the interface layer 1002, the high-k dielectric layer 1003, the metal nitride cap layer 1004, and the metal gate electrode layer 1005 may be a layer of material conformally deposited within this cavity.

Semiconductor substrate 1001 may be any suitable semiconductor substrate on which metal gate structure 1000 may be formed. Accordingly, the semiconductor substrate 1001 may be formed of any suitable semiconductor material, including but not limited to Si (Si), Ge (germanium), silicon germanium (Si-Ge), silicon germanium carbon (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), and all other group III/V or group II/VI compound semiconductors. Alternatively or additionally, the semiconductor substrate 1001 may be a layered semiconductor, such as Si/Si-Ge, semiconductor-on-insulator (SOI), or Si-Ge-on-insulator (sigoi). Furthermore, in some embodiments, the semiconductor substrate 1001 includes doped and/or undoped regions, such as n-doped or p-doped regions adjacent to the interfacial oxide layer 1002.

An interfacial oxide layer 1002 is disposed on the semiconductor substrate 1001 between the semiconductor substrate 1001 and the high-k dielectric layer 1003, and is configured as an interfacial oxide layer suitable for application in the metal gate structure 1000. In embodiments where the semiconductor substrate 1001 includes a Si-containing material, the interfacial oxide 1002 layer may include silicon oxide (SiO)_x) Silicon oxynitride (SiNO, Si)₂NO、Si₂N₂O), and/or nitrided silicon oxide. In embodiments where the semiconductor substrate 1001 is not a Si-containing semiconductor material, the interfacial oxide layer 1002 can include a semiconductor oxide, a semiconductor oxynitride, and/or a nitrided semiconductor oxide.

The interfacial oxide layer 1002 may be formed via any suitable thermal or wet growth technique (e.g., oxidation or oxynitridation). For example, and without limitation, interfacial oxide layer 1002 may be formed by a wet chemical oxidation process that includes treating a cleaned surface of semiconductor substrate 1001 with a mixture of ammonium hydroxide, hydrogen peroxide, and water, such as a semiconductor surface that was last treated with HF. Alternatively, the interfacial oxide layer 1002 can be formed by treating a previously HF treated semiconductor surface in an ozonated aqueous solution. Alternatively, interfacial oxide layer 1002 may be formed by any suitable thermal oxidation technique.

The thickness of interfacial oxide layer 1002 varies with the semiconductor device of which metal gate structure 1000 is a part. In addition, the interfacial oxide layer 1002 is significantly thinner than the high-k dielectric layer 1003, the metal nitride cap layer 1004, and the metal gate electrode layer 1005. Typically, the interfacial oxide layer 1002 has a thickness from about 0.5 to 2.0nm, although the interfacial oxide layer 1002 may be thicker in some embodiments. In some embodiments, the thermal process for device fabrication that occurs after the formation of the metal gate structure 1000 may further increase the thickness of the interfacial oxide layer 1002.

The high-k dielectric layer 1003 may be a gate dielectricA dielectric layer or other dielectric layer in the metal gate structure 1000, and includes a so-called "high-k dielectric" material. More specifically, the high-k dielectric layer 1003 includes one or more materials having a dielectric constant greater than SiO₂Such as a material having a dielectric constant of at least about 4.0, or desirably at least about 10.0. In addition, the high-k dielectric material included in the high-k dielectric layer 1003 is suitable for use in an integrated circuit. Thus, in addition to high dielectric constant, the one or more high dielectric constant dielectric materials included in the high dielectric constant dielectric layer 1003 also desirably have the ability to prevent dopant diffusion, fewer electrical defects that can compromise breakdown performance, good thermal stability, and a high recrystallization temperature. Examples of such high-k dielectric materials suitable for use in the high-k dielectric layer 1003 include, but are not limited to, silicon nitride, silicon oxynitride, metal oxide, metal nitride, metal oxynitride, and/or metal silicate. In some embodiments, the high-k dielectric layer 1003 includes one or more of the following: hafnium oxide (Hf)_xO_y) Zirconium oxide (ZrO)₂) Hafnium oxide silicate (Hf)_xSi_1-xO_y) Or other hafnium-based dielectrics, lanthanum oxide (La)₂O₃) Alumina (Al)₂O₃) Titanium oxide (TiO)₂) Strontium titanate (SrTiO)₃) Lanthanum aluminate (LaAlO)₃) Yttrium oxide (Y)₂O₃) Hafnium oxide silicate (Hf)_xSi_1-xO_y) Lanthanum oxide (La)₂O₃) And/or a plurality of layer stacks of the above.

The high-k dielectric layer 1003 may be formed via any suitable deposition method, including a thermal growth process, such as an oxidation, nitridation or oxynitridation process. Alternatively, the high-k dielectric layer 1003 may be formed by one or more deposition processes, including but not limited to Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), evaporation, reactive sputtering, chemical solution deposition, and/or any combination thereof.

The thickness 1003A of the high-k dielectric layer 1003 may vary depending on the dielectric material included therein, the process used to form the high-k dielectric layer 1003, and the geometry and operation of the semiconductor device in which the metal gate structure 1000 is included. In some embodiments, the high-k dielectric layer 1003 has a thickness 1003A from about 1.0nm to about 20 nm.

The metal nitride cap layer 1004 is a metal layer disposed on the high-k dielectric layer 1003, which is typically configured as a conductive protective layer on the high-k dielectric layer 1003. Thus, in some embodiments, the metal nitride cap layer 1004 is configured to prevent undesired oxidation of the semiconductor substrate 1001 and/or the high-k dielectric layer 1003. Furthermore, in such embodiments, the metal nitride cap layer 1004 may also be configured to allow oxygen to diffuse out of the high-k dielectric layer 1003 during a thermal annealing process that occurs after the metal nitride cap layer 1004 is deposited. In such embodiments, the metal nitride cap 1004 may also be configured to allow oxygen to diffuse out of the interface layer 1009 formed between the high-k dielectric layer 1003 and the metal nitride cap 1004 during the thermal annealing process.

In some embodiments, the metal nitride cap layer 1004 includes a metal nitride, such as silicon nitride (TiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), and the like. Note that in some embodiments, depositing the nitride cap layer 1004 on the high-k dielectric layer 1003 may result in the formation of an interface layer 1009, which is disposed at the interface between the high-k dielectric layer 1003 and the metal nitride cap layer 1004. According to some embodiments, the interface layer 1009 is subsequently eliminated or reduced in thickness when a sequential plasma hydrogenation and nitridation process as described herein is applied to the exposed surface of the metal nitride cap layer 1004.

The metal nitride cap layer 1004 may be formed via any suitable deposition method, including but not limited to a PVD process, a CVD process, a PECVD process, a MOCVD process, an ALD evaporation process, reactive sputtering, chemical solution deposition, and/or any combination thereof.

In some embodiments, the metal nitride cap layer 1004 is significantly thinner than the high-k dielectric layer 1003 and the metal gate electrode layer 1005. For example, in an embodiment of the metal gate structure 1000, wherein the high-k dielectric layer 1003 layer is HfO having a thickness 1003A of about 20nm to about 40nm₂The layer and the metal gate electrode layer 1005 is a TiN layer having a thickness of about 20nm to about 40nm, and the metal nitride cap layer 1004 may have a thickness 1004A of about 5nm to about 15 nm.

In some embodiments, the thickness 1004A of the metal nitride cap layer 1004 is selected to promote diffusion of oxygen atoms from the high-k dielectric layer 1003 and/or the interface layer 1009. Specifically, in such an embodiment, the thickness 1004A is selected such that O atoms diffuse from the high-k dielectric layer 1003 and/or the interface layer 1009 during a thermal annealing process that occurs after the metal nitride cap layer 1004 is deposited. In such an embodiment, the thickness 1004A is selected to be less than the diffusion length of O atoms through the metal nitride cap layer 1004 during the thermal annealing process. In one example, one such thermal annealing process is a spike annealing process performed on the metal gate structure 1000 for a duration of 1-2 seconds and a peak temperature of about 700 to about 900 ℃.

The metal gate electrode layer 1005 is a metal layer formed on the metal nitride cap layer 1004 and includes one or more deposited metal layers. In some embodiments, metal gate electrode layer 1005 is configured as a gate electrode and/or a work function metal of metal gate structure 1000. In such an embodiment, one or more metal layers included in metal gate electrode layer 1005 are selected to have a common gate electrode work function value that facilitates operation of metal gate structure 1000 and the semiconductor device in which metal gate structure 1000 is included. The metal gate electrode 1005 may be formed via any suitable deposition method including, but not limited to, CVD, PECVD, MOCVD, ALD, evaporation, reactive sputtering, chemical solution deposition, and/or any combination thereof.

In some embodiments, the metal gate electrode layer 1005 is a p-metal gatePole material such as TiN. Alternatively, in some embodiments, metal gate electrode layer 1005 is an n-metal gate. N-metal suitable for use in metal gate electrode layer 1005 includes titanium aluminum carbide (Ti)_xAlC)。

Forming metal gate structures with reduced EOT

According to various embodiments, during the fabrication of metal gate structure 1000, a sequential plasma hydrogenation and nitridation process is performed on metal nitride cap layer 1004 prior to depositing metal gate electrode layer 1005. In such an embodiment, the EOT of the metal gate structure 1000 is reduced, while the leakage current of the metal gate structure 1000 increases at a lower than expected magnitude. Furthermore, in such an implementation, the metal gate structure 1000 exhibits little or no flat band voltage shift typically associated with reduced EOT.

For example, in one embodiment of the metal gate structure 1000, the interfacial oxide layer 1002 has a thickness of about 1-2nm, the high-k dielectric layer 1003 has a thickness 1003A of about 2-3nm, and the metal nitride cap layer 1004 has a thickness 1004A of about 3-4 nm. In such an embodiment, one measurable effect of treating the metal nitride cap layer 1004 with the sequential plasma hydrogenation and nitridation processes described herein is a reduction in the measurable EOT of the metal gate structure 1000 by about

(i.e., from about

Down to about

). Another effect of this treatment of the metal nitride cap 1004 is an increase in leakage current (at a flat charge voltage of-1V) of about 2.4 times (i.e., from about 0.268A/cm)²To about.658A/cm²). In contrast, according to the established scaling trend known in the art,when the EOT of the metal gate structure 1000 is instead reduced by conventional techniques (e.g., by scaling down the thickness 1003A by about

) The leakage current is expected to increase by a factor of about 10. Thus, it has been found that treating the metal nitride cap layer 1004 with the sequential plasma hydrogenation and nitridation processes described herein has the effect of reducing the EOT of the metal gate structure 1000 with about one-fourth of the increased leakage current as associated with merely scaling down the thickness 1004A of the metal nitride cap layer 1004.

Furthermore, despite the reduction in EOT described above, it has been illustrated that the flat band voltage offset measured in the metal gate structure 1000 remains substantially stable when the metal gate structure 1000 is formed using a sequential plasma hydrogenation and nitridation process. Thus, applying sequential plasma hydrogenation and nitridation processes to the metal nitride cap layer 1004 enables the fabrication of a metal gate structure 1000 with reduced EOT without flat band voltage shifts and without impacting device design.

Fig. 11 illustrates a flow chart of process steps for reducing EOT in a metal gate structure according to various embodiments of the present disclosure. Fig. 12A-12J are schematic cross-sectional views of a semiconductor device corresponding to different stages of the process of fig. 11, in accordance with various embodiments of the present disclosure.

The method 1100 begins at step 1101 as shown in fig. 12A, where a high-k dielectric layer 1003 is deposited over the interfacial oxide layer 1002. The high-k dielectric layer 1003 may be formed via any suitable deposition method described above in connection with fig. 10.

In step 1102, a metal nitride cap layer 1004 is deposited over the high-k dielectric layer 1003, as shown in fig. 12B. The metal nitride cap layer 1004 may be formed via any suitable deposition method described above in connection with fig. 10. In some embodiments, depositing the metal nitride cap layer 1004 results in the formation of an interface layer 1009, which is disposed at the interface between the high-k dielectric layer 1003 and the metal nitride cap layer 1004. In such an embodiment, the interfacial layer 1009 typically includes vacancies (which may be similar to the vacancies 213 in fig. 2A) and/or O atoms introduced by contamination present in the processing environment during the deposition process of step 1102.

In optional step 1103, exposed surface 1201 shown in fig. 12B is exposed to air. For example, in some embodiments, the metal nitride cap layer 1004 is deposited in one processing system, such as the multi-chamber processing system 500 of fig. 5, while the next processing step to be performed on the semiconductor substrate 1001 is performed in a different processing system. Thus, in this embodiment, after the metal nitride layer 1004 is deposited, the semiconductor substrate 1001 is exposed to air. In an embodiment in which the metal nitride cap layer 1004 is deposited in one chamber of a multi-chamber processing system, and step 1104 is performed in one or two other processing chambers of the same multi-chamber processing system, optional step 1103 is not performed.

In embodiments in which the metal nitride cap layer 1004 deposited in step 1102 is a sacrificial metal nitride layer that is subsequently removed, the method 1100 proceeds to step 1131. In embodiments where the metal nitride cap layer 1004 deposited in step 1102 remains in the metal gate structure 1000, the method 1100 proceeds to step 1104. In some embodiments, the sacrificial metal nitride layer may be removed by using a subsequent wet or dry etch process that is selective to the removal of the metal nitride cap layer 1004.

In step 1104, a sequential plasma hydrogenation and nitridation process is performed on surface 1201 of metal nitride cap layer 1004, as shown in fig. 12C. The plasma hydrogenation and nitridation process may be substantially similar to the plasma hydrogenation and nitridation process described above in connection with fig. 4. In addition, the plasma hydrogenation process includes non-oxidizing plasma excited hydrogen species and does not include any oxidizing plasma excited hydrogen species.

In some embodiments, the chamber pressure is between about 20mTorr and about 100mTorr, the process temperature is between about 400 ℃ and about 500 ℃ (e.g., substrate pedestal temperature), and the RF power is atBetween about 500W and about 1500W, H₂At a flow rate of between about 20sccm and about 100sccm and Ar at a flow rate of between about 900sccm and about 980sccm, the plasma hydrogenation process of step 1104 is performed for a duration of between about 30 seconds and about 150 seconds. In some embodiments, H₂Is between about 1% and about 15% of the total process gas introduced into the chamber. In some embodiments, the process temperature is between about 425 ℃ and about 475 ℃ at a chamber pressure of between about 45mTorr and about 55mTorr, with an RF power of between about 700W and about 800W, H₂At a flow rate of between about 45sccm and about 55sccm and Ar at a flow rate of between about 965sccm and about 955sccm, the plasma hydrogenation process of step 1104 is performed for a duration of between about 85 seconds and about 95 seconds.

In some embodiments, the process temperature is between about 400 ℃ and about 500 ℃ at a chamber pressure of between about 10mTorr and about 50mTorr, with RF power between about 500W and about 1500W, NH₃Is between about 1% and about 10% of the total process gas flow, N₂Is between about 45% and about 55% of the total process gas flow, and the flow of Ar is selected to be equal to the remainder of the process gas flow, the plasma nitridation process of step 1104 is performed for a duration of between about 30 seconds and about 150 seconds. In some embodiments, the NH is performed at a chamber pressure of between about 15mTorr and about 25mTorr, at a process temperature of between about 425 ℃ and about 475 ℃, with an RF power of between about 700W and about 800W₃Is between about 2% and about 3% of the total process gas flow, N₂Is between about 45% and about 55% of the total process gas flow, and the flow of Ar is selected to be equal to the remainder of the process gas flow, the plasma nitridation process of step 1104 is performed for a duration of between about 85 seconds and about 95 seconds.

In summary, in step 1104, substrate 1201 is exposed to plasma excited hydrogen species generated in a plasma hydrogenation process and some or all of the oxides present on surface 1201 are reduced. In addition, in some embodiments, such plasma-excited hydrogen species may also reduce some or all of the oxygen (O) atoms present in the bulk material of the metal nitride cap layer 1004. Further, in step 1104, substrate 1201 is exposed to plasma-excited nitrogen species generated in a plasma nitridation process, thereby bringing surface 1201 to N-atom saturation and, in some embodiments, filling vacancies present in the host material of metal nitride cap layer 1004 with N atoms. Thus, in some embodiments, as shown in fig. 12D, the interface layer 1009 is eliminated or significantly reduced.

In some embodiments, the plasma hydrogenation process of step 1104 is performed in the same processing chamber as the plasma nitridation process of step 1104, e.g., in processing chamber 400 of fig. 4. Alternatively, the plasma hydrogenation process of step 1104 is performed in a first processing chamber of a multi-chamber processing system, while the plasma nitridation process of step 1104 is performed in a second processing chamber of the same multi-chamber processing system. In either case, it is noted that the surface 1201 is not exposed to air between the plasma hydrogenation process and the plasma nitridation process of step 1104. Thus, in either embodiment, surface 1201 is not exposed to air after exposure to the plasma excited hydrogen species and before exposure to the plasma excited nitrogen species.

In some embodiments, an oxygen-free conditioning process is performed in the processing chamber prior to performing the plasma hydrogenation process in the processing chamber, for example, to reduce trace oxygen contamination in the processing chamber. In such embodiments, the processing chamber is treated with an oxygen-free plasma without a substrate disposed therein and prior to treating the substrate via the plasma hydrogenation process described above. Such plasma processing of a processing chamber prior to introduction of a substrate into the chamber is sometimes referred to as a Plasma Every Wafer (PEW) process or PEW processing.

In some embodiments, such a PEW process includes the addition of one or more non-oxygen-containing gases (e.g., N)₂、NH₃、Ar、H₂Or any suitable combination thereof) is introduced into the processing chamber and one or more gases are energized to form an oxygen-free plasma. Alternatively, PEWThe process may include adding plasma-containing radicals and/or N, H, or NH₃Or any suitable combination thereof, into a processing chamber, wherein a plasma is formed in a remote plasma source external to the processing chamber. In one embodiment, NH is reacted with₃Gas or NH₃And Ar gas are introduced into the process chamber. In another embodiment, H is₂Gas or H₂And Ar gas are introduced into the process chamber. In yet another embodiment, N is₂Gas or N₂And Ar gas are introduced into the process chamber.

Typically, plasma processing of a process chamber prior to introduction of a substrate involves introducing or forming a hydrogen and/or nitrogen containing plasma in the process chamber. In some embodiments, radicals (e.g., N, NH, and/or H) generated by a plasma inside the processing chamber during the PEW process react with trace O atoms within the processing chamber.

In some embodiments, one or more gases introduced into the processing chamber are energized by an RF power source, such as RF power source 414 of fig. 4, during the PEW process. The RF power may be pulsed at a duty cycle of 2% to 70%, and may range from about 100W to about 2500W. The RF power may be a continuous wave ranging from about 100W to about 2500W. In such embodiments, the process temperature is between about 400 ℃ and about 500 ℃ at a chamber pressure of about 10mTorr to about 200mTorr, with an RF power of between about 250W and about 750W, H₂Is between about 50sccm and about 200sccm, and O₂Between about 450sccm and about 550sccm, the PEW process of step 1104 is performed for a duration of between about 20 seconds and about 100 seconds.

In optional step 1105, exposed surface 1201 is exposed to air. For example, in some embodiments, the sequential hydrogenation and nitridation processes described above are performed in one processing system, while the next processing step to be performed on the semiconductor substrate 1001 is performed in a different processing system. Thus, in this embodiment, after the metal nitride layer 1004 is deposited, the semiconductor substrate 1001 is exposed to air. In embodiments where the sequential hydrogenation and nitridation processes are performed in one chamber of a multi-chamber processing system and step 1106 is performed in another processing chamber of the same multi-chamber processing system, optional step 1105 is not performed.

In embodiments where a sacrificial silicon-containing layer is subsequently deposited and removed as part of forming the metal gate structure 1000, the method 1100 proceeds from step 1105 to step 1121. In embodiments in which a sacrificial silicon layer is not deposited when forming the metal gate structure 1000, the method 1100 continues to step 1106. The sacrificial silicon-containing layer may be formed by using a CVD or ALD process that uses one or more silicon-containing precursor gases to form the deposited layer.

In step 1106, a thermal annealing process (e.g., post-capping anneal) is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, and the metal nitride cap layer 1004. For example, in some embodiments, a spike annealing process is performed in step 1106, wherein a peak temperature of about 600 to 900 ℃ is reached. A post-capping anneal is performed on the partially formed metal gate structure 1000 to smooth the interface, repair dangling bonds, and inject thermal energy into the metal nitride capping layer.

In step 1107, as shown in fig. 12E, a metal gate electrode layer 1005 is deposited over the treated metal nitride cap layer 1004, thereby completing the formation of the metal gate structure 1000. Metal gate electrode 1005 may be formed via any suitable deposition method described above in connection with fig. 10.

In step 1121, a sacrificial silicon layer 1202 is deposited over the metal nitride cap layer 1004, as shown in FIG. 12F. Step 1121 is performed after the surface 1201 of the metal nitride cap layer 1004 is treated by the sequential plasma hydrogenation and nitridation processes of step 1104 and the optional air exposure of step 1105.

The sacrificial silicon layer 1202 may comprise any suitable silicon-containing material, such as amorphous silicon, and may be deposited using any suitable deposition process known in the art, such as a CVD process. A sacrificial silicon layer 1202 is deposited over the metal nitride cap layer 1004 to reduce the formation of oxide in the metal nitride cap layer 1004, the interface layer 1009 (if still present), and the high-k dielectric layer 1003 during a subsequent thermal annealing process, such as a so-called post-cap annealing process. In some embodiments, the post-capping annealing process comprises an atmospheric thermal annealing process. Subsequently, further oxidation of very thin layers of the metal gate structure 1000, including the interfacial layer 1002, the high-k dielectric layer 1003, and the metal nitride cap layer 1004, may occur, thereby increasing the EOT of the metal gate structure 1000. However, the presence of the sacrificial silicon layer 1202 may shield the layers of the metal gate structure 1000 from atmospheric O atoms during the pre-capping anneal process. In addition, the sacrificial silicon layer 1202 may react with and thereby retain the O atoms that diffuse out of the high-k dielectric layer 1003, the interface layer 1009 (if still present), and the metal nitride cap layer 1004 during the thermal annealing process. Accordingly, the sacrificial silicon layer 1202 minimizes or eliminates the potential for undesirably oxidizing portions of the metal gate structure 1000 during a subsequent thermal anneal process.

In step 1122, a thermal annealing process (e.g., post-capping anneal) is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, the metal nitride cap layer 1004, and the sacrificial silicon layer 1202. The thermal annealing process of step 1122 may be substantially similar to the thermal annealing process of step 1106 described above.

In step 1123, the sacrificial silicon layer 1202 is removed from the metal gate structure 1000. Any technically feasible removal process may be employed in step 1123, including a selective wet etch process, a plasma-based dry etch process, a chemical mechanical polishing process, or any combination thereof. The method 1100 then continues to step 1107, where the final layers of the metal gate structure 1000 are deposited.

In step 1131, as shown in fig. 12G, a sacrificial silicon layer 1203 is deposited on the metal nitride cap layer 1004. Sacrificial silicon layer 1203 may be substantially similar to sacrificial silicon layer 1202 deposited in step 1131. Note, however, that in step 1131, the metal nitride cap layer 1004 has not been treated with a sequential plasma hydrogenation and nitridation process. Thus, the metal nitride cap layer 1004 may still include the interface layer 1009 as shown.

In step 1132, a thermal annealing process (e.g., post-cap anneal) is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, the metal nitride cap layer 1004, the interface layer 1009, and the sacrificial silicon layer 1203. The thermal annealing process of step 1132 may be substantially similar to the thermal annealing process of step 1106 described above.

In step 1133, as shown in fig. 12H, sacrificial silicon layer 1203, metal nitride cap layer 1004, and interface layer 1009 are removed from metal gate structure 1000. Any technically feasible removal process or combination of processes may be employed in step 1123, including a selective wet etch process, a plasma-based dry etch process, a chemical mechanical polishing process, or any combination thereof. The method 1100 then proceeds to step 1134.

In step 1134, a final metal nitride cap layer 1204 is deposited over the high-k dielectric layer 1003, as shown in fig. 12I. The final metal nitride cap layer 1204 may be substantially similar to the metal nitride cap layer 1004 and may include an interface layer 1009.

In optional step 1135, the exposed surface 1205 shown in FIG. 12I is exposed to air. For example, in some embodiments, the final metal nitride cap layer 1204 is deposited in one processing system, while the next processing step to be performed on the semiconductor substrate 1001 (i.e., step 1136) is performed in a different processing system. Thus, in such an embodiment, the semiconductor substrate 1001 is exposed to air after the deposition of the final metal nitride layer 1204. In embodiments where the final metal nitride capping layer 1204 is performed in one chamber of a multi-chamber processing system, and step 1136 is performed in one or two other processing chambers of the same multi-chamber processing system, optional step 1135 is not performed.

In step 1136, a sequential plasma hydrogenation and nitridation process is performed on the surface 1205 of the final metal nitride cap layer 1204, as shown in fig. 12J. The sequential plasma hydrogenation and nitridation processes performed in step 1136 may be substantially similar to the processes employed in step 1104. Subsequently, the interfacial layer 1009 may be eliminated or reduced during step 1136, thereby removing O atoms present in the final metal nitride capping layer 1204, the interfacial layer 1009, and in some embodiments the high-k dielectric layer 1003. Accordingly, the EOT of the metal gate structure 1000 is reduced without scaling down the thickness 1003A of the high-k dielectric layer 1003.

After performing the sequential plasma hydrogenation and nitridation processes in step 1136, method 1100 continues to step 1107, where the final layers of metal gate structure 1000 are deposited. In an embodiment where

steps

1136 and 1107 are performed in different processing systems, the semiconductor substrate 1001 must be exposed to air. However, because the plasma nitridation process of step 1136 may completely or nearly completely nitridize the exposed surface 1205 of the final metal nitride cap layer 1204, little or no oxidation thereof typically occurs during such air exposure.

Single step nitridation-hydrogenation process

The method 1300 begins at step 1301, as shown in FIG. 14A, wherein a high dielectric constant dielectric layer 1003 is deposited over the interfacial oxide layer 1002. The interfacial oxide layer 1002 may be deposited by any suitable method, such as chemically oxidizing the underlying semiconductor substrate 1001, thermally oxidizing the underlying substrate, Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or the like. The high-k dielectric layer 1003 may be formed via any suitable deposition method described above in connection with fig. 10. The high dielectric constant dielectric layer 1003 may include any high dielectric constant material that is oxidizable. According to one embodiment, the high-k dielectric layer 1003 includes silicon dioxide (SiO)₂) Or hafnium oxide (HfO)₂)。

In step 1302, a capping layer 1404 is deposited over the high-k dielectric layer 1003, as shown in fig. 14B. The capping layer 1404 may be formed via any suitable deposition method described above in connection with fig. 10. The capping layer 1404 may comprise a metal nitride. According to one embodiment, the capping layer may include a metal nitride, such as titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TAN), or titanium silicon nitride (TiSiN). In some embodiments, depositing the capping layer 1404 results in the formation of an interface layer 1409 disposed at the interface between the high-k dielectric layer 1003 and the capping layer 1404. In such an embodiment, the interfacial layer 1409 typically includes defects such as vacancies (which may be similar to the vacancies 213 in fig. 2A) and/or O atoms introduced by contamination present in the processing environment during the deposition process of step 1302. Defects may allow for undesired charge transfer due to electron hopping between defects. The charge transfer may result in current leakage or dielectric breakdown, thereby reducing the electrical reliability of the metal gate structure 1000.

In optional step 1303, exposed surface 1401 shown in FIG. 14B is exposed to air. For example, in some embodiments, the cap layer 1404 is deposited in one processing system, such as the multi-chamber processing system 500 of fig. 5, while the next processing step to be performed on the semiconductor substrate 1001 is performed in a different processing system. Thus, in such an embodiment, the semiconductor substrate 1001 is exposed to air after the capping layer 1404 is deposited. In embodiments where the cap layer 1404 is deposited in one chamber of a multi-chamber processing system and step 1304 is performed in one or two other processing chambers of the same multi-chamber processing system, optional step 1303 is not performed.

In embodiments where the capping layer 1404 deposited in step 1302 is a sacrificial layer that is subsequently removed, the method 1400 continues to step 1331. In embodiments where the capping layer 1404 deposited in step 1302 remains in the metal gate structure 1000, the method 1300 proceeds to step 1304. In some implementations, the sacrificial layer can be removed by using a subsequent wet or dry etch process that is selective to the removal of the capping layer 1404.

In step 1304, a single-step plasma hydrogenation and nitridation process is performed on surface 1401 of cap layer 1404, as shown in fig. 14C. The single-step plasma hydrogenation and nitridation process includes exposing a workpiece (e.g., metal gate structure 1000) to a processing plasma, wherein the processing plasma includes a nitrogen-containing gas and a hydrogen-containing gas. In some embodiments, the hydrogen-containing gas substantially includes both nitrogen-containing and hydrogen-containing gases, such as ammonia (NH)₃) Hydrazine (N)₂H₄) Or hydrogen azide (HN)₃). In one example, the hydrogen-containing gas comprises ammonia (NH)₃) And the nitrogen-containing gas comprises (N)₂). According to one embodiment, the processing plasma may include a single gas containing hydrogen and nitrogen, such as hydrazine (N)₂H₄) Or ammonia (NH)₃). According to one embodiment, the processing plasma may include an additional neutral carrier gas, such as argon (Ar), or helium (He). In one example, the process gas contained in the processing plasma substantially comprises ammonia (NH)₃) Nitrogen (N)₂) And a neutral carrier gas such as argon (Ar) or helium (He). In addition, a bias voltage may be applied to the substrate by the bias power supply 426 during the single-step plasma hydrogenation and nitridation process of step 1304. Similar to the RF power supply 414, the bias power supply 426 is generally capable of generating an RF signal having a tunable frequency ranging from about 2MHz to about 160MHz and a power between about 0kW and about 10 kW. The bias power improves conformality of the growing film by rearranging the deposited atoms.

In some embodiments, the chamber pressure is between about 10mTorr and about 100mTorr, the process temperature (e.g., substrate pedestal temperature) is between about 350 ℃ and about 500 ℃, the RF power is between about 300W and about 2000W, NH₃At a flow rate of between about 5sccm and about 100sccm, N₂Between about 50sccm and about 1000sccm, and a helium (He) flow between about 1 to about 1000sccm, performing the single-step plasma hydrogenation and nitridation process of step 1304 for a duration between about 30 seconds and about 150 seconds, and applying a substrate bias having a frequency from about 2MHz to about 160MHz and a bias power between about 0kW and about 10 kW.

In some embodiments, the process temperature is between about 425 ℃ and about 475 ℃ at a chamber pressure of between about 15mTorr and about 25mTorr, with an RF power of between about 900W and about 1100W, NH₃At a flow rate of between about 15sccm to about 35sccm, N₂At a flow rate of between about 450sccm to about 550sccm, at a flow rate of Ar of from about 450sccm to about 500sccm, the single-step plasma hydrogenation and nitridation process of step 1304 is performed for a duration of between about 85 seconds and about 95 seconds, and no substrate bias power is applied.

In summary, in step 1304, surface 1401 is exposed to plasma excited hydrogen and nitrogen species generated in a plasma process and some or all of the oxide present on surface 1401 is converted to a nitride. Thus, as shown in fig. 14D, in some embodiments, the thickening of the interface layer 1409 is eliminated or substantially reduced. The interfacial layer 1409 remains but no layer thickening occurs. The reduction or nitridation of the interfacial layer 1409 reduces EOT and changes the work function of the metal gate structure 1000.

In some embodiments, an oxygen-free conditioning process is performed in the processing chamber prior to performing the single-step plasma hydrogenation and nitridation process of step 1304, for example, to reduce trace oxygen contamination in the processing chamber. In such embodiments, the processing chamber is treated with an oxygen-free plasma without a substrate disposed therein and prior to treating the substrate via the single-step plasma hydrogenation and nitridation processes described above.

In optional step 1305, exposed surface 1401 is exposed to air. For example, in some embodiments, the single-step plasma hydrogenation and nitridation process of step 1304 above is performed in one processing system, while the next processing step to be performed on the semiconductor substrate 1001 is performed in a different processing system. Thus, in such an embodiment, after depositing layer 1404, semiconductor substrate 1001 is exposed to air. In embodiments where the single-step plasma hydrogenation and nitridation process of step 1304 is performed in one chamber of a multi-chamber processing system and step 1306 is performed in another processing chamber of the same multi-chamber processing system, optional step 1305 is not performed.

In embodiments where a sacrificial silicon-containing layer is subsequently deposited and removed as part of forming the metal gate structure 1000, the method 1300 proceeds from step 1305 to step 1321. In embodiments in which a sacrificial silicon layer is not deposited when forming the metal gate structure 1000, the method 1300 proceeds to step 1306. The sacrificial silicon-containing layer may be formed by using a CVD or ALD process that uses one or more silicon-containing precursor gases to form the deposited layer.

In step 1306, a thermal annealing process (e.g., post-capping anneal) is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, and the capping layer 1404. For example, in some embodiments, a spike annealing process is performed in step 1306, wherein a peak temperature of about 600 ℃ to about 900 ℃ is reached. A post-capping anneal is performed on the partially formed metal gate structure 1000 to smooth the interface, repair dangling bonds, and inject thermal energy into the capping layer 1404.

In step 1307, as shown in fig. 14E, a metal gate electrode layer 1005 is deposited over the treated cap layer 1404, thereby completing the formation of metal gate structure 1000. Metal gate electrode 1005 may be formed via any suitable deposition method described above in connection with fig. 10.

In step 1321, a sacrificial silicon layer 1202 is deposited on the capping layer 1404, as shown in fig. 14F. Step 1321 is performed after surface 1401 of capping layer 1404 has been treated by the single-step plasma hydrogenation and nitridation process of step 1304 and optional air exposure of step 1305.

In step 1322, a thermal annealing process (e.g., post capping anneal) is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, the capping layer 1404, and the sacrificial silicon layer 1202. The thermal annealing process of step 1322 may be substantially similar to the thermal annealing process of step 1306 described above.

In step 1323, the sacrificial silicon layer 1202 is removed from the metal gate structure 1000. Any technically feasible removal process may be employed in step 1323, including a selective wet etch process, a plasma-based dry etch process, a chemical mechanical polishing process, or any combination thereof. The method 1300 then continues to step 1307 where the final layers of the metal gate structure 1000 are deposited.

In step 1331, a sacrificial silicon layer 1203 is deposited over the capping layer 1404, as shown in fig. 14G. Sacrificial silicon layer 1203 may be substantially similar to sacrificial silicon layer 1202 deposited in step 1331. Note, however, that in step 1331, cap layer 1404 has not been treated with a single-step plasma hydrogenation and nitridation process. Thus, the cover layer 1404 may still include the interface layer 1409 as shown.

In step 1332, a thermal annealing process (e.g., post-capping anneal) is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, the capping layer 1404, the interface layer 1409, and the sacrificial silicon layer 1203. The thermal annealing process of step 1332 may be substantially similar to the thermal annealing process of step 1306 described above.

In step 1333, the sacrificial silicon layer 1203, the capping layer 1404, and the interfacial layer 1409 are removed from the metal gate structure 1000 as shown in fig. 14H. Any technically feasible removal process or combination of processes may be employed in step 1333, including a selective wet etch process, a plasma-based dry etch process, a chemical mechanical polishing process, or any combination thereof. Method 1300 then proceeds to step 1334.

In step 1334, a final capping layer 1404f is deposited over the high-k dielectric layer 1003, as shown in fig. 14I. The final cover layer 1404f may be composed of the same material as the cover layer 1404, and the final cover layer may also include the interface layer 1409.

In optional step 1335, the exposed surface 1405 shown in fig. 14I is exposed to air. For example, in some embodiments, the final cap layer 1404f is deposited in one processing system while the next processing step (i.e., step 1336) to be performed on the semiconductor substrate 1001 is performed in a different processing system. Thus, in such an embodiment, the semiconductor substrate 1001 is exposed to air after the deposition of the final cover layer 1404 blinks. In embodiments where the final cap layer 1404f is deposited in one chamber of a multi-chamber processing system and step 1336 is performed in one or two other processing chambers of the same multi-chamber processing system, optional step 1335 is not performed.

In step 1336, a single-step plasma hydrogenation and nitridation process is performed on the surface 1405 of the final cap layer 1404, as shown in fig. 14J. The single-step plasma hydrogenation and nitridation process performed in step 1336 may be substantially similar to the process employed in step 1304. Thus, thickening of the interface layer 1409 can eliminate or reduce during step 1336, thereby removing O atoms present in the final capping layer 1404f, the interface layer 1009, and in some embodiments the high-k dielectric layer 1003. Accordingly, the EOT of the metal gate structure 1000 is reduced without scaling down the thickness 1003A of the high-k dielectric layer 1003.

After performing the single-step plasma hydrogenation and nitridation process in step 1336, method 1300 continues to step 1307 where the final layers of metal gate structure 1000 are deposited. In embodiments where

steps

1336 and 1307 are performed in different processing systems, the semiconductor substrate 1001 must be exposed to air. However, because the plasma nitridation process of step 1336 may completely or nearly completely nitridize the exposed surface 1405 of the final capping layer 1404f, little or no oxidation thereof typically occurs during such air exposure.

In embodiments disclosed herein, a sequential hydrogenation and nitridation process, or a single step hydrogenation and nitridation process, is employed to enable the formation of metal gate structures having a reduced EOT compared to similar structures formed via conventional methods. A plasma hydrogenation process followed by a plasma nitridation process is performed in the metal nitride layer in the film stack, whereby in some embodiments, O atoms disposed within the layers of the film stack are removed, and in some embodiments, the oxygen-containing interfacial layer disposed within the film stack is reduced or prevented from thickening, and in some embodiments, N atoms are added to the layers of the film stack. Thus, the EOT of the metal gate structure is reduced with little or no attendant flat band voltage shift. In addition, the metal gate structure operates with increased leakage currents as low as one-quarter of the increase in leakage current associated with similar metal gate structures formed via conventional techniques.

While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A method of forming a structure in a semiconductor device, the method comprising:

depositing a metal nitride capping layer on the high-k dielectric layer formed over the surface of the substrate; and

exposing the exposed surface of the deposited metal nitride cap layer to a plasma comprising a first gas comprising a hydrogen-containing species and a second gas comprising a nitrogen-containing species, wherein the hydrogen-containing species in the first gas comprises nitrogen.

2. The method of claim 1, further comprising:

depositing a silicon-containing layer on the exposed surface of the deposited metal nitride cap layer after exposing the exposed surface to the plasma;

performing a thermal annealing process on the silicon-containing layer; and

and removing the silicon-containing layer.

3. The method of claim 1, further comprising:

depositing a sacrificial layer on the high-k dielectric layer;

depositing a silicon-containing layer on the sacrificial layer;

performing a thermal annealing process on the sacrificial layer and the silicon-containing layer; and

removing the sacrificial layer and the silicon-containing layer prior to depositing the metal nitride capping layer on the high-k dielectric layer.

4. The method of claim 1, wherein the metal nitride cap layer comprises titanium and nitrogen, and the hydrogen-containing species comprises ammonia, and the nitrogen-containing species comprises nitrogen gas (N)₂)。

5. The method of claim 1, wherein the hydrogen-containing species comprises ammonia and the nitrogen-containing species comprises nitrogen (N) gas₂)。

6. The method of claim 5, wherein exposing the exposed surface to the hydrogen-containing species and the nitrogen-containing species further comprises: exposing the exposed surface to argon (Ar).

7. A method of forming a structure in a semiconductor device, the method comprising:

depositing a high dielectric constant dielectric layer on a semiconductor substrate;

depositing a capping layer on the high-k dielectric layer;

exposing the exposed surface of the capping layer to plasma-excited hydrogen species and plasma-excited nitrogen species;

exposing the exposed surface to air; and

performing a thermal annealing process on the high-k dielectric layer and the capping layer at a specific temperature for a specific time.

8. The method of claim 7, further comprising: prior to depositing the high-k dielectric layer, an interfacial layer comprising silicon dioxide is formed, upon which the high-k dielectric layer is subsequently formed.

9. The method of claim 7, further comprising:

depositing a silicon-containing layer on the exposed surface;

performing a secondary thermal annealing process on the silicon-containing layer; and

and removing the silicon-containing layer.

10. The method of claim 7, further comprising:

depositing a sacrificial layer on the high-k dielectric layer;

depositing a silicon-containing layer on the sacrificial layer;

performing a third thermal annealing process on the sacrificial layer and the silicon-containing layer; and

and removing the sacrificial layer and the silicon-containing layer.

11. The method of claim 7, further comprising: performing an oxygen-free plasma treatment process on a processing chamber in which the exposed surface is exposed to the plasma-excited hydrogen species prior to exposing the exposed surface to the plasma-excited hydrogen species and the plasma-excited nitrogen species.

12. The method of claim 7, wherein a substrate bias is applied to the semiconductor substrate while exposing the exposed surface to the plasma-excited hydrogen species and the plasma-excited nitrogen species.

13. The method of claim 7, wherein the plasma-excited hydrogen species comprise ammonia and the plasma-excited nitrogen species comprise nitrogen gas (N)₂)。

14. A method of forming a structure in a semiconductor device, the method comprising:

depositing a capping layer on the high-k dielectric layer to form a portion of the structure, wherein the portion includes the capping layer and the high-k dielectric layer, and wherein the deposited capping layer has an exposed surface; and

exposing the exposed surface to plasma-excited hydrogen species and plasma-excited nitrogen species, wherein the plasma-excited hydrogen species comprise ammonia and the plasma-excited nitrogen species comprise nitrogen gas (N)₂)。

15. The method of claim 14, wherein a substrate bias is applied to the semiconductor substrate while exposing the exposed surface to the plasma-excited hydrogen species and the plasma-excited nitrogen species.