TWI739176B - Forming method of structure in semiconductor device for modifying effective oxide thickness - Google Patents

Abstract

Embodiments described herein generally relate to enable the formation of a metal gate structure with a reduced effective oxide thickness over a similar structure formed via conventional methods. A plasma hydrogenation process followed by a plasma nitridization process, or a single-step plasma hydrogenation and nitridization process, is performed on a metal nitride layer in a film stack, thereby, according to some embodiments, removing oxygen atoms disposed within layers of the film stack and, in some embodiments, adding nitrogen atoms to the layers of the film stack. As a result, an effective oxide thickness of the metal gate structure is reduced with little or no accompanying flatband voltage shift.

Description

Method for forming structure for improving effective oxide thickness in semiconductor element

The embodiments described herein generally relate to a method and apparatus for processing semiconductor substrates, and more specifically, to hydrogenation and nitridation processes for improving the effective oxide thickness of the film.

In integrated circuits, smaller transistors such as metal oxide semiconductor field effect transistors (MOSFETs) are highly needed. First, smaller transistors enable the formation of more transistors in a given wafer area, thereby reducing the wafer size. Secondly, smaller transistors can usually switch faster than larger transistors, thereby improving chip performance.

One method for reducing the size of MOSFETs is scaling, in which important component sizes such as transistor length, transistor width, and oxide (or dielectric) thickness are reduced proportionally. In this method, the transistor channel resistance does not change as the size of the transistor decreases, and the gate capacitance and RC delay of the transistor decrease in proportion to the size reduction.

However, although the reduction of the dielectric thickness in the MOSFET is critical for scaling the MOSFET to the size required by future technology nodes, there are important trade-offs. Specifically, as the thickness of the conventional oxide/oxynitride dielectric layer in the MOSFET decreases linearly, there is an exponential increase in gate leakage, resulting in increased power consumption. In addition, the thickness of the dielectric layer is now close to a few atomic layers, causing reliability problems. Therefore, any way in which the oxide thickness or effective oxide thickness (EOT) in the transistor can be reduced without exponential increase in gate leakage is highly desirable. This need and other needs are resolved in this disclosure.

The embodiments described herein generally relate to a continuous hydrogenation and nitridation process for reducing the interface and host O atoms in the conductive structure in a semiconductor device. In one embodiment, there is provided a method of forming a structure in a semiconductor element, the method comprising: depositing a high-k dielectric layer on a semiconductor substrate; depositing a capping layer on the high-k dielectric layer to form the structure A part of the deposited covering layer has an exposed surface; and exposing the exposed surface to plasma-excited hydrogen species and plasma-excited nitrogen species. The part of the substrate includes a cover layer and a high-k dielectric.

In one embodiment, a method of forming a structure in a semiconductor device includes: depositing a high-k dielectric layer on a semiconductor substrate; depositing a metal nitride layer on the high-k metal dielectric layer to form a part of the structure , Where the part includes a metal nitride layer and a high-k metal dielectric layer and has a first effective oxide thickness, and the deposited metal nitride layer has an exposed surface; the exposed surface is continuously exposed to the non- The oxidized plasma excited hydrogen species are then exposed to the plasma excited nitrogen species to reduce the first effective oxide thickness to the second effective oxide thickness.

In another embodiment, a method of forming a structure in a semiconductor device includes: depositing a high-k dielectric layer on a semiconductor substrate; depositing a metal nitride layer on the high-k metal dielectric layer; The surface is continuously exposed to plasma-excited hydrogen species and subsequently to plasma-excited nitrogen species; after exposing the exposed surface to plasma-excited hydrogen species and subsequently to plasma-excited nitrogen species, the The exposed surface is exposed to air; and after exposing the exposed surface to air, a thermal annealing process is performed on the high-k dielectric layer and the metal nitride layer at a specific temperature for a specific time.

In another embodiment, a method for forming a structure in a semiconductor device includes: depositing a high-k dielectric layer on a semiconductor substrate; depositing a metal nitride layer on the high-k metal dielectric layer to form the substrate A part, where the part includes a metal nitride layer and a high-k metal dielectric layer and has a first effective oxide thickness, and the deposited metal nitride layer has an exposed surface; by continuously connecting the exposed surface Exposure to non-oxidized plasma excited hydrogen species, and subsequent exposure to plasma excited nitrogen species, reduces the first effective oxide thickness to the second effective oxide thickness.

In another embodiment, a method of forming a structure in a semiconductor element is provided, the method comprising: depositing a high-k dielectric layer on a semiconductor substrate; depositing a capping layer on the high-k metal dielectric layer; Expose the exposed surface of the cover layer to plasma-excited hydrogen species and plasma-excited nitrogen species; expose the exposed surface to air; and perform heat at a specific temperature on the high-permittivity dielectric layer and the cover layer The annealing process reaches a specific time.

In another embodiment, a method of forming a structure in a semiconductor element is provided, the method comprising: depositing a high-k dielectric layer on a semiconductor substrate; and depositing a capping layer on the high-k dielectric layer to form A part of the structure in which the deposited covering layer has an exposed surface; and exposing the exposed surface to plasma excited hydrogen species and plasma excited nitrogen species, wherein the plasma excited hydrogen species include ammonia, and the plasma excited The nitrogen species include nitrogen (N ₂ ). The part of the structure includes a cover layer and a high-k dielectric.

In another embodiment, a method for forming a structure in a semiconductor device is provided, including: depositing a metal nitride coating layer on a high-k dielectric layer formed on the surface of a substrate; and depositing the deposited metal nitride The exposed surface of the cover layer is exposed to a plasma containing a first gas and a second gas. The first gas includes a hydrogen-containing species and the second gas includes a nitrogen-containing species, wherein the hydrogen-containing species in the first gas includes nitrogen.

In another embodiment, a method for forming a structure in a semiconductor element is provided, including: depositing a high-permittivity dielectric layer on a semiconductor substrate; depositing a cover layer on the high-permittivity dielectric layer; The exposed surface is exposed to plasma-excited hydrogen species and plasma-excited nitrogen species; the exposed surface is exposed to air; and a thermal annealing process is performed at a specific temperature on the high-permittivity dielectric layer and the cover layer. Specific time.

In another embodiment, a method for forming a structure in a semiconductor element is provided, which includes: depositing a high-permittivity dielectric layer on a semiconductor substrate; depositing a cover layer on the high-permittivity dielectric layer to form a structure A part, where the part includes a cover layer and a high-permittivity dielectric layer, and the deposited cover layer has an exposed surface; and exposing the exposed surface to plasma-excited hydrogen species and plasma-excited nitrogen species, The hydrogen species excited by the plasma includes ammonia, and the nitrogen species excited by the plasma includes nitrogen (N ₂ ).

The embodiments described herein generally relate to methods and apparatuses for nitriding layers in structures within semiconductor devices formed on substrates. The single-step plasma hydrogenation and nitridation process can be performed on a metal layer or a stack of metal layers included in the conductive structure, such as metal layers that are thermally annealed before depositing the metal capping layer. In various embodiments, a single-step plasma hydrogenation and nitridation process may be performed before the thermal annealing process, after the thermal annealing process, or before and after the thermal annealing process. In various embodiments, the concentration of nitrogen atoms in the conductive structure is advantageously increased, thereby reducing the resistance in the conductive structure. One such conductive structure is shown in Figure 1. Conductive structure with reduced interface and main oxygen

FIG. 1 shows a cross-sectional view of a conductive structure 100 or a contact structure formed as part of a semiconductor element on a semiconductor substrate 110 according to an embodiment of the present disclosure. The conductive structure 100 may be any part of a semiconductor element that is configured to conduct current, and thereby benefit from reduced resistance. In the embodiment shown in Figure 1, the conductive structure 100 is shown as a contact structure for providing electrical contact to the source or drain structure 101, and is illustrated after the conductive structure 100 has been formed, and such as chemical The planarization process of chemical-mechanical polishing (CMP) has been completed on the semiconductor substrate 110. For example, the conductive structure 100 can be a contact structure for a field-effect transistor (FET).

The conductive structure 100 is disposed in the contact well 109 or hole, which is a cavity formed in the insulating material 120. The insulating material 120 (or called shallow trench isolation (STI)) may include one or more dielectric materials, such as _{silicon dioxide (SiO 2} ), silicon nitride (Si ₃ N ₄ ), Or multiple layers of each of the above. The insulating material 120 can be made of high-density plasma (HDP), flowable chemical vapor deposition (FCVD), tetraethyl orthosilicate (TEOS), or the like. form. The conductive structure 100 may include a stack of a plurality of metal layers, for example, a first metal layer 102, a metal nitride layer 103, and at least one conductive portion disposed above the first metal layer 102 and the metal nitride layer 103. The conductive part may include the cover layer 104 and/or the conductive layer 106.

The source or drain structure 101 may be formed of a semiconductor substrate 110 or may be formed of different semiconductor materials deposited on the semiconductor substrate 110. In the latter case, the different semiconductor materials may include germanium silicon, group III-V compound semiconductor materials, or the like. For example, in some embodiments, an epitaxial process may be performed to grow the source or drain structure 101.

The first metal layer 102 is formed on the source or drain structure 101 and includes one or more metals, which are selected to be at the interface with the source or drain structure 101 after a suitable thermal annealing process The silicide 105 is formed. For example, in some embodiments, the first metal layer 102 includes titanium (Ti) or is entirely composed of Ti, and may have a thickness of about 40 Å to about 50 Å. The metal nitride layer 103 is formed on the first metal layer 102 and includes metal nitride, for example, used as a diffusion barrier layer in the conductive structure 100. In some embodiments, the metal nitride layer 103 includes titanium nitride (TiN), tantalum nitride (TaN), and/or tungsten nitride (W ₃ N ₂ ), and may have a thickness of about 10 Å to 20 Å. The capping layer 104 is usually formed on the metal nitride layer 103 after a thermal annealing process. The silicide 105 is formed in the conductive structure 100 by the thermal annealing process, and includes one or more metals. In some embodiments, the conductive structure 100 may include a separately formed conductive layer 106, and the conductive layer may include a metal, such as cobalt, copper, ruthenium, nickel, tungsten, aluminum, or other available metals, or a combination thereof. In some embodiments, the capping layer 104 includes Co, and may have a thickness of about 10 Å to 20 Å. In other embodiments, the capping layer 104 includes a metal (for example, cobalt) that completely fills the remaining part of the contact well 109.

As mentioned earlier, the presence of O atoms in the first metal layer 102 and/or the metal nitride layer 103 adversely affects the effective conductivity of the conductive structure 100. First, the oxide in any metal layer increases the bulk conductivity of the formed metal layer. Secondly, the interface oxide (that is, the metal oxide formed at the interface between the metal nitride layer 103 and the cover layer 104) aggravates the bad adhesion between the metal nitride layer 103 and the cover layer 104, potentially The ground results in a void that significantly reduces the effective cross-sectional area of the conductive structure 100. Unfortunately, there is almost always a certain degree of low concentration of O atoms in the main part of the metal layer of the conductive structure 100. In addition, in many cases, oxides can be formed at higher concentrations on metal surfaces that are exposed to air between manufacturing steps. According to the embodiments of the present disclosure, the presence of host and interface O atoms in the conductive structure 100 can be reduced by continuous hydrogenation and plasma nitridation processes. Fig. 2A to Fig. 2E and Fig. 3A to Fig. 3D show a physical model of the degree of reduction of the main body and interface O atoms in the conductive structure 100 for a continuous process. Reduce the physical model of interface and main body oxygen

2A to 2E are schematic diagrams of the metal nitride layer 103 in the contact structure 100 at various stages of manufacturing the contact structure 100 according to an embodiment of the present disclosure. It should be noted that FIGS. 2A to 2E only show one possible surface end of the metal nitride layer 103, and only show a common TiN structure. In some embodiments, the metal nitride layer 103 may have any other possible surface ends or crystal structures associated with the TiN layer.

In Figure 2A, the portion 200 of the metal nitride layer 103 immediately after the metal nitride layer 103 has been deposited on the first metal layer 102 and before the portion 200 is exposed to the air is schematically shown. The portion 200 includes the surface 201 of the portion 200 on which the cover layer 104 will eventually be deposited. As shown in the figure, the portion 200 has a NACl cubic structure and is mainly composed of Ti and N atoms. In addition, the portion 200 includes a low concentration of bulk O atoms 211 (cross-hatched) generally provided in the bulk region of the portion 200 below the surface 201. The bulk O atoms 211 may be carried in by contamination, which is found in the processing environment during the deposition process used to form the portion 200. In addition, the portion 200 generally includes vacancies 213, which are sites in the crystal lattice of the portion 200 where atoms are being lost. The vacancy 213 is a location where additional oxidation can occur in the portion 200 when the nitride layer 103 is exposed to air. Note that when the metal nitride layer 103 is formed by an atomic layer deposition (ALD) process, it is due to the film nucleation and growth mechanism found in the ALD process. Compared with the traditional chemical vapor deposition (chemical vapor deposition) In vapor deposition; CVD) or physical vapor deposition (PVD) processes, vacancies 213 are relatively common. Therefore, relative to conventional PVD or CVD type processes, one or more embodiments of the disclosure provided herein can provide significant benefits when used on films formed by ALD processes.

In Figure 2B, the portion 200 after removal from the processing system for depositing the metal nitride layer 103 is shown. For example, when preparing for the thermal annealing process, the semiconductor substrate 110 on which the portion 200 is formed may be exposed to air. Generally, due to the difference in cleanliness, thermal management control, and vacuum level requirements required to form most of the current advanced component node applications, conventional heat treatment chambers (such as annealing chambers) are used to form the first The processing systems of a metal layer 102 and a metal nitride layer 103 are executed in different processing systems. Therefore, in Figure 2B, the portion 200 after being exposed to air is shown. As shown in the figure, the surface 201 has been partially oxidized, in which the surface O atoms 212 occupy most or all of the vacancies 213 provided on the surface 201. In some cases, due to the exposure of the portion 200 to the air, some of the vacancies 213 provided in the portion 200 are occupied by the host O atoms 211.

In FIG. 2C, the portion 200 after undergoing a thermal annealing process to form a silicide 105 (as shown in FIG. 1) is shown. Some or all of the remaining vacancies 213 are filled with host O atoms 211 or surface O atoms 212. In some embodiments, the main O atom 211 may also be displaced by a part of the N atom provided in the portion 200. Therefore, the annealing process generally increases the number of both the main O atoms 211 and the surface O atoms 212 in the portion 200. Even when the depth of the surface O atoms 212 on the surface 201 is only one or two monolayers, the effect on the resistivity of the conductive structure 100 can be significant, and it is specifically targeted at smaller device structures, such as nodes with advanced devices ( For example, 65 nm technology node and below technology nodes) related structures.

In Figure 2D, the portion 200 after being exposed to hydrogen atoms according to various embodiments of the present disclosure is shown. The hydrogen atoms and the host O atoms 211 and/or surface O atoms 212 included in the portion 200 are shown. reaction. In some embodiments, as part of the thermal hydrogenation process, main O atoms 211 and/or surface O atoms 212 react with _{hydrogen atoms from thermally dissociated hydrogen (H 2} ), while in other embodiments, it is used as plasma hydrogenation During the process, the main O atoms 211 and/or the surface O atoms 212 react with the hydrogen atoms from the hydrogen-containing plasma.

The thermal hydrogenation process can be performed in a suitable rapid thermal processing chamber under certain processing conditions, including heating the portion 200 to at least about 550°C to about 650°C. The plasma hydrogenation process can be performed in a suitable plasma processing chamber under certain processing conditions. Exemplary plasma processing chambers and plasma processing conditions are each described below for the plasma hydrogenation process. As shown in the figure, the hydrogenation process reduces or otherwise removes all or substantially all of the surface O atoms 212 from the surface 201, thereby leaving vacancies 213. In addition, the plasma hydrogenation process can also remove some or all of the main O atoms 211 disposed under the surface 201.

In FIG. 2E, the portion 200 after undergoing the plasma nitriding process according to various embodiments of the present disclosure is shown. The plasma nitriding process can be performed in a suitable plasma processing chamber under certain processing conditions, and each of an exemplary plasma processing chamber and plasma processing conditions is described below for the plasma nitriding process. In some embodiments, the plasma nitriding process can be performed in the same plasma processing chamber where the plasma hydrogenation process is performed. In addition, no gap occurs between the plasma or thermal hydrogenation process and the plasma nitridation process. That is, after the plasma or thermal hydrogenation process and before the plasma nitriding process, the portion 200 is not exposed to air.

As shown in the figure, the nitridation process results in filling the vacancies 213 with N atoms, so that there are very few or no surface O atoms 212 on the surface 201. Therefore, the surface 201 can reach saturation with N atoms, and therefore, subsequent oxidation of the surface 201 is greatly reduced or eliminated, even when the surface 201 is exposed to air again before the cover layer 104 is deposited. Thus, the adhesion between the surface 201 of the metal nitride layer 103 and the cover layer 104 is improved. In addition, some or all of the vacancies under the surface 201 can be filled with N atoms instead of the main O atoms 211, thereby further improving the conductivity of the metal nitride layer 103, the first metal layer 102, and the conductive structure 100 as a whole.

Figure 3 is an X-ray Photoelectron Spectroscopy (X-ray Photoelectron Spectroscopy; XPS) spectrum 310 of a TiN film deposited and thermally annealed before processing according to an embodiment of the present disclosure and the same after processing XPS spectrum 320 of the deposited and thermally annealed TiN film. The treatment includes a plasma or thermal hydrogenation process, followed by a plasma nitridation process. The thermal annealing process is a rapid thermal process _{in a nitrogen (N 2} ) or ammonia (NH ₃ ) environment at a temperature between about 550° C. and 600° C. At a temperature between about 340°C and 500°C, at a processing pressure between about 10 mTorr and 150 mTorr, at a plasma power between about 250 W and 2000 W, between about 5 sccm and 100 sccm The plasma hydrogenation process is performed in an inductively coupled plasma (ICP) chamber on the substrate base at an H ₂ flow rate between about 250 sccm and 2000 sccm at an argon (Ar) flow rate between about 250 sccm and 2000 sccm. Perform for a duration between about 30 seconds and about 200 seconds. On the substrate base at a temperature between about 350°C and 500°C, at a processing pressure between about 10 mTorr and 100 mTorr, at a plasma power between about 250 W and 2000 W, at about 5 sccm _{At a} flow rate of NH 3 between 100 sccm and 100 sccm _{, at a nitrogen (N 2} ) flow rate between about 300 sccm and 500 sccm, and at an argon (Ar) flow rate between about 20 sccm and 500 sccm, The plasma nitriding process can be performed in the same ICP chamber for a duration between about 30 seconds and about 200 seconds.

As is well known in the art, the XPS spectrum of a TiN film may include multiple peaks, each indicating a different relative concentration of different titanium-containing materials. For example, a Ti-O peak with a binding energy of about 458.5 eV generally indicates the presence of a Ti-O bond, and thus, the presence of O atoms in a titanium-containing material; a Ti-ON peak with a binding energy of about 457 eV generally indicates The presence of Ti-ON bonds, and thus, indicates the presence of N atoms and O atoms in the titanium-containing material; and the Ti-N peak with a binding energy of about 454.9 eV generally indicates the presence of Ti-N bonds, and thus, indicates that there are Nitrogen (N) atoms are present in titanium-containing materials.

For the TiN deposited film after the thermal annealing process described above is performed thereon, the XPS spectrum 310 is associated with the Ti 2p shell, and for the plasma hydrogenation process described above, followed by the plasma nitrogen deposition process described above. After the TiN deposition and thermal annealing film after the chemical process, the XPS spectrum 320 is correlated with the Ti 2p shell. As shown in the figure, compared to the XPS spectrum 310, the peaks indicating the presence of Ti-O bonds and the peaks indicating the presence of Ti-ON bonds in the XPS spectrum 320 are significantly lower, thereby clearly indicating the presence in the TiN film The O atom decreases. In addition, the peak indicating the presence of the Ti-N bond in the XPS spectrum 320 is significantly higher than in the XPS spectrum 310, thereby clearly indicating an increase in the concentration of N atoms in the TiN film. Therefore, by performing the hydrogenation and nitridation process after the annealing process, the concentration of O atoms in the metal nitride film 103 can be significantly reduced, and the concentration of N atoms in the metal nitride film 103 can be significantly increased.

FIGS. 2A to 2E and 3 show the effect of the continuous hydrogenation and nitridation process on the metal nitride layer 103 after annealing. In some embodiments, using a plasma or thermal hydrogenation process on the portion 200 before the thermal annealing process, followed by a plasma nitriding process may have similar beneficial effects. Specifically, due to the plasma nitridation process (as shown in Figure 2E), the surface 201 can be mostly or fully saturated with N atoms, and subsequent air exposure and thermal annealing of the surface 201 result in little or no oxidation. Therefore, the concentration of the host O atoms 211 found in the portion 200 and the concentration of the surface O atoms 212 on the surface 201 do not increase significantly.

System overview for continuous hydrogenation and nitridation

Figure 4 is a schematic cross-section of a plasma processing chamber 400 configured to implement one or more aspects of the present disclosure. The plasma processing chamber 400 can be any suitable plasma processing chamber, such as an inductively coupled plasma (ICP) processing chamber. As shown in FIG. 4, the processing chamber 400 may include a chamber wall 406, a chamber cover 408, and a substrate support base 404 provided in the chamber wall 406. Generally, the chamber wall 406 is coupled to electrical ground 416. The chamber cover 408 can be made of any suitable dielectric (such as quartz). For some embodiments, the chamber cover 408 may assume a different shape (for example, a dome shape). In some embodiments, the chamber cover 408 may be coated with a ceramic coating (such as yttrium-containing oxide) to resist plasma species. In one embodiment, the ceramic coating is a high performance material (HPM), which is composed of Y ₄ Al ₂ O ₉ compound and solid solution Y _2-x Zr _x O ₃ (Y ₂ O _3- ZrO ₂ solid solution) constituted. The ceramic coating may have a thickness varying from about 100 microns to about 300 microns, such as about 200 microns.

On the chamber cover 408, a radio frequency (RF) antenna including at least one induction coil element 410 may be provided (two coaxial coil elements are shown). In some embodiments, the induction coil element 410 may be provided around at least a portion of the chamber wall 406. One end of the induction coil element 410 may be coupled to the RF power source 414 via the first impedance matching network 412, and the other end may be connected to the electrical ground 417 as shown in the figure. At a tunable frequency ranging from 2 to 160 MHz, the power supply 414 is typically capable of generating up to 10 kilowatts (kW) of power, of which 13.56 MHz is the common operating frequency. The RF power supplied to the induction coil element 410 can be pulsed (that is, switching between on and off states) or power cycling (that is, changing the power input from a high level to a low level), and its frequency varies from 1. In the range of change to 100 kHz.

The shield electrode 418 may be inserted between the induction coil element 410 of the RF antenna and the chamber wall 408. The shield electrode 418 may alternately be electrically floating or coupled to the electrical ground 419 via any suitable member that is used to make and break the electrical connection, such as the switch 420 shown in FIG. 4.

For some embodiments, the detector 422 may be attached to the chamber wall 406 to facilitate the decision when to excite the gas mixture in the chamber 400 into plasma. For example, the detector 422 can detect the radiation emitted by the excited gas or use optical emission spectroscopy (OES) to measure the light associated with the generated plasma at one or more wavelengths. strength.

The base 404 may be coupled to the bias power supply 426 via the second impedance matching network 424. Similar to the RF power supply 414, the bias power supply 426 is generally capable of generating an RF signal with a tunable frequency ranging from 2 to 160 MHz and a power between 0 and 10 kW. Alternatively, the bias power supply 426 may be a direct current (DC) or pulsed DC source.

In operation, a substrate 428 (such as a semiconductor substrate) may be placed on the base 404, and a processing gas may be supplied from the gas panel 430 through the inlet port 432 in an effort to form the gas mixture 434. The following describes common processing gases that can be used in one or more of the processes described herein. The inlet port 432 may be coated with a ceramic coating (such as HPM). The gas mixture 434 may be excited as a plasma 436 in the processing chamber 400 by applying power from the RF power source 414. The pressure in the internal volume of the processing chamber 400 can be controlled using a throttle valve 438 and a vacuum pump 440. In some embodiments, the temperature of the chamber wall 406 may use a liquid-containing pipe (not shown) that travels through the chamber wall 406 or is embedded in the chamber wall 406 (for example, a heating cylinder or coil) or wound in the processing chamber. The heating elements around the chamber 400 (eg, heater packs or bands) are controlled.

The temperature of the substrate 428 can be controlled by stabilizing the temperature of the base 404. In some embodiments, helium (He) gas from the gas source 442 may be provided via a gas pipe 444 to a channel (not shown) formed in the base surface below the substrate 428. Helium can promote heat transfer between the base 404 and the substrate 428. During processing, the base 404 can be heated to a steady state temperature, and then helium can promote uniform heating of the substrate 428. The base may be so heated by a heating element (not shown), such as a resistive heater embedded in the base 404, or a lamp usually aimed at the base 404 or the substrate 428 thereon. Using this thermal control, the substrate 428 can be maintained at a temperature between approximately 20 degrees Celsius and 350 degrees Celsius (°C).

To allow control of the components of the processing chamber 400 as described herein, a controller 446 may be provided. The controller 446 may include a central processing unit (CPU) 448, a memory 450, and a support circuit 452 for the CPU 448. The controller 446 can interface with the RF power supply 414, the switch 420, the detector 422, and the bias power supply 426.

The controller 446 can be any suitable type of general-purpose computer processor that can be used in industrial settings for controlling various chambers and sub-processors. The memory 450 or other computer-readable media used for the CPU 448 can be one or more of any easily available memory form, such as random access memory (RAM), read-only memory (read only memory; ROM), floppy disk, hard disk, or any other form of digital storage (local or remote). The support circuit 452 may be coupled to the CPU 448 in an effort to support the processor in a conventional manner. These circuits may include cache memory, power supplies, clock circuits, input/output (I/O) circuit systems and subsystems, and the like. For some embodiments, the techniques for stimulating and maintaining plasma disclosed herein can be stored in the memory 450 as a software routine. The software routines may also be stored and/or executed by a second CPU (not shown), which is located at the remote end of the hardware controlled by the CPU 448.

According to some embodiments of the present disclosure, the thermal or plasma hydrogenation process is followed by a plasma nitridation process, hereinafter referred to as a "continuous hydrogenation/nitridation process", on the substrate before and/or after thermal annealing is performed on the substrate implement. The continuous hydrogenation/nitridation process may include a capacitively coupled plasma process or an inductively coupled plasma process. In some embodiments, the plasma used in the hydrogenation/nitridation process can be formed in a remote plasma source outside the processing chamber 400, and in other embodiments, the plasma used in the plasma process can be formed in situ Formed, that is, formed in the processing chamber 400. Hydrogenation and nitridation can be performed in the same step, which is hereinafter referred to as a "single-step plasma hydrogenation and nitridation process". In some embodiments, the plasma used in the single-step plasma hydrogenation and nitridation process can be formed in a remote plasma source outside the processing chamber 400, and in other embodiments, the plasma used in the plasma process The slurry may be formed in situ, that is, formed in the processing chamber 400.

In the plasma hydrogenation process, H radicals and/or ions excited by the plasma react with the host O atoms 211 and/or the surface O atoms 212 to generate vacancies 213. In the case of the thermal hydrogenation process, the dissociated H atoms react with the host O atoms 211 and/or the surface O atoms 212 to generate vacancies 213. During the nitridation process, N radicals and/or ions occupy the vacancies 213.

Note that during the plasma hydrogenation process, due to the presence of H atoms, such as dissociated H atoms, H radicals, and/or H ions, the processing environment in the processing chamber 400 usually includes a relatively low concentration. The O atom. Therefore, the processing environment in the processing chamber 400 during the plasma hydrogenation process is compared with the processing environment in the processing chamber 400 during the nitridation process or the processing environment in the processing chamber during the deposition of the metal nitride layer. A lower concentration of O atoms can be included. However, for both hydrogenation or nitridation, a lower concentration of O atoms is generally advantageous. Therefore, in some embodiments, before the plasma hydrogenation process and/or the nitridation process, the processing chamber can be _{adjusted by a plasma process (such as an H 2} process) to remove any trace O species.

When the metal nitride layer to be processed by the hydrogenation/nitridation process or the single-step plasma hydrogenation and nitridation process described herein is a thin film with a thickness of about 200 Å or less, the ICP process is generally less easy to perform hydrogenation or nitridation. The metal nitride layer is destroyed during nitriding. Specifically, in the ICP process, the plasma sheath is usually smaller than the plasma sheath in the CCP chamber, and thus the ions passing through it usually have a proportionally smaller energy, for example, on the order of 10 times EV , Such as 10 to 20 eV. In contrast, the ions in the CCP chamber typically have energy on the order of 100 times eV (eg, >200-400 eV), and can subsequently cause significant damage to the metal nitride layer. In addition, due to the higher density of ions, free radicals, and other plasma excitations that are usually formed in the ICP processing chamber and close to the substrate relative to the remote plasma source used in CCP and other types of processing chambers Species, the ICP process can provide more oxygen removal from the metal nitride layer than by using CCP or remote plasma processes. In contrast, the concentration of free radicals from CCP and remote plasma sources is relatively low.

In the embodiment where the plasma for the plasma process is formed in situ, the plasma may be formed through the induction coil element 410, the first impedance matching network 412, the RF power supply 414, and in some embodiments, through the second The impedance matching network 424 and the bias power supply 426 are formed. In such an embodiment, the plasma process may include introducing one or more process gases into the process chamber 400, the process gases being selected to generate certain plasma species (ie, ions, neutral atoms, and / Or free radicals). More specifically, in the case of a plasma hydrogenation process, one or more processing gases are selected to generate plasma excited hydrogen species, and in the case of a plasma nitridation process, one or more processing gases are selected Select the nitrogen species that is excited to generate plasma. Therefore, for the plasma hydrogenation process, one or more process gases may include hydrogen (H ₂ ) and/or D ₂ , and for the plasma nitridation process, one or more process gases may include nitrogen (N ₂ ) Or ammonia (NH ₃ ). Alternatively or additionally, the plasma process may include introducing one or more carriers and/or inert gases (such as argon (Ar)) into the processing chamber 400. For a single-step plasma hydrogenation and nitridation process, one or more processing gases may include hydrogen (H ₂ ), D ₂ , nitrogen (N ₂ ), ammonia (NH ₃ ), or hydrazine (N ₂ H ₄ ).

In some embodiments, the plasma hydrogenation process mainly includes forming a plasma, the plasma including _{a process gas consisting essentially of hydrogen (H 2} ), and the process gas forms a reactive species provided by the plasma. It will be noted that the use of plasma (for example, inductively coupled plasma) (which is _{formed using H 2} ) to form hydrogen-containing species will have significantly more hydrogen-containing species _{than a thermal hydrogenation process using a process gas containing H 2} Hydrogen radicals and ions therefore improve the effectiveness of the plasma hydrogenation process and reduce undesirable reactions found when using impure hydrogen-containing reaction gas.

In some embodiments, one or more process gases are excited by an RF power source (such as RF power source 414). The RF power can be pulsed at a duty cycle of 2% to 70%, and can vary from about 100 W to about 2500 W. The RF power can be a continuous wave varying from about 100 W to about 2500 W. The processing chamber may have a chamber pressure that varies from about 10 mTorr to about 200 mTorr during the plasma process, and the processing temperature (for example, the temperature of the base 404) may vary from 20°C to about 500°C.

In an exemplary embodiment, at a processing temperature between about 400° C. and about 500° C., at a chamber pressure between about 5 mTorr and about 20 mTorr, an RF between about 1000 W and about 2000 W At power, and at a bias voltage between about 175 V and about 250 V, where the H ₂ flow rate is between about 20 sccm and about 40 sccm and the Ar flow rate is between about 400 sccm and about 500 sccm, the electrical The slurry hydrogenation process has a duration between about 50 seconds and about 300 seconds. The hydrogen species excited by the plasma generated by the plasma inside the processing chamber 400 can reduce the exposed surface of the metal nitride layer (for example, the metal nitride layer 103) of the partially formed conductive structure (for example, the conductive structure 100) Some or all of the oxides present on it. In some embodiments, the hydrogen species excited by the plasma can also reduce some or all of the O atoms present in the metal nitride layer of the conductive structure (such as the first metal layer 102 of the conductive structure 100) or the host material of other metal layers. . This reduction of O atoms is described above in conjunction with Figure 2D and Figure 3B.

In another exemplary embodiment, at a processing temperature between about 400° C. and about 500° C., at a chamber pressure between about 5 mTorr and about 25 mTorr, between about 1000 W and about 2000 W Under the RF power of about 175 V and about 250 V, the NH ₃ flow rate is between about 20 sccm and about 40 sccm, and the N ₂ flow rate is between about 400 sccm and about 600 sccm. And the Ar flow rate is between about 400 sccm and about 500 sccm, and the plasma nitriding process is performed for a duration between about 50 seconds and about 300 seconds. The nitrogen species excited by the plasma generated by the plasma inside the processing chamber 400 may saturate the exposed surface (for example, the surface 201 of the metal nitride layer 103) of the metal nitride layer of the partially formed conductive structure. In some embodiments, the nitrogen species excited by the plasma can also fill the vacancies existing in the metal nitride layer of the conductive structure or the host material of other metal layers. This nitridation is described above in conjunction with Figures 2E and 3C.

In some embodiments, at a chamber pressure between about 10 mTorr and about 100 mTorr, at a processing temperature (such as substrate base temperature) between about 350° C. and about 500° C., where the RF power is about 300 W And about 2000 W, _{the flow rate of NH 3} is between about 5 sccm and about 100 sccm, _{the flow rate of N 2} is between about 50 sccm and about 1000 sccm, and the flow rate of helium (He) is between about 1 to about Between 1000 sccm, perform a single-step plasma hydrogenation and nitridation process for a duration of about 30 seconds and about 150 seconds, and apply a substrate bias, where the frequency is from about 2 MHz to about 160 MHz, and the bias power is about Between 0 kW and approximately 10 kW.

In some embodiments, at a chamber pressure between about 15 mTorr and about 25 mTorr, at a processing temperature between about 350° C. and about 500° C., where the RF power is between about 300 W and about 1600 W , _{The flow rate of NH 3} is between about 10 sccm and about 40 sccm, _{the flow rate of N 2} is between about 200 sccm and about 550 sccm, and the flow rate of Ar is between about 200 sccm and about 550 sccm. The slurry hydrogenation and nitridation process has a duration between about 85 seconds and about 95 seconds, and no substrate bias power is applied.

In embodiments where the plasma for the plasma process is formed remotely, the plasma can be formed via any technically feasible remote plasma source. In such an embodiment, the plasma process may include introducing one or more process gases into the remote plasma source, the process gases being selected to generate plasma-excited hydrogen species or plasma-excited nitrogen species. Alternatively or additionally, the remote plasma process may include introducing one or more carriers and/or inert gases (such as argon (Ar)) into the remote plasma source. The plasma species generated at the remote end then flows into the processing chamber 400, and processes the metal nitride layer of the conductive structure formed on the substrate provided in the processing chamber 400. As described above, depending on whether the plasma species is a plasma-excited hydrogen species or a plasma-excited nitrogen species, the interface and host O atoms in the metal nitride layer are reduced, or the nitridation of the metal nitride layer is enhanced.

In some embodiments, unlike the plasma hydrogenation process, a thermal hydrogenation process may be used to expose the metal nitride layer to hydrogen atoms. In such an embodiment, the thermal hydrogenation process usually occurs at a high temperature (for example, between about 500°C and about 650°C). At such a high temperature, the H ₂ gas dissociates into individual atoms, which can subsequently react with the O atoms in the metal nitride layer 103 and generate vacancies 213. In addition, in such an embodiment, the thermal hydrogenation process is usually performed in a processing chamber different from the processing chamber 400. For example, in some embodiments, the thermal hydrogenation process is performed in a rapid thermal processing chamber. In this embodiment, the silicidation process can be performed simultaneously with the thermal hydrogenation process, thereby eliminating the subsequent annealing process.

In an embodiment in which a thermal annealing process is used to expose the metal nitride layer to hydrogen atoms, the plasma nitridation process is performed without a break, which exposes the metal nitride layer 103 to the air. For example, in such an embodiment, one chamber of the multi-chamber processing system may be configured to perform a thermal hydrogenation process, and another chamber of the same multi-chamber processing system may be configured to perform a plasma nitriding process . Therefore, the substrate on which the metal nitride layer 103 is formed can undergo a thermal hydrogenation process, and then be directly transferred to the plasma nitriding chamber without being exposed to air.

Figure 5 is a top plan view of a multi-chamber processing system 500 configured to implement one or more aspects of the present disclosure. The multi-chamber processing system 500 is configured to perform one or more manufacturing processes on a separate substrate (such as a silicon wafer) for forming semiconductor devices. The multi-chamber processing system 500 includes some or all of the transfer chamber 506, buffer chamber 508, single wafer loading gates 510 and 512, processing chambers 514, 516, 518, 520, 522, and 524, and preheating chamber 523 And 525, and robots 526 and 528. The single wafer load gates 510 and 512 may include a heating element 513 and attached to the buffer chamber 508. The processing chambers 514, 516, 518, and 520 are attached to the transfer chamber 506. The processing chambers 522 and 524 are attached to the buffer chamber 508. The operation of the multi-chamber processing system 500 is controlled by the computer system 530. The computer system 530 may be any element or combination of elements configured to implement the operations of the present invention provided herein. Therefore, the computer system 530 may be a controller or a controller array and/or a general-purpose computer configured with software, and when the software is executed, the software performs the operations of the present invention. An example of a suitable multi-chamber processing system 500 is the Endura® RTM CL system manufactured by Applied Materials, Inc., Santa Clara, California, USA.

Each of the processing chambers 514, 516, 518, 520, 522, and 524 can be configured to fabricate conductive structures (such as contact structures for field-effect transistors (FETs)) in semiconductor devices One or more processing steps are executed at the time. More specifically, the processing chambers 514, 516, 518, 520, 522, and 524 may include one or more metal deposition chambers, surface cleaning and preparation chambers, thermal annealing and/or thermal hydrogenation chambers, and electrical Slurry hydrogenation/nitridation chamber.

For example, for a contact structure including a Ti-TiN-Co stack formed on a silicon source or drain structure, in some embodiments, the multi-chamber processing system 500 can be configured to be used in the manufacturing process of such a conductive structure Several processing steps are executed consecutively. In such an embodiment, the processing chamber 514 can be configured to perform surface cleaning and preparation processes on the exposed surface of the silicon source or drain structure, and the processing chamber 516 can be configured to perform surface cleaning and preparation processes on the silicon source or drain structure. Ti and TiN layers are continuously deposited on the drain structure, and the processing chamber 522 and/or 524 can be configured to perform rapid thermal processing (RTP) on the Ti/TiN layer and the source/or drain structure or Other thermal annealing processes to form silicides, the processing chamber 518 can be configured to deposit a Co cap layer on the annealed Ti/TiN layer, and the processing chamber 520 can be configured to perform a hydrogenation process before or after the thermal annealing process and Subsequent nitriding process. Therefore, in such an embodiment, a complete contact structure can be formed without occurrence of vacancies and undesired oxidation of the resultant one or more layers of contact structure.

In an alternative embodiment, not all processing steps for forming a complete contact structure are performed on a single multi-chamber processing system 500. For example, in some embodiments, the multi-chamber processing system 500 may include a metal deposition processing chamber, and the thermal annealing and silicidation process may be performed on different substrate processing systems. In this embodiment, the vacancy occurs before the thermal annealing process, and it is known that such vacancy can increase the presence of O atoms on the interface surface of the metal nitride layer and in the host material of the metal nitride layer of the contact structure . However, before the disconnection, since the multi-chamber processing system 500 can be configured with both a metal deposition chamber and one or more plasma processing chambers, continuous plasma (or thermal) hydrogenation/plasma nitridation can be performed Process or single-step plasma hydrogenation and nitridation process. Therefore, the multi-chamber processing system 500 may be configured to perform continuous operations on the substrate after depositing the first metal layer 102 and the metal nitride layer 103 but before removing the substrate from the multi-chamber processing system 500 and exposing the substrate to air. Hydrogenation/nitridation process or single-step plasma hydrogenation and nitridation process. As discussed above, the nitridation of the exposed surface of the metal nitride layer 103 before the disconnection can greatly reduce the oxidation of the exposed surface during the disconnection and during the subsequent thermal annealing process.

In some embodiments, the multi-chamber processing system 500 may include one or more thermal annealing and plasma processing chambers. In such an embodiment, the continuous hydrogenation and nitridation process or the single-step plasma hydrogenation and nitridation process can be performed after the thermal annealing process, thereby removing the pre-annealing gap and the introduction of the thermal annealing process itself. O atom. Generally, due to the high temperatures reached by the processing components (eg, seals, processing kit components, pumps, etc.) during heat treatment, the thermal annealing process cannot maintain the desired low oxygen level required for most advanced component nodes.

Alternatively or additionally, a continuous hydrogenation/nitridation process or a single-step plasma hydrogenation and nitridation process may be performed before the thermal annealing process. Therefore, in this embodiment, even if no vacancy occurs after the metal nitride layer 103 is deposited and before the thermal annealing process, the interface O atoms and the O atoms present in the main part of the metal nitride layer can also be performed Reduce or eliminate before the thermal annealing process. Thus, in some configurations, the continuous hydrogenation and plasma nitridation process or the single-step plasma hydrogenation and nitridation process can be performed before the thermal annealing process and also after the thermal annealing process but before the air interruption occurs.

In some embodiments, the multi-chamber processing system 500 may include one or more metal deposition chambers and one or more plasma processing chambers configured to deposit the capping layer 104 and/or the conductive layer 106 to perform Continuous hydrogenation and nitridation process or single-step plasma hydrogenation and nitridation process. In such an embodiment, the continuous hydrogenation and nitridation process or the single-step plasma hydrogenation and nitridation process can be performed before depositing the capping layer in the conductive structure, thereby removing the heat caused by the air interruption and the formation of the silicide 105. The interface and host O atoms introduced by the annealing process. Note that in this embodiment, no gap occurs between the continuous hydrogenation and nitridation process and the deposition of the capping layer 104 and/or the conductive layer 106. Therefore, in such an embodiment, when a gap occurs between the thermal annealing process and the deposition of the capping layer 104, the interface O atoms and the O atoms present in the main part of the metal nitride layer can be reduced or eliminated. Reduce the main body and interface oxygen in the contact structure

FIG. 6 illustrates a flowchart of processing steps for reducing the main body and interface oxygen in the contact structure according to some embodiments of the present disclosure. FIGS. 7A to 7E are schematic cross-sectional views of semiconductor devices at different stages of the manufacturing process corresponding to FIG. 6 according to various embodiments of the present disclosure. Although FIGS. 7A to 7E show the first metal layer 102 and the metal nitride layer filling the hole 109 as selectively deposited (for example, as shown in FIG. 1, the layer is not formed conformally above the hole 109) 103 and the cover layer 104, which are not intended to be limited to the scope of the disclosure described herein, and therefore the first metal layer 102, the metal nitride layer 103 and the cover layer 104 can be selectively formed or non-selectively formed, and include a Or more additional layers.

Before step 601, a cleaning process or other surface preparation process may be performed on the surface of the semiconductor substrate, on which contacts will be formed, such as the exposed surface 701 of the source or drain structure 101 in FIG. 7A. In some embodiments, a dry etching process may be performed to remove the original oxide of the substrate 701. For example, a conventional plasma etching or remote plasma-assisted dry etching process can be performed, such as the SiCoNi ^TM etching process available from Applied Materials in Santa Clara, USA. In the SiCoNi ^™ etching process, the surface of the semiconductor substrate on which the contacts are to be formed is exposed to H ₂ , NF ₃ , and/or NH ₃ plasma species, for example, hydrogen and fluorine species excited by the plasma. For example, in some embodiments, such a surface may undergo simultaneous exposure to H ₂ , NF ₃ , and NH ₃ plasma. The SiCoNi ^TM etching process can be performed in a SiCoNi ^TM pre-cleaning chamber, which can be integrated into one of various multi-processing platforms, including the Producer ^TM GT, Centura ^TM AP and Endura platforms available from Applied Materials.

As shown in FIG. 7B, the method 600 starts in step 601, in which a first metal layer 102 and a metal nitride layer 103 are deposited on a semiconductor substrate. For example, in some embodiments, a Ti layer is deposited, followed by a TiN barrier layer. Any suitable PVD, CVD, or ALD process can be used to perform this deposition. Therefore, the deposition process can be a selective process or a non-selective deposition process. In the selective deposition process, the first metal layer 102 and the metal nitride layer 103 are deposited on the surface 701, but not on other surfaces of the semiconductor substrate 110. In the non-selective process, the first metal layer 102 and the metal The nitride layer 103 may be deposited on all unshielded surfaces of the semiconductor substrate 110. In some embodiments, after the surface preparation process described above, the deposition of step 601 is performed without interruption. That is, the semiconductor substrate is not exposed to the atmosphere between the surface preparation process and the deposition in step 601. In such an embodiment, the deposition and surface preparation processes of step 601 can be respectively performed by different chambers on the same multi-chamber processing system (such as the multi-chamber processing system 500).

In step 603, the thermal annealing process is performed on the semiconductor substrate 110, which includes the first metal layer 102, the metal nitride layer 103, and the source or drain structure 101. As shown in FIG. 7C, the silicide 105 is formed by the thermal annealing process. For example, in some embodiments, a tip annealing process that reaches a peak temperature between about 500° C. and about 600° C. may be performed in step 603. Alternatively, any other suitable annealing process may be performed to form the silicide 105 between the source or drain structure 101 and the first metal layer 102 deposited in step 601.

In some embodiments, the chamber for performing step 603 may be configured as a chamber for performing the metal deposition of step 601 of the same multi-chamber processing system. Therefore, in such an embodiment, after the metal deposition in step 601, the thermal annealing process in step 603 is performed without vacancies, thereby further reducing the presence of interface O on the surface 702 of the metal nitride layer 103 . However, for the reasons discussed above, such a configuration of a multi-chamber processing system is not common, and a gap usually occurs between step 601 and step 603.

In step 604, a continuous hydrogenation/plasma nitridation process is performed on the surface 702 of the metal nitride layer 103. That is, as shown in FIG. 7D, the surface 702 is exposed to hydrogen atoms and exposed to plasma excited nitrogen species 703. In some embodiments, a plasma hydrogenation process is performed in step 604, followed by a plasma nitridation process. In the embodiment of the plasma hydrogenation process of the hydrogenation process, both the plasma hydrogenation process and the plasma nitridation process can be performed in the processing chamber 400 and use the processing parameters described above in conjunction with FIG. 4. Alternatively, the plasma hydrogenation process can be performed in one of the processing chambers 514, 516, 518, 520, 522, and 524 of the multi-chamber processing system 500, and the plasma nitriding process can be performed in the processing chambers 514, 516, 516, 518, 520, 522, and 524 are executed in another one.

As mentioned earlier, in some embodiments, the surface 702 of the metal nitride layer 103 is exposed to hydrogen atoms through a thermal hydrogenation process. In this embodiment, the thermal hydrogenation process of step 604 is performed in one of the processing chambers 514, 516, 518, 520, 522, and 524 of the multi-chamber processing system 500, for example, configured to use H ₂ gas As a rapid thermal processing chamber for processing gas. In addition, in this embodiment, the plasma nitriding process is performed in another of the processing chambers 514, 516, 518, 520, 522, and 524, which is similar to the plasma processing chamber 400 in Figure 4 Processing chamber. Therefore, even though the thermal hydrogenation process and the plasma nitriding process are performed in different processing chambers, no gap occurs between these two processes.

In step 605, as shown in FIG. 7E, the capping layer 104 is deposited on the annealed first metal layer 102 and the metal nitride layer 103. For example, in one embodiment, the metal covering layer is a Co layer or a cobalt-containing alloy layer. Because the interface O atoms that can be present on the surface 702 of the metal nitride layer 103 are removed in step 604, the adhesion between the covering layer 104 and the metal nitride layer 103 is improved, which is better than that formed by conventional techniques. The adhesion force in the contact structure. In addition, removing the O atoms in the metal nitride layer 103 reduces the resistivity of the conductive structure 100.

In some embodiments, steps 604 and 605 are performed on the same multi-chamber processing system, so that no interruption occurs after the continuous hydrogenation and nitridation process of step 604. Subsequently, the oxidation of the metal nitride layer 103 that can occur during exposure to the atmosphere is avoided. In other embodiments, the processing chamber used to perform the continuous hydrogenation and nitridation processing of step 604 may be configured on a multi-chamber processing system different from the processing chamber used to perform step 605. Note that, in this embodiment, the nitridation process of step 604 completely nitrates the surface of the metal nitride layer 103, thereby minimizing or otherwise preventing the possible occurrence of a gap between steps 604 and 605. Oxidation.

Figure 8 illustrates a flow chart of processing steps for reducing body and interface oxygen in the contact structure according to some embodiments of the present disclosure. Before step 801, as described above in conjunction with FIG. 7, a cleaning process or other surface preparation processes can be performed.

The method 800 starts in step 801, where a metal layer 102 and a metal nitride layer 103 are deposited on the source or drain structure 101. Step 801 may be substantially similar to step 601 in method 600.

In step 802, a continuous hydrogenation/plasma nitridation process is performed on the surface 702 of the metal nitride layer 103. That is, the surface 702 is exposed to hydrogen atoms and exposed to plasma excited nitrogen species. Step 802 may be substantially similar to step 604 in method 600. However, it is noted that unlike step 604, the continuous hydrogenation/plasma nitridation process of step 802 is performed before the thermal annealing process. Furthermore, in some embodiments, step 802 is performed in a chamber configured as part of a multi-chamber processing system that includes a thermal annealing chamber (such as a rapid thermal processing chamber) for performing step 803. In this embodiment, since such O atoms are removed before the annealing process in step 803, the influence of O atoms in the first metal layer 102 and the metal nitride layer 103 deposited in step 801 is further reduced.

In step 803, the thermal annealing process is performed on the semiconductor substrate 110, which includes the first metal layer 102, the metal nitride layer 103, and the source or drain structure 101. Step 803 may be substantially similar to step 603 in method 600. Alternatively, in an embodiment in which the thermal hydrogenation process occurs in step 802, the thermal annealing process is performed in step 802, and step 803 may be skipped. For example, in some embodiments, the thermal annealing process for forming the silicide 105 is performed in the same processing chamber as the thermal hydrogenation process in step 802. In such an embodiment, immediately before the thermal hydrogenation process or immediately after the thermal hydrogenation process, the thermal annealing process may be performed simultaneously with the thermal hydrogenation process.

In an optional step 804, the plasma treatment process is performed on the surface 702 of the metal nitride layer 103. Step 804 may be substantially similar to step 604 in method 600. Therefore, in the embodiment of the method 800 in which step 804 is performed, a continuous hydrogenation/nitridation process is performed before and after the thermal annealing process of step 803. In some embodiments, the continuous hydrogenation/nitridation process performed in step 804 is substantially the same as the plasma treatment process performed in step 802. In other embodiments, the continuous hydrogenation/nitridation process of step 804 may be different from the continuous hydrogenation/nitridation process of step 802. For example, the processing parameters of the continuous hydrogenation/nitridation process used in step 802 may be different from the processing parameters of the continuous hydrogenation/nitridation process used in step 804.

In step 805, the capping layer 104 and/or the conductive layer 106 are deposited on the annealed first metal layer 102 and the metal nitride layer 103. Step 805 may be substantially similar to step 605 in method 600. Similarly, in some embodiments, steps 804 and 805 can be performed on the same multi-chamber processing system, so that no interruption occurs after the plasma processing process of step 804. Subsequently, the oxidation of the metal nitride layer 103 that can occur during exposure to air is avoided, and the adhesion between the cover layer 104 and the metal nitride layer 103 is improved, which is better than the contact structure formed by the conventional technology Adhesion in the.

Figure 9 illustrates a flow chart of processing steps for reducing the body and interface oxygen in the contact structure according to some embodiments of the present disclosure. Before step 901, as described above in connection with the method 600, a cleaning process or other surface preparation processes may be performed. As shown in the figure, the method 900 starts in step 901, where a first metal layer 102 and a metal nitride layer 103 are deposited on the source or drain structure 101. Step 901 may be substantially similar to step 601 in method 600. In step 902, a continuous hydrogenation/nitridation process is performed on the surface 702 of the metal nitride layer 103. Step 902 may be substantially similar to step 802 in method 800. In step 903, the thermal annealing process is performed on the semiconductor substrate 110, which includes the first metal layer 102, the metal nitride layer 103, and the source or drain structure 101. Step 903 may be substantially similar to step 603 in method 600. In step 905, the capping layer 104 is deposited on the annealed first metal layer 102 and the metal nitride layer 103. Step 905 may be substantially similar to step 605 in method 600. Therefore, in the method 900, the continuous hydrogenation/nitridation process is performed before the thermal annealing process in step 903 and not after the thermal annealing process in step 903. Continuous hydrogenation/nitridation processes usually include plasma or thermal hydrogenation processes and plasma nitridation processes.

Although the methods 600 and 800 for forming contact structures on a substrate are described, the methods 600 and 800 can also be used to form other conductive structures on the substrate. Therefore, any conductive structure including a metal nitride layer can benefit from being formed by the method 600 or 800. Metal gate structure with reduced EOT

According to various embodiments of the present disclosure, continuous hydrogenation and nitridation processes are used to reduce the effective oxide thickness (EOT) of the stack when manufacturing the high-k dielectric/metal gate stack. In such an embodiment, the stacked EOT is reduced without loss of leakage increase and flat-band voltage offset, which is known to be in the high-permittivity dielectric layer of the stack. Occurs when the thickness is only reduced or otherwise scaled down via conventional techniques. Figure 10 shows one such stack.

FIG. 10 shows a cross-sectional view of a metal gate structure 1000 formed according to an embodiment of the present disclosure. The metal gate structure 1000 is formed on the semiconductor substrate 1001 as a part of a semiconductor element (such as a MOSFET or other FET). The metal gate structure 1000 is a stack of multiple material layers formed on the semiconductor substrate 1001, and includes, for example, an interface layer 1002 provided on the semiconductor substrate 1001, a high-permittivity dielectric layer 1003 provided on the interface layer 1002, A metal nitride coating layer 1004 is provided on the high-k dielectric layer 1003, and a metal gate electrode layer 1005 is provided on the metal nitride coating layer 1004. In the embodiment shown in FIG. 10, each layer of the metal gate structure 1000 is shown as a simple film stack formed on the semiconductor substrate 1001. In fact, the metal gate structure 1000 may be formed in a contact well or other cavity formed in an insulating or dielectric material similar to the insulating material 120 in Figure 1. Therefore, one or more of the interface layer 1002, the high-k dielectric layer 1003, the metal nitride cover layer 1004, and the metal gate electrode layer 1005 may be material layers conformally deposited in the cavity.

The semiconductor substrate 1001 can be any suitable semiconductor substrate on which the metal gate structure 1000 can be formed. Therefore, the semiconductor substrate 1001 may be formed of any suitable semiconductor material, including but not limited to Si (Si), Ge (germanium), silicon germanium (Si-Ge), silicon germanium carbon (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), and all other group III/V or group II/VI compound semiconductors. Alternatively or additionally, the semiconductor substrate 1001 may be a layered semiconductor, for example, Si/Si-Ge, semiconductor on insulator (SOI), or Si-Ge on insulator (SiGOI). In addition, in some embodiments, the semiconductor substrate 1001 includes doped and/or undoped regions, such as n-doped or p-doped regions adjacent to the interface oxide layer 1002.

The interface oxide layer 1002 is provided on the semiconductor substrate 1001 between the semiconductor substrate 1001 and the high-k dielectric layer 1003, and is configured as an interface oxide layer suitable for application in the metal gate structure 1000. In the embodiment where the semiconductor substrate 1001 includes Si-containing material, the interface oxide 1002 layer may include silicon oxide (SiO _x ), silicon oxynitride (SiNO, Si ₂ NO, Si ₂ N ₂ O), and/or nitride Of silicon oxide. In an embodiment where the semiconductor 1001 is not a Si-containing semiconductor material, the interface oxide layer 1002 may include a semiconductor oxide, a semiconductor oxynitride, and/or a nitrided semiconductor oxide.

The interface oxide layer 1002 can be formed by any suitable thermal or wet growth technique (for example, oxidation or oxynitride). For example, and without limitation, the interface oxide layer 1002 can be formed by a wet chemical oxidation process, which includes treating the cleaned surface of the semiconductor substrate 1001 with a mixture of ammonium hydroxide, hydrogen peroxide, and water, as described above Semiconductor surface treated by HF. Alternatively, the interface oxide layer 1002 may be formed by treating the surface of the semiconductor that was treated with HF last time in an ozonized aqueous solution. Alternatively, the interface oxide layer 1002 can be formed by any suitable thermal oxidation technique.

The thickness of the interface oxide layer 1002 varies with the part of the semiconductor element of the metal gate structure 1000. In addition, the interface oxide layer 1002 is significantly thinner than the high-k dielectric layer 1003, the metal nitride coating layer 1004, and the metal gate electrode layer 1005. Generally, the interfacial oxide layer 1002 has a thickness from about 0.5 to 2.0 nm, although the interfacial oxide layer 1002 may be thicker in some embodiments. In some embodiments, the thermal process for device manufacturing that occurs after the metal gate structure 1000 is formed can further increase the thickness of the interface oxide layer 1002.

The high-k dielectric layer 1003 can be a gate dielectric layer or other dielectric layers in the metal gate structure 1000, and includes so-called "high-k dielectric" materials. More specifically, the high-permittivity dielectric layer 1003 includes one or more materials having _{a dielectric constant greater than SiO 2} , such as a material having a dielectric constant of at least about 4.0, or ideally at least about 10.0 . In addition, the high-permittivity dielectric material included in the high-permittivity dielectric layer 1003 is suitable for use in integrated circuits. Therefore, in addition to high permittivity, one or more high permittivity dielectric materials included in the high permittivity dielectric layer 1003 also ideally have the ability to prevent the diffusion of dopants and have less potential Electrical defects that damage breakdown performance, good thermal stability, and high recrystallization temperatures. Examples of such high-k dielectric materials suitable for use in the high-k dielectric layer 1003 include, but are not limited to, silicon nitride, silicon oxynitride, metal oxide, metal nitride, metal oxynitride, and / Or metal silicate. In some embodiments, the high-k dielectric layer 1003 includes one or more of the following: hafnium oxide (Hf _x O _y ), zirconium oxide (ZrO ₂ ), hafnium oxide silicate (Hf _x Si _1-x O _y ), or other hafnium-based dielectrics, lanthanum oxide (La ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), strontium titanate (SrTiO ₃ ), lanthanum aluminate ( LaAlO ₃ ), yttrium oxide (Y ₂ O ₃ ), hafnium oxide silicate (Hf _x Si _1-x O _y ), lanthanum oxide (La ₂ O ₃ ), and/or multiple layer stacks of each of the above.

The high-k dielectric layer 1003 can be formed by any suitable deposition method, including a thermal growth process, for example, an oxidation, nitridation, or oxynitride process. Alternatively, the high-k dielectric layer 1003 may be formed by one or more deposition processes, including but not limited to chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition) deposition; PECVD), metalorgano chemical vapor deposition (MOCVD), atomic layer deposition (ALD), evaporation, reactive sputtering, chemical solution deposition, and/or any combination thereof.

The thickness 1003A of the high-k dielectric layer 1003 may depend on the dielectric material included therein, the process used to form the high-k dielectric layer 1003, and the geometry and operation of the semiconductor device including the metal gate structure 1000 therein. And change. In some embodiments, the thickness 1003A of the high-k dielectric layer 1003 is from about 1.0 nm to about 20 nm.

The metal nitride coating layer 1004 is a metal layer disposed on the high-k dielectric layer 1003, and the metal layer is usually configured as a conductive protective layer on the high-k dielectric layer 1003. Therefore, in some embodiments, the metal nitride capping layer 1004 is configured to prevent undesired oxidation of the semiconductor substrate 1001 and/or the high-k dielectric layer 1003. In addition, in such an embodiment, the metal nitride capping layer 1004 can also be configured to allow oxygen to diffuse out of the high-k dielectric layer 1003 during the thermal annealing process that occurs after the metal nitride capping layer 1004 is deposited. In this embodiment, the metal nitride capping layer 1004 can also be configured to allow oxygen to diffuse out of the interface layer 1009 formed between the high-k dielectric layer 1003 and the metal nitride capping layer 1004 during the thermal annealing process. .

In some embodiments, the metal nitride capping layer 1004 includes metal nitrides, such as silicon nitride (TiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), and the like. Note that in some embodiments, depositing a nitride capping layer 1004 on the high-k dielectric layer 1003 may result in the formation of an interface layer 1009, which is between the high-k dielectric layer 1003 and the metal nitride capping layer. Set at the interface between 1004. According to some embodiments, when the continuous plasma hydrogenation and nitridation process as described herein is applied to the exposed surface of the metal nitride capping layer 1004, the interface layer 1009 is subsequently eliminated or reduced in thickness.

The metal nitride coating layer 1004 can be formed by any suitable deposition method, including but not limited to PVD process, CVD process, PECVD process, MOCVD process, ALD evaporation process, reactive sputtering, chemical solution deposition, and/or any combination thereof.

In some embodiments, the metal nitride capping layer 1004 is significantly thinner than the high-k dielectric layer 1003 and the metal gate electrode layer 1005. For example, in the embodiment of the metal gate structure 1000, the high-permittivity dielectric layer 1003 has a HfO ₂ layer with a thickness of 1003A from about 20 nm to about 40 nm, and the metal gate electrode layer 1005 has a thickness of about 20 nm to about 40 nm. For a TiN layer with a thickness of about 40 nm, the metal nitride capping layer 1004 may have a thickness 1004A of about 5 nm to about 15 nm.

In some embodiments, the thickness 1004A of the metal nitride capping layer 1004 is selected to facilitate the diffusion of oxygen atoms from the high-k dielectric layer 1003 and/or the interface layer 1009. Specifically, in such an embodiment, the thickness 1004A is selected so that O atoms diffuse from the high-k dielectric layer 1003 and/or the interface layer 1009 during the thermal annealing process that occurs after the metal nitride capping layer 1004 is deposited. In this embodiment, the thickness 1004A is selected to be smaller than the diffusion length of O atoms through the metal nitride coating layer 1004 during the thermal annealing process. In one example, one such thermal annealing process is performed on the metal gate structure 1000 with a duration of 1-2 seconds and a tip annealing process with a peak temperature of about 700 to about 900°C.

The metal gate electrode layer 1005 is a metal layer formed on the metal nitride cover layer 1004, and includes one or more deposited metal layers. In some embodiments, the metal gate electrode layer 1005 is configured as the gate electrode and/or work function metal of the metal gate structure 1000. In such an embodiment, the one or more metal layers included in the metal gate electrode layer 1005 are selected to have a common gate electrode work function value that promotes the metal gate structure 1000 and the metal included therein. Operation of the semiconductor element of the gate structure 1000. The metal gate electrode 1005 can be formed by any suitable deposition method, including but not limited to CVD, PECVD, MOCVD, ALD, evaporation, reactive sputtering, chemical solution deposition, and/or any combination thereof.

In some embodiments, the metal gate electrode layer 1005 is a p-metal gate material, such as TiN. Alternatively, in some embodiments, the metal gate electrode layer 1005 is an n-metal gate. The N metal suitable for use in the metal gate electrode layer 1005 includes titanium aluminum carbide (Ti _x AlC). Form a metal gate structure with reduced EOT

According to various embodiments, during the manufacturing of the metal gate structure 1000, before the metal gate electrode layer 1005 is deposited, a continuous plasma hydrogenation and nitridation process is performed on the metal nitride cover layer 1004. In such an embodiment, the EOT of the metal gate structure 1000 is reduced, and the leakage current of the metal gate structure 1000 is increased below the desired value. In addition, in such an embodiment, the metal gate structure 1000 exhibits little or no flat-band voltage offset normally associated with reduced EOT.

For example, in one embodiment of the metal gate structure 1000, the interface oxide layer 1002 has a thickness of about 1-2 nm, the high-permittivity dielectric layer 1003 has a thickness of 1003A of about 2-3 nm, and the metal nitride covers The layer 1004 has a thickness 1004A of about 3-4 nm. In this embodiment, a measurable effect of treating the metal nitride coating layer 1004 with the continuous plasma hydrogenation and nitriding process described herein is that the measurable EOT of the metal gate structure 1000 is reduced by about 1 Å (that is, , Dropped from about 9 Å to about 8 Å). Another effect of this treatment of the metal nitride coating layer 1004 is that the leakage current (at a flat band voltage of -1 V) increases by about 2.4 times (that is, from about 0.268 A/cm ² to about .658 A/cm ² ). In contrast, according to established scaling trends known in the art, when the EOT of the metal gate structure 1000 is instead reduced by conventional techniques (for example, by reducing the thickness of 1003A by approximately 1 Å) When the leakage current is expected to increase by a factor of about 10. Therefore, it has been found that the treatment of the metal nitride capping layer 1004 with the continuous plasma hydrogenation and nitriding process described herein has approximately the same value as the increased leakage current associated with only scaling down the thickness 1004A of the metal nitride capping layer 1004. A quarter to reduce the influence of the EOT of the metal gate structure 1000.

In addition, in addition to the reduction in EOT described above, it has been illustrated that when the metal gate structure 1000 is formed using a continuous plasma hydrogenation and nitridation process, the flat-band voltage offset measured in the metal gate structure 1000 maintains substantially Stablize. Therefore, the continuous plasma hydrogenation and nitridation process is applied to the metal nitride cover layer 1004 to realize the manufacture of the metal gate structure 1000 with reduced EOT without flat-band voltage offset and without affecting the device design.

FIG. 11 illustrates a flowchart of processing steps for reducing EOT in a metal gate structure according to various embodiments of the present disclosure. FIGS. 12A to 12J are schematic cross-sectional views of semiconductor devices at different stages of the manufacturing process corresponding to FIG. 11 according to various embodiments of the present disclosure.

The method 1100 starts at step 1101, as shown in FIG. 12A, where a high-k dielectric layer 1003 is deposited on the interface oxide layer 1002. The high-k dielectric layer 1003 can be formed by any suitable deposition method described above in conjunction with FIG. 10.

In step 1102, as shown in FIG. 12B, a metal nitride capping layer 1004 is deposited on the high-k dielectric layer 1003. The metal nitride capping layer 1004 can be formed by any suitable deposition method described above in conjunction with FIG. 10. In some embodiments, depositing the metal nitride capping layer 1004 results in the formation of an interface layer 1009 that is disposed at the interface between the high-k dielectric layer 1003 and the metal nitride capping layer 1004. In such an embodiment, the interface layer 1009 generally includes vacancies (which may be similar to the vacancies 213 in FIG. 2A) and/or O atoms brought in by pollution existing in the processing environment during the deposition process of step 1102.

In optional step 1103, the exposed surface 1201 shown in Figure 12B is exposed to air. For example, in some embodiments, the metal nitride capping layer 1004 is deposited in a processing system, such as the multi-chamber processing system 500 in Figure 5, and the next processing step to be performed on the semiconductor substrate 1001 is in a different Executed in the processing system. Therefore, in such an embodiment, after the metal nitride layer 1004 is deposited, the semiconductor substrate 1001 is exposed to the air. In an embodiment, where the metal nitride coating layer 1004 is deposited in one chamber of the multi-chamber processing system, and step 1104 is performed in one or two other processing chambers of the same multi-chamber processing system, it is not performed Optional step 1103.

In an embodiment, where the metal nitride capping layer 1004 deposited in step 1102 is a sacrificial metal nitride layer that is subsequently removed, the method 1100 proceeds to step 1131. In an embodiment, where the metal nitride capping layer 1004 deposited in step 1102 remains in the metal gate structure 1000, the method 1100 proceeds to step 1104. In some embodiments, the sacrificial metal nitride layer can be removed by using a subsequent wet or dry etching process, which is selective for the removal of the metal nitride capping layer 1004.

In step 1104, as shown in FIG. 12C, a continuous plasma hydrogenation and nitridation process is performed on the surface 1201 of the metal nitride coating layer 1004. The plasma hydrogenation and nitridation process can be substantially similar to the plasma hydrogenation and nitridation process described in connection with FIG. 4 above. In addition, the plasma hydrogenation process includes non-oxidized plasma excited hydrogen species, and does not include any oxidized plasma excited hydrogen species.

In some embodiments, at a chamber pressure between about 20 mTorr and about 100 mTorr, at a processing temperature between about 400° C. and about 500° C. (such as substrate base temperature), where the RF power is at about 500 W And about 1500 W, _{the flow rate of H 2} is between about 20 sccm and about 100 sccm, and the flow rate of Ar is between about 900 sccm and about 980 sccm, and the plasma hydrogenation process of step 1104 is performed up to about 30 sccm. Duration between about 150 seconds and about 150 seconds. In some embodiments, _{the flow rate of H 2} is between about 1% and about 15% of the total process gas introduced into the chamber. In some embodiments, at a chamber pressure between about 45 mTorr and about 55 mTorr, at a processing temperature between about 425° C. and about 475° C., where the RF power is between about 700 W and about 800 W , _{The flow rate of H 2} is between about 45 sccm and about 55 sccm, and the flow rate of Ar is between about 965 sccm and about 955 sccm, and the plasma hydrogenation process of step 1104 is performed between about 85 seconds and about 95 seconds. The duration of the time.

In some embodiments, at a chamber pressure between about 10 mTorr and about 50 mTorr, at a processing temperature between about 400° C. and about 500° C., where the RF power is between about 500 W and about 1500 W, NH _{The flow rate of 3} is between about 1% and about 10% _{of the total process gas flow rate, the flow rate of N 2} is between about 45% and about 55% of the total process gas flow rate, and the flow rate of Ar is selected To be equal to the remaining part of the processing gas flow rate, the plasma nitriding process of step 1104 is performed for a duration between about 30 seconds and about 150 seconds. In some embodiments, at a chamber pressure between about 15mTorr and about 25mTorr, at a processing temperature between about 425°C and about 475°C, where the RF power is between about 700W and about 800W, the NH ₃ The flow rate is between about 2% and about 3% _{of the total process gas flow rate, the flow rate of N 2} is between about 45% and about 55% of the total process gas flow rate, and the flow rate of Ar is selected to be equal to For the remaining part of the processing gas flow, the plasma nitriding process of step 1104 is performed for a duration between about 85 seconds and about 95 seconds.

In summary, in step 1104, the surface 1201 is exposed to the hydrogen species excited by the plasma generated in the plasma hydrogenation process, and some or all oxides present on the surface 1201 are reduced. In addition, in some embodiments, the hydrogen species excited by the plasma can also reduce some or all of the oxygen (O) atoms present in the host material of the metal nitride coating layer 1004. In addition, in step 1104, the surface 1201 is exposed to nitrogen species excited by the plasma generated in the plasma nitriding process, thereby making the surface 1201 saturated with N atoms, and in some embodiments, the surface 1201 is filled with N atoms The metal nitride coating layer 1004 covers the vacancies in the host material. Therefore, in some embodiments, as shown in FIG. 12D, the interface layer 1009 is eliminated or significantly reduced.

In some embodiments, the plasma hydrogenation process in step 1104 is performed in the same processing chamber as the plasma nitridation process in step 1104, for example, in the processing chamber 400 in FIG. 4. Alternatively, the plasma hydrogenation process of step 1104 is performed in the first processing chamber of a multi-chamber processing system, and the plasma nitriding process of step 1104 is performed in the second processing chamber of the same multi-chamber processing system. In either case, it is noted that the surface 1201 is not exposed to air between the plasma hydrogenation process and the plasma nitridation process of step 1104. Therefore, in either embodiment, the surface 1201 is not exposed to air after exposure to plasma excited hydrogen species and before exposure to plasma excited nitrogen species.

In some embodiments, before the plasma hydrogenation process is performed in the process chamber, the oxygen-free conditioning process is performed in the process chamber, for example, to reduce trace oxygen pollution in the process chamber. In this embodiment, the processing chamber is treated with oxygen-free plasma without placing the substrate therein and before processing the substrate through the plasma hydrogenation process described above. This type of plasma processing in the processing chamber before the substrate is introduced into the chamber is sometimes referred to as a plasma every wafer (PEW) process or PEW processing.

In some embodiments, this PEW process includes introducing one or more non-oxygen-containing gases (such as N ₂ , NH ₃ , Ar, H ₂ , or any suitable combination thereof) into the processing chamber, and energizing one or More kinds of gases to form oxygen-free plasma. Alternatively, the PEW process may include introducing plasma free radicals and/or N, H, or NH ₃ ions or any suitable combination thereof into the processing chamber, wherein the plasma is in a remote plasma source outside the processing chamber form. In one embodiment, NH ₃ gas or _{a combination of NH 3} and Ar gas is introduced into the processing chamber. In another embodiment, H ₂ gas or _{a combination of H 2} and Ar gas is introduced into the processing chamber. In yet another embodiment, N ₂ gas or _{a combination of N 2} and Ar gas is introduced into the processing chamber.

Generally, plasma processing in a processing chamber prior to introduction of the substrate involves introducing or forming hydrogen and/or nitrogen-containing plasma in the processing chamber. In some embodiments, free radicals (such as N*, NH*, and/or H*) generated by the plasma inside the processing chamber during the PEW process react with trace O atoms in the processing chamber.

In some embodiments, during the PEW process, one or more gases introduced into the processing chamber are excited by an RF power source, such as the RF power source 414 in FIG. 4. The RF power can be pulsed at a duty cycle of 2% to 70%, and can vary from about 100 W to about 2500 W. The RF power can be a continuous wave varying from about 100 W to about 2500 W. In such an embodiment, at a chamber pressure of about 10 mTorr to about 200 mTorr, at a processing temperature between about 400°C and about 500°C, where the RF power is between about 250 W and about 750 W, The flow rate of H ₂ is between about 50 sccm and about 200 sccm, and _{the flow rate of O 2} is between about 450 sccm and about 550 sccm, and the PEW process of step 1104 is performed for between about 20 seconds and about 100 seconds. duration.

In an optional step 1105, the exposed surface 1201 is exposed to air. For example, in some embodiments, the continuous hydrogenation and nitridation processes described above are performed in one processing system, and the next processing step to be performed on the semiconductor substrate 1001 is performed in a different processing system. Therefore, in such an embodiment, after the metal nitride layer 1004 is deposited, the semiconductor substrate 1001 is exposed to the air. In the embodiment, the continuous hydrogenation and nitridation process is performed in one chamber of the multi-chamber processing system, and step 1106 is performed in another processing chamber of the same multi-chamber processing system, and optional steps are not performed 1105.

In an embodiment, where the sacrificial silicon-containing layer is subsequently deposited and removed as part of forming the metal gate structure 1000, the method 1100 proceeds from step 1105 to step 1121. In an embodiment, where a sacrificial silicon layer is not deposited when forming the metal gate structure 1000, the method 1100 proceeds to step 1106. The sacrificial silicon-containing layer can be formed by using a CVD or ALD process that uses one or more silicon-containing precursor gases to form the deposited layer.

In step 1106, a thermal annealing process (such as annealing after covering) is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, and the metal nitride coating layer 1004. For example, in some embodiments, the tip annealing process is performed in step 1106, where a peak temperature of about 600 to 900°C is reached. The post-covering annealing is performed on the partially formed metal gate structure 1000 to smooth the interface, repair the unsaturated bonds, and inject heat energy into the metal nitride cover layer.

In step 1107, as shown in FIG. 12E, a metal gate electrode layer 1005 is deposited on the processed metal nitride coating layer 1004, thereby completing the formation of the metal gate structure 1000. The metal gate electrode 1005 can be formed by any suitable deposition method described above in conjunction with FIG. 10.

In step 1121, as shown in FIG. 12F, a sacrificial silicon layer 1202 is deposited on the metal nitride capping layer 1004. Step 1121 is performed after the continuous plasma hydrogenation and nitridation process of step 1104 and the optional air exposure treatment of step 1105 on the surface 1201 of the metal nitride coating layer 1004.

The sacrificial silicon layer 1202 may include any suitable silicon-containing material, such as amorphous silicon, and may be deposited using any suitable deposition process known in the art, such as a CVD process. The sacrificial silicon layer 1202 is deposited on the metal nitride cover layer 1004 to reduce the metal nitride cover layer 1004, the interface layer 1009 (if still present), and the high dielectric material during the subsequent thermal annealing process (such as the so-called post-cover annealing process). The formation of oxide in the dielectric constant layer 1003. In some embodiments, the post-cover annealing process includes an atmospheric thermal annealing process. Subsequently, further oxidation of the very thin layer of the metal gate structure 1000 may occur, including the interface layer 1002, the high-k dielectric layer 1003, and the metal nitride cover layer 1004, thereby increasing the EOT of the metal gate structure 1000. However, there is a sacrificial silicon layer 1202 that can shield the metal gate structure 1000 from atmospheric O atoms during the pre-covering annealing process. In addition, the sacrificial silicon layer 1202 can react with O atoms and thereby retain O atoms, which diffuse into the high-k dielectric layer 1003, interface layer 1009 (if still present), and metal nitrogen during the thermal annealing process.化物盖层1004。 Compound covering layer 1004. Therefore, the sacrificial silicon layer 1202 minimizes or eliminates the possibility of undesirably oxidizing portions of the metal gate structure 1000 during the subsequent thermal annealing process.

In step 1122, a thermal annealing process (such as post-covering annealing) is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, the metal nitride cover layer 1004, and the sacrificial silicon layer 1202. The thermal annealing process of step 1122 may be substantially similar to the thermal annealing process of step 1106 described above.

In step 1123, the sacrificial silicon layer 1202 is removed from the metal gate structure 1000. Any technically feasible removal process can be used in step 1123, including a selective wet etching process, a plasma-based dry etching process, a chemical mechanical polishing process, or any combination thereof. The method 1100 then proceeds to step 1107, where the final layer of the metal gate structure 1000 is deposited.

In step 1131, as shown in FIG. 12G, a sacrificial silicon layer 1203 is deposited on the metal nitride capping layer 1004. The sacrificial silicon layer 1203 may be substantially similar to the sacrificial silicon layer 1202 deposited in step 1131. However, note that in step 1131, the metal nitride coating layer 1004 has not been processed by a continuous plasma hydrogenation and nitridation process. Subsequently, the metal nitride cover layer 1004 may still include the interface layer 1009 as shown in the figure.

In step 1132, a thermal annealing process (such as post-covering annealing) is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, the metal nitride cover layer 1004, the interface layer 1009, and the sacrificial silicon layer 1203 . The thermal annealing process of step 1132 may be substantially similar to the thermal annealing process of step 1106 described above.

In step 1133, as shown in FIG. 12H, the sacrificial silicon layer 1203, the metal nitride cover layer 1004, and the interface layer 1009 are removed from the metal gate structure 1000. Any technically feasible removal process or process combination can be used in step 1123, including a selective wet etching process, a plasma-based dry etching process, a chemical mechanical polishing process, or any combination thereof. The method 1100 then proceeds to step 1134.

In step 1134, as shown in FIG. 12I, a metal nitride capping layer 1204 is finally deposited on the high-k dielectric layer 1003. The final metal nitride capping layer 1204 may be substantially similar to the metal nitride capping layer 1004, and may include an interface layer 1009.

In optional step 1135, the exposed surface 1205 shown in Figure 12I is exposed to air. For example, in some embodiments, the final metal nitride capping layer 1204 is deposited in one processing system, and the next processing step to be performed on the semiconductor substrate 1001 (ie, step 1136) is performed in a different processing system. Therefore, in such an embodiment, the semiconductor substrate 1001 is exposed to air after the final metal nitride layer 1204 is deposited. In an embodiment, where the final metal nitride coating layer 1204 is performed in one chamber of the multi-chamber processing system, and step 1136 is performed in one or two other processing chambers of the same multi-chamber processing system, no Perform optional step 1135.

In step 1136, as shown in FIG. 12J, a continuous plasma hydrogenation and nitridation process is performed on the surface 1205 of the final metal nitride coating layer 1204. The continuous plasma hydrogenation and nitridation process performed in step 1136 may be substantially similar to the process used in step 1104. Subsequently, the interface layer 1009 can be eliminated or reduced during step 1136, thereby removing the O atoms present in the final metal nitride capping layer 1204, the interface layer 1009, and in some embodiments the high-k dielectric layer 1003. Therefore, without scaling down the thickness 1003A of the high-k dielectric layer 1003, the EOT of the metal gate structure 1000 is reduced.

After performing the continuous plasma hydrogenation and nitridation process in step 1136, the method 1100 proceeds to step 1107, where the final layer of the metal gate structure 1000 is deposited. In an embodiment, where steps 1136 and 1107 are executed in different processing systems, the semiconductor substrate 1001 must be exposed to air. However, because the plasma nitriding process of step 1136 can completely or almost completely nitrate the exposed surface 1205 of the final metal nitride cover layer 1204, its oxidation usually rarely or does not occur during this air exposure. Single step nitridation - hydrogenation treatment

The method 1300 starts at step 1301, as shown in FIG. 14A, where a high-k dielectric layer 1003 is deposited on the interface oxide layer 1002. The interface oxide layer 1002 can be deposited by any suitable method, such as chemical oxidation of the underlying semiconductor substrate 1001, thermal oxidation of the underlying substrate, atomic layer deposition (ALD), chemical vapor deposition (CVD), or Similar. The high-k dielectric layer 1003 can be formed by any suitable deposition method described above in conjunction with FIG. 10. The high-k dielectric layer 1003 may include any high-k material that can be oxidized. According to one embodiment, the high-k dielectric layer 1003 includes _{silicon dioxide (SiO 2} ) or hafnium oxide (HfO ₂ ).

In step 1302, as shown in FIG. 14B, a capping layer 1404 is deposited on the high-k dielectric layer 1003. The capping layer 1404 can be formed by any suitable deposition method described above in conjunction with FIG. 10. The capping layer 1404 may include metal nitride. According to one embodiment, the capping layer may include a metal nitride, such as titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TAN), or titanium silicon nitride (TiSiN). In some embodiments, the deposition of the capping layer 1404 results in the formation of an interface layer 1409 that is disposed at the interface between the high-k dielectric layer 1003 and the capping layer 1404. In such an embodiment, the interface layer 1409 usually includes defects, such as vacancies (which may be similar to the vacancies 213 in Figure 2A) and/or O caused by pollution present in the processing environment during the deposition process of step 1302. atom. Due to the hopping of electrons between defects, defects can allow undesirable charge transfer. The charge transfer may cause current leakage or dielectric breakdown, thereby reducing the electrical reliability of the metal gate structure 1000.

In optional step 1303, the exposed surface 1401 shown in Figure 14B is exposed to air. For example, in some embodiments, the cover layer 1404 is deposited in one processing system, such as the multi-chamber processing system 500 in Figure 5, and the next processing step to be performed on the semiconductor substrate 1001 is performed in a different processing system . Therefore, in such an embodiment, after depositing the capping layer 1404, the semiconductor substrate 1001 is exposed to the air. In an embodiment, where the cover layer 1404 is deposited in one chamber of the multi-chamber processing system, and step 1304 is performed in one or two other processing chambers of the same multi-chamber processing system, no optional steps are performed 1303.

In an embodiment, where the capping layer 1404 deposited in step 1302 is a sacrificial layer that is subsequently removed, the method 1400 proceeds to step 1331. In an embodiment, where the capping layer 1404 deposited in step 1302 remains in the metal gate structure 1000, the method 1300 proceeds to step 1304. In some embodiments, the sacrificial layer can be removed by using a subsequent wet or dry etching process, which is selective to the removal of the cover layer 1404.

In step 1304, as shown in FIG. 14C, a single-step plasma hydrogenation and nitridation process is performed on the surface 1401 of the cover layer 1404. The single-step plasma hydrogenation and nitridation process includes exposing a workpiece (such as the metal gate structure 1000) to a processing plasma, where the processing plasma includes a nitrogen-containing gas and a hydrogen-containing gas. In some embodiments, the hydrogen-containing gas substantially includes both nitrogen-containing and hydrogen-containing gas, such as ammonia (NH ₃ ), hydrazine (N ₂ H ₄ ), or hydrogen azide (HN ₃ ). In one example, the hydrogen-containing gas includes ammonia (NH ₃ ), and the nitrogen-containing gas includes (N ₂ ). According to an embodiment, the processing plasma may include a single gas containing hydrogen and nitrogen, such as hydrazine (N ₂ H ₄ ) or ammonia (NH ₃ ). According to one embodiment, the processing plasma may include an additional neutral carrier gas, such as argon (Ar) or helium (He). In one example, the processing gas contained in the processing plasma substantially includes ammonia (NH ₃ ), nitrogen (N ₂ ), and a neutral carrier gas, such as argon (Ar) or helium (He). In addition, during the single-step plasma hydrogenation and nitridation process of step 1304, a bias voltage can be applied to the substrate by the bias power supply 426. Similar to the RF power supply 414, the bias power supply 426 is generally capable of generating an RF signal having a tunable frequency varying from about 2 MHz to about 160 MHz and a power between about 0 kW and about 10 kW. The bias power improves the conformality of the grown film by rearranging the deposited atoms.

In some embodiments, at a chamber pressure between about 10 mTorr and about 100 mTorr, at a processing temperature (such as substrate base temperature) between about 350° C. and about 500° C., where the RF power is about 300 W And about 2000 W, _{the flow rate of NH 3} is between about 5 sccm and about 100 sccm, _{the flow rate of N 2} is between about 50 sccm and about 1000 sccm, and the flow rate of helium (He) is between about 1 to about Between 1000 sccm, the single-step plasma hydrogenation and nitridation process of step 1304 is performed for a duration between about 30 seconds and about 150 seconds, and the application has a frequency from about 2 MHz to about 160 MHz, and at about 0 Substrate bias with a bias power between kW and about 10 kW.

In some embodiments, at a chamber pressure between about 15 mTorr and about 25 mTorr, at a processing temperature between about 425° C. and about 475° C., where the RF power is between about 900 W and about 1100 W , _{The flow rate of NH 3} is between about 15 sccm and about 35 sccm, _{the flow rate of N 2} is between about 450 sccm and about 550 sccm, and the flow rate of Ar is between about 450 sccm and about 500 sccm. Perform step 1304 The single-step plasma hydrogenation and nitridation process has a duration between about 85 seconds and about 95 seconds, and no substrate bias power is applied.

In summary, in step 1304, the surface 1401 is exposed to hydrogen and nitrogen species excited by the plasma generated in the plasma process, and some or all oxides present on the surface 1401 are converted into nitrides. Therefore, as shown in FIG. 14D, in some embodiments, the thickening of the interface layer 1409 is eliminated or substantially reduced. The interface layer 1409 remains, but no layer thickening occurs. The reduction or nitridation of the interface layer 1409 reduces the EOT and changes the work function of the metal gate structure 1000.

In some embodiments, before performing the single-step plasma hydrogenation and nitridation process of step 1304, the oxygen-free conditioning process is performed in the processing chamber, for example, to reduce trace oxygen pollution in the processing chamber. In this embodiment, the processing chamber is treated with oxygen-free plasma without placing the substrate therein and before processing the substrate through the single-step plasma hydrogenation and nitridation process described above.

In an optional step 1305, the exposed surface 1401 is exposed to air. For example, in some embodiments, the single-step plasma hydrogenation and nitridation process of step 1304 above is performed in one processing system, and the next processing step to be performed on the semiconductor substrate 1001 is performed in a different processing system. Therefore, in such an embodiment, after the layer 1404 is deposited, the semiconductor substrate 1001 is exposed to the air. In an embodiment, the single-step plasma hydrogenation and nitridation process of step 1304 is performed in one chamber of a multi-chamber processing system, and step 1306 is performed in another processing chamber of the same multi-chamber processing system , Optional step 1305 is not performed.

In an embodiment, where the sacrificial silicon-containing layer is subsequently deposited and removed as part of forming the metal gate structure 1000, the method 1300 proceeds from step 1305 to step 1321. In an embodiment, where a sacrificial silicon layer is not deposited when forming the metal gate structure 1000, the method 1300 proceeds to step 1306. The sacrificial silicon-containing layer can be formed by using a CVD or ALD process that uses one or more silicon-containing precursor gases to form the deposited layer.

In step 1306, a thermal annealing process (such as post-covering annealing) is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, and the cover layer 1404. For example, in some embodiments, the tip annealing process is performed in step 1306, where a peak temperature of about 600°C to about 900°C is reached. Post-covering annealing is performed on the partially formed metal gate structure 1000 to smooth the interface, repair unsaturated bonds, and inject thermal energy into the cover layer 1404.

In step 1307, as shown in FIG. 14E, a metal gate electrode layer 1005 is deposited on the processed cover layer 1404, thereby completing the formation of the metal gate structure 1000. The metal gate electrode 1005 can be formed by any suitable deposition method described above in conjunction with FIG. 10.

In step 1321, as shown in FIG. 14F, a sacrificial silicon layer 1202 is deposited on the capping layer 1404. Step 1321 is performed after the surface 1401 of the cover layer 1404 is processed by the single-step plasma hydrogenation and nitridation process of step 1304 and the optional air exposure of step 1305.

In step 1322, a thermal annealing process (such as post-covering annealing) is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, the cover layer 1404, and the sacrificial silicon layer 1202. The thermal annealing process of step 1322 may be substantially similar to the thermal annealing process of step 1306 described above.

In step 1323, the sacrificial silicon layer 1202 is removed from the metal gate structure 1000. Any technically feasible removal process can be used in step 1323, including a selective wet etching process, a plasma-based dry etching process, a chemical mechanical polishing process, or any combination thereof. The method 1300 then proceeds to step 1307, where the final layer of the metal gate structure 1000 is deposited.

In step 1331, as shown in FIG. 14G, a sacrificial silicon layer 1203 is deposited on the capping layer 1404. The sacrificial silicon layer 1203 may be substantially similar to the sacrificial silicon layer 1202 deposited in step 1331. However, note that in step 1331, the cover layer 1404 has not been processed by a single-step plasma hydrogenation and nitridation process. Subsequently, the cover layer 1404 may still include the interface layer 1409 as shown in the figure.

In step 1332, a thermal annealing process (such as post-covering annealing) is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, the cover layer 1404, the interface layer 1409, and the sacrificial silicon layer 1203. The thermal annealing process of step 1332 may be substantially similar to the thermal annealing process of step 1306 described above.

In step 1333, as shown in FIG. 14H, the sacrificial silicon layer 1203, the capping layer 1404, and the interface layer 1409 are removed from the metal gate structure 1000. Any technically feasible removal process or process combination can be used in step 1333, including a selective wet etching process, a plasma-based dry etching process, a chemical mechanical polishing process, or any combination thereof. The method 1300 then proceeds to step 1334.

In step 1334, as shown in FIG. 14I, the final capping layer 1404f is deposited on the high-k dielectric layer 1003. The final cover layer 1404f may be composed of the same material as the cover layer 1404, and the final cover layer may also include the interface layer 1409.

In optional step 1335, the exposed surface 1405 shown in Figure 14I is exposed to air. For example, in some embodiments, the final cover layer 1404f is deposited in one processing system, and the next processing step to be performed on the semiconductor substrate 1001 (ie, step 1336) is performed in a different processing system. Therefore, in such an embodiment, after depositing the final capping layer 1404f, the semiconductor substrate 1001 is exposed to air. In an embodiment, where the final cover layer 1404f is deposited in one chamber of the multi-chamber processing system, and step 1336 is performed in one or two other processing chambers of the same multi-chamber processing system, the optional Step 1335.

In step 1336, as shown in FIG. 14J, a single-step plasma hydrogenation and nitridation process is performed on the surface 1405 of the final cover layer 1404. The single-step plasma hydrogenation and nitridation process performed in step 1336 may be substantially similar to the process used in step 1304. Subsequently, the thickening of the interface layer 1409 can be eliminated or reduced during step 1336, thereby removing the O atoms present in the final capping layer 1404f, the interface layer 1009, and in some embodiments the high-k dielectric layer 1003. Therefore, without scaling down the thickness 1003A of the high-k dielectric layer 1003, the EOT of the metal gate structure 1000 is reduced.

After performing the single-step plasma hydrogenation and nitridation process in step 1336, the method 1300 proceeds to step 1307, where the final layer of the metal gate structure 1000 is deposited. In an embodiment, where steps 1336 and 1307 are executed in different processing systems, the semiconductor substrate 1001 must be exposed to air. However, because the plasma nitriding process of step 1336 can completely or almost completely nitridize the exposed surface 1405 of the final cover layer 1404f, its oxidation usually rarely occurs or does not occur during this air exposure.

In the embodiments disclosed herein, a continuous hydrogenation and nitridation process or a single-step hydrogenation and nitridation process is used to enable the formation of a metal gate structure having a reduced EOT compared to similar structures formed by conventional methods. The plasma hydrogenation process and the subsequent plasma nitridation process are performed in the metal nitride layer in the film stack, thereby in some embodiments, the O atoms disposed in the film stack are removed, and in some embodiments, the O atoms are reduced. Small or prevent the oxygen-containing interfacial layer provided in the film stack from thickening, and in some embodiments, N atoms are added to the film stack layer. Therefore, the EOT of the metal gate structure is reduced with little or no accompanying flat-band voltage shift. In addition, the metal gate structure operates with an increased leakage current that is as low as a quarter of the increase in leakage current associated with similar metal gate structures formed via conventional techniques.

Although the above content relates to the embodiments of the present disclosure, other and further embodiments of the present disclosure can be designed without departing from its basic scope, and its scope is determined by the scope of the following patent applications.

100: conductive structure/contact structure

101: source or drain structure

102: The first metal layer

103: Metal nitride layer

104: Overlay

105: Silicide

106: conductive layer 109: contact trap 110: Semiconductor substrate 120: insulating material 200: part 201: Surface 211: Subject O atom 212: surface O atom 213: Vacancy 310: XPS spectrum 320: XPS spectrum 400: Plasma processing chamber 404: substrate support base 406: Chamber Wall 408: chamber cover 410: induction coil element 412: The first impedance matching network 414: RF power supply 416: Electrical grounding 417: electrical grounding 418: Shield electrode 419: Electrical grounding 420: switch 422: Detector 424: second impedance matching network 426: Bias power supply 428: Substrate 430: Gas Panel 432: Entrance Port 434: Gas mixture 436: Plasma 438: Throttle Valve 440: Vacuum pump 442: Gas Source 444: Gas Pipeline 446: Controller 448: central processing unit (CPU) 450: memory 452: Support Circuit 500: Multi-chamber processing system 506: Passing Chamber 508: Buffer Chamber 510: Single wafer loading gate 512: Single wafer load gate 513: heating element 514: processing chamber 516: Processing Chamber 518: Processing Chamber 520: processing chamber 522: Processing Chamber 523: preheating chamber 524: Processing Chamber 525: preheating chamber 526: Robot 528: Robot 530: computer system 600: method 601: Step 603: step 604: step 605: step 701: Surface 703: Nitrogen Species Excited by Plasma 800: method 801: Step 802: step 803: step 804: step 805: step 900: method 901: step 902: step 903: step 905: step 1000: Metal gate structure 1001: Semiconductor substrate 1002: Interface layer 1003: High dielectric constant dielectric layer 1003A: Thickness 1004A: Thickness 1004: Metal nitride coating 1005: Metal gate electrode layer 1009: Interface layer 1100: Method 1101: Step 1102: step 1103: Step 1104: step 1105: Step 1106: step 1107: step 1121: step 1122: step 1123: Step 1131: step 1132: step 1133: step 1134: step 1135: step 1136: step 1201: exposed surface 1202: Sacrificial silicon layer 1203: Sacrificial silicon layer 1205: exposed surface 1300: method 1301: Step 1302: Step 1303: step 1304: step 1305: step 1306: step 1307: step 1321: step 1322: step 1323: step 1331: step 1332: step 1333: step 1334: step 1335: step 1336: step 1401: Surface 1404: Overlay 1404f: final overlay 1409: Interface layer

In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are used, a more specific description of the present disclosure briefly outlined above can be made with reference to the embodiments, some of which are shown in the accompanying drawings. However, it will be noted that the drawings only show common embodiments of the present disclosure, and thus are not considered to limit its scope, because the present disclosure may allow other equally effective embodiments.

FIG. 1 shows a cross-sectional view of a contact structure formed on a substrate as a part of a semiconductor element according to an embodiment of the present disclosure.

2A to 2E are schematic diagrams of the metal nitride layer in the contact structure of FIG. 1 at various stages of manufacturing the contact structure according to an embodiment of the present disclosure.

FIG. 3 is an X-ray Photoelectron Spectroscopy (X-ray Photoelectron Spectroscopy; XPS) spectrum 310 of a TiN film deposited and thermally annealed before processing according to an embodiment of the present disclosure and the same after processing XPS spectrum 320 of the deposited and thermally annealed TiN film.

Figure 4 is a cross-sectional side view of a processing chamber configured to implement one or more aspects of the present disclosure.

Figure 5 is a top plan view of a multi-chamber processing system configured to implement one or more aspects of the present disclosure.

FIG. 6 illustrates a flowchart of processing steps for reducing the main body and interface oxygen in the contact structure according to some embodiments of the present disclosure.

FIGS. 7A to 7E are schematic cross-sectional views of semiconductor devices at different stages of the manufacturing process corresponding to FIG. 6 according to various embodiments of the present disclosure.

Figure 8 illustrates a flow chart of processing steps for reducing body and interface oxygen in the contact structure according to some embodiments of the present disclosure.

Figure 9 illustrates a flow chart of processing steps for reducing the body and interface oxygen in the contact structure according to some embodiments of the present disclosure.

FIG. 10 shows a cross-sectional view of a metal gate structure formed according to an embodiment of the present disclosure.

FIG. 11 illustrates a flowchart of processing steps for reducing the effective oxide thickness (EOT) in the metal gate structure according to various embodiments of the present disclosure.

FIGS. 12A to 12J are schematic cross-sectional views of semiconductor devices at different stages of the manufacturing process corresponding to FIG. 11 according to various embodiments of the present disclosure.

FIG. 13 illustrates a flow chart of the processing steps for treating the metal gate structure with a single-step hydrogenation and nitridation process according to various embodiments of the present disclosure.

FIGS. 14A to 14J are schematic cross-sectional views of semiconductor devices at different stages of the manufacturing process corresponding to FIG. 13 according to various embodiments of the present disclosure.

For ease of understanding, the same component symbols have been used to identify the same components in the drawings where possible. It is anticipated that the elements and features of one embodiment can be advantageously incorporated into other embodiments without further description.

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1000: Metal gate structure

1001: Semiconductor substrate

1002: Interface layer

1003: High dielectric constant dielectric layer

1401: Surface

1404: Overlay

1409: Interface layer

Claims (20)

A method of forming a structure in a semiconductor device, the method comprising the following steps: depositing a metal nitride coating layer on a high-k dielectric layer formed on a surface of a substrate; An exposed surface of the coating layer is exposed to a plasma containing a first gas and a second gas, the first gas contains a hydrogen-containing species, the second gas contains a nitrogen-containing species, and the first gas contains a nitrogen-containing species. The hydrogen-containing species in the gas contains nitrogen; after exposing the exposed surface to the plasma, depositing a silicon-containing layer on the exposed surface of the deposited metal nitride capping layer; on the silicon-containing layer Performing a thermal annealing process; and removing the silicon-containing layer. The method according to claim 1, wherein the metal nitride coating layer includes a metal selected from the group consisting of titanium, tantalum, and tungsten. The method of claim 1, wherein a substrate bias is applied to the substrate while exposing the exposed surface to the plasma. The method of claim 1, further comprising: forming an interface layer containing silicon dioxide on a surface of the substrate, wherein the high-permittivity dielectric layer is formed on the surface of the substrate. Formed on the interface layer of silicon oxide. The method according to claim 1, further comprising: depositing a sacrificial layer on the high-k dielectric layer; depositing a silicon-containing layer on the sacrificial layer; performing a sacrificial layer on the sacrificial layer and the silicon-containing layer Thermal annealing process; and removing the sacrificial layer and the silicon-containing layer before depositing the metal nitride covering layer on the high-k dielectric layer. The method according to claim 1, further comprising: before exposing the exposed surface to the plasma-excited hydrogen species and the plasma-excited nitrogen species, performing a process on at least one surface of a processing chamber. An oxygen plasma processing process, wherein the exposed surface is exposed to hydrogen species excited by the plasma when the substrate is not disposed in the processing chamber. The method of claim 1, wherein the metal nitride coating layer includes titanium and nitrogen, the hydrogen-containing species includes ammonia, and the nitrogen-containing species includes nitrogen (N ₂ ). The method of claim 1, wherein the hydrogen-containing species contains ammonia, and the nitrogen-containing species contains nitrogen (N ₂ ). The method according to claim 8, wherein the step of exposing an exposed surface further comprises: exposing the exposed surface to argon (Ar). A method of forming a structure in a semiconductor device, the method comprising the following steps: depositing a high-k dielectric layer on a semiconductor substrate; depositing a cover layer on the high-k dielectric layer; Exposing an exposed surface of the covering layer to a plasma-excited hydrogen species and a plasma-excited nitrogen species; exposing the exposed surface to air; on the high-k dielectric layer and the covering layer Performing a thermal annealing process at a specific temperature for a specific time; depositing a silicon-containing layer on the exposed surface; performing a thermal annealing process on the silicon-containing layer; and removing the silicon-containing layer. The method according to claim 10, wherein the cover layer includes nitrogen and a metal. The method according to claim 11, wherein the cover layer comprises titanium (Ti). The method according to claim 10, further comprising: before depositing the high-k dielectric layer, forming an interface layer containing silicon dioxide, and subsequently forming the high-k dielectric layer thereon. The method according to claim 10, further comprising: depositing a sacrificial layer on the high-k dielectric layer; depositing a silicon-containing layer on the sacrificial layer; performing a sacrificial layer on the sacrificial layer and the silicon-containing layer A third thermal annealing process; and removing the sacrificial layer and the silicon-containing layer. The method according to claim 10, further comprising: performing an oxygen-free plasma on a processing chamber before exposing the exposed surface to the hydrogen species excited by the plasma and the nitrogen species excited by the plasma A treatment process in which the exposed surface is exposed to hydrogen species excited by the plasma. The method of claim 10, wherein a substrate bias is applied to the semiconductor substrate while exposing the exposed surface to the plasma excited hydrogen species and the plasma excited nitrogen species. The method according to claim 10, wherein the hydrogen species excited by the plasma includes ammonia, and the nitrogen species excited by the plasma includes nitrogen (N ₂ ). A method of forming a structure in a semiconductor device, the method comprising the following steps: depositing a high-k dielectric layer on a semiconductor substrate; depositing a cover layer on the high-k dielectric layer to form the A part of the structure, where the part includes the capping layer and the high-k dielectric layer, and where the deposited capping layer has an exposed surface; exposing the exposed surface to a plasma excited hydrogen species and a Plasma-excited nitrogen species, wherein the plasma-excited hydrogen species includes ammonia, and the plasma-excited nitrogen species includes nitrogen (N ₂ ); depositing a silicon-containing layer on the exposed surface; on the silicon-containing layer Performing a thermal annealing process; and removing the silicon-containing layer. The method of claim 18, wherein the covering layer includes a metal selected from the group consisting of titanium, tantalum, and tungsten. The method according to claim 18, wherein a substrate is A bias voltage is applied to the semiconductor substrate while exposing the exposed surface.

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