KR102491574B1 - 반도체 패키지의 제조 방법 - Google Patents

반도체 패키지의 제조 방법 Download PDF

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KR102491574B1
KR102491574B1 KR1020160024709A KR20160024709A KR102491574B1 KR 102491574 B1 KR102491574 B1 KR 102491574B1 KR 1020160024709 A KR1020160024709 A KR 1020160024709A KR 20160024709 A KR20160024709 A KR 20160024709A KR 102491574 B1 KR102491574 B1 KR 102491574B1
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South Korea
Prior art keywords
group
flux
carbon nanotubes
layer
connection pad
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KR1020160024709A
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English (en)
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KR20170101728A (ko
Inventor
송민우
변세기
유진
조성일
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삼성전자주식회사
한국과학기술원
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Priority to KR1020160024709A priority Critical patent/KR102491574B1/ko
Priority to US15/443,347 priority patent/US10076801B2/en
Publication of KR20170101728A publication Critical patent/KR20170101728A/ko
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Publication of KR102491574B1 publication Critical patent/KR102491574B1/ko

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/20—Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
    • B23K1/203—Fluxing, i.e. applying flux onto surfaces
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
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    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/008—Soldering within a furnace
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    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/19—Soldering, e.g. brazing, or unsoldering taking account of the properties of the materials to be soldered
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    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
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Abstract

반도체 패키지의 제조 방법에서, 제1 면 상에 접속 패드를 구비하는 기판의 상기 접속 패드 상에 탄소 나노 튜브를 포함하는 플럭스를 도포하고, 상기 플럭스가 도포된 접속 패드 상에 솔더볼을 배치하며, 리플로우 공정에 의해 상기 솔더볼로부터 상기 접속 패드에 부착된 솔더층을 형성하고, 상기 리플로우된 솔더볼이 반도체 칩에 구비된 접속 패드와 마주보도록 상기 반도체 칩을 상기 기판 상에 실장한다.

Description

반도체 패키지의 제조 방법{Method of manufacturing semiconductor package}
본 발명의 기술적 사상은 반도체 패키지 및 이의 제조 방법에 관한 것으로, 더욱 상세하게는, 플럭스를 사용한 반도체 패키지의 제조 방법과 이에 의하여 제조된 반도체 패키지에 관한 것이다.
전자 산업의 비약적인 발전 및 사용자의 요구에 따라 전자기기는 더욱 더 소형화 및 다기능화되고 있다. 이에 따라, 전자기기에 사용되는 반도체 장치의 소형화 및 다기능화의 필요성 또한 높아지고 있다. 이에 따라, 미세 피치의 연결 단자를 가지는 반도체 장치가 요구된다. 그러나, 미세 피치의 연결 단자에 연결되는 솔더볼의 사이즈 또한 감소하므로, 솔더볼의 부착 공정에서 접합 불량이 발생하기 쉽고, 이에 따라 상기 반도체 장치와 외부 장치 사이에 신뢰성 있는 전기적 연결을 제공하기 어렵다.
본 발명의 기술적 사상이 이루고자 하는 기술적 과제는 솔더볼의 리플로우 공정시 접합 불량을 방지할 수 있는 반도체 패키지의 제조 방법 및 이에 의해 제조된 반도체 패키지를 제공하는 데에 있다.
상기 기술적 과제를 달성하기 위한 본 발명의 기술적 사상에 따른 반도체 패키지의 제조 방법에서, 제1 면 상에 접속 패드를 구비하는 기판의 상기 접속 패드 상에 탄소 나노 튜브를 포함하는 플럭스를 도포하고, 상기 플럭스가 도포된 접속 패드 상에 솔더볼을 배치하며, 리플로우 공정에 의해 상기 솔더볼로부터 상기 접속 패드에 부착된 솔더층을 형성하고, 상기 리플로우된 솔더볼이 반도체 칩에 구비된 접속 패드와 마주보도록 상기 반도체 칩을 상기 기판 상에 실장한다.
예시적인 실시예들에 있어서, 상기 플럭스는 친수성 작용기가 부착된 탄소 나노 튜브를 포함할 수 있다.
예시적인 실시예들에 있어서, 상기 친수성 작용기는 히드록시기, 알콕시기, 니트로기, 시아노기, 아미노기, 아지도기 (azido group), 아미디노기 (amidino group), 히드라지노기 (hydrazino group), 히드라조노기 (hydrazono group), 카르보닐기 (carbonyl group), 카르바밀기 (carbamyl group), 티올기 (thiol group), 알릴아민기(allylamin group), 에테르기(ether group), 에스테르기 (ester group), 카르복실기 (carboxyl group), 카르복실기의 염, 술폰산기 (sulfonic acid group), 트리메톡시실란기(-Si(OCH3)3), 및 트리클로로실란기(-SiCl3)로 구성된 군으로부터 선택된 적어도 하나일 수 있다.
예시적인 실시예들에 있어서, 상기 플럭스는 약 0.01 wt% 내지 약 1.0 wt%의 탄소 나노 튜브를 포함할 수 있다.
예시적인 실시예들에 있어서, 상기 플럭스는 약 0.4 wt% 내지 약 0.8 wt%의 탄소 나노 튜브를 포함할 수 있다.
예시적인 실시예들에 있어서, 상기 탄소 나노 튜브는 단일벽 탄소 나노 튜브, 이중벽 탄소 나노 튜브, 다중벽 탄소 나노 튜브 및 탄소 나노 튜브 로프(rope)로 구성된 군으로부터 선택된 적어도 하나를 포함할 수 있다.
예시적인 실시예들에 있어서, 상기 플럭스를 도포하는 단계에서, 상기 접속 패드와 상기 플럭스 사이의 접촉각이 60도보다 작을 수 있다.
예시적인 실시예들에 있어서, 상기 기판은 인쇄 회로 기판, 연성 인쇄 회로 기판 또는 인터포저일 수 있다.
예시적인 실시예들에 있어서, 상기 솔더층을 형성하는 단계 이후에, 상기 솔더볼의 측벽 상에 또는 상기 접속 패드의 상면 상에 상기 탄소 나노 튜브를 포함하는 플럭스 잔류층이 형성될 수 있다.
예시적인 실시예들에 있어서, 상기 솔더층을 형성하는 단계 이후에, 상기 플럭스 잔류층을 제거하기 위한 세정 공정이 더 수행될 수 있다.
예시적인 실시예들에 있어서, 상기 반도체 칩을 상기 기판 상에 실장하는 단계 이후에, 상기 플럭스 잔류층을 제거하기 위한 세정 공정이 더 수행될 수 있다.
상기 기술적 과제를 달성하기 위한 본 발명의 기술적 사상에 따른 반도체 패키지의 제조 방법에서, 제1 면 상에 접속 패드를 구비하는 기판의 상기 접속 패드 상에 친수성 작용기가 부착된 탄소 나노 튜브를 포함하는 플럭스를 도포하고, 상기 플럭스가 도포된 접속 패드 상에 솔더볼을 배치하며, 리플로우 공정에 의해 상기 솔더볼로부터 상기 접속 패드에 부착된 솔더층을 형성하고, 상기 리플로우된 솔더볼이 반도체 칩에 구비된 접속 패드와 마주보도록 상기 반도체 칩을 상기 기판 상에 실장한다.
예시적인 실시예들에 있어서, 상기 플럭스는 약 0.4 wt% 내지 약 0.8 wt%의 탄소 나노 튜브를 포함할 수 있다.
예시적인 실시예들에 있어서, 상기 플럭스를 도포하는 단계에서, 상기 접속 패드와 상기 플럭스 사이의 접촉각이 60도보다 작을 수 있다.
예시적인 실시예들에 있어서, 상기 솔더층을 형성하는 단계 이후에, 상기 솔더볼의 측벽 상에 또는 상기 접속 패드의 상면 상에 상기 탄소 나노 튜브를 포함할 수 있다.
본 발명의 기술적 사상에 의한 반도체 패키지의 제조 방법에서, 친수성 작용기가 부착된 탄소 나노 튜브를 포함하는 플럭스를 접속 패드 상에 도포한다. 친수성 작용기가 부착된 탄소 나노 튜브를 포함하는 플럭스는 향상된 젖음 특성(wettability)을 가질 수 있고, 따라서 솔더볼의 리플로우 공정에서 접속 패드와 솔더볼 사이의 접착 불량이 방지될 수 있다. 또한, 탄소 나노 튜브를 포함하는 플럭스는 향상된 열 전도도를 가질 수 있다. 따라서, 솔더볼의 리플로우 공정에서 플럭스와 닿는 솔더볼 표면이 더욱 빠르게 용융될 수 있으므로 접속 패드와 솔더볼 사이의 접착 불량이 방지될 수 있다. 상기 반도체 패키지의 제조 방법에 따르면, 반도체 칩과 기판 사이에서 신뢰성 있는 전기적 연결을 제공할 수 있다.
도 1 내지 도 9는 예시적인 실시예들에 따른 반도체 패키지의 제조 방법을 나타내는 단면도들이다.
도 10은 예시적인 실시예들에 따른 반도체 패키지를 나타내는 단면도이다.
도 11은 예시적인 실시예들에 따른 반도체 패키지를 나타내는 단면도이다.
도 12는 예시적인 실시예들에 따른 탄소 나노 튜브의 구조를 나타내는 개략도이다.
도 13a 및 도 13b는 탄소 나노 튜브를 포함하는 플럭스의 젖음성 테스트 결과를 나타내는 그래프이다.
도 14a 및 도 14b는 탄소 나노 튜브를 포함하는 플럭스의 웨팅 발란스 테스트 결과를 나타내는 그래프이다.
도 15는 예시적인 실시예들에 따른 반도체 패키지를 포함하는 메모리 모듈의 평면도이다.
도 16은 예시적인 실시예들에 따른 반도체 패키지를 포함하는 메모리 카드의 개략도이다.
도 17은 예시적인 실시예들에 따른 반도체 패키지를 포함하는 전자 시스템의 일 예를 도시한 블록도이다.
본 발명의 구성 및 효과를 충분히 이해하기 위하여, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예들을 설명한다. 그러나 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라, 여러 가지 형태로 구현될 수 있고 다양한 변경을 가할 수 있다. 단지, 본 실시예들에 대한 설명은 본 발명의 개시가 완전하도록 하며, 본 발명이 속하는 기술 분야의 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위하여 제공되는 것이다. 첨부된 도면에서 구성 요소들은 설명의 편의를 위하여 그 크기를 실제보다 확대하여 도시한 것이며, 각 구성 요소의 비율은 과장되거나 축소될 수 있다.
어떤 구성 요소가 다른 구성 요소에 "상에" 있다거나 "접하여" 있다고 기재된 경우, 다른 구성 요소에 상에 직접 맞닿아 있거나 또는 연결되어 있을 수 있지만, 중간에 또 다른 구성 요소가 존재할 수 있다고 이해되어야 할 것이다. 반면, 어떤 구성 요소가 다른 구성 요소의 "바로 위에" 있다거나 "직접 접하여" 있다고 기재된 경우에는, 중간에 또 다른 구성 요소가 존재하지 않는 것으로 이해될 수 있다. 구성 요소들 간의 관계를 설명하는 다른 표현들, 예를 들면, "～사이에"와 "직접 ～사이에" 등도 마찬가지로 해석될 수 있다.
제1, 제2 등의 용어는 다양한 구성요소들을 설명하는데 사용될 수 있지만, 상기 구성요소들은 상기 용어들에 의해 한정되어서는 안된다. 상기 용어들은 하나의 구성요소를 다른 구성요소로부터 구별하는 목적으로만 사용될 수 있다. 예를 들어, 본 발명의 권리 범위를 벗어나지 않으면서 제1 구성요소는 제2 구성요소로 명명될 수 있고, 유사하게 제2 구성요소도 제1 구성요소로 명명될 수 있다.
단수의 표현은 문맥상 명백하게 다르게 표현하지 않는 한, 복수의 표현을 포함한다. "포함한다" 또는 "가진다" 등의 용어는 명세서 상에 기재된 특징, 숫자, 단계, 동작, 구성요소, 부분품 또는 이들을 조합한 것이 존재함을 지정하기 위한 것으로, 하나 또는 그 이상의 다른 특징들이나 숫자, 단계, 동작, 구성요소, 부분품 또는 이들을 조합한 것들이 부가될 수 있는 것으로 해석될 수 있다.
본 발명의 실시예들에서 사용되는 용어들은 다르게 정의되지 않는 한, 해당 기술 분야에서 통상의 지식을 가진 자에게 통상적으로 알려진 의미로 해석될 수 있다.
도 1 내지 도 9는 예시적인 실시예들에 따른 반도체 패키지의 제조 방법을 나타내는 단면도들이다.
도 1을 참조하면, 도전 패드(112A, 112B)를 구비하는 기판(110)이 제공된다.
예시적인 실시예들에 있어서, 기판(110)은 인쇄 회로 기판(printed circuit board, PCB), 연성 인쇄 회로 기판(flexible printed circuit board, FPCB) 또는 인터포저(interposer)일 수 있다. 기판(110)은 여러 물질들의 층이 적층된 적층 구조를 가질 수 있고, 상기 층들은 하나 이상의 금속 배선층과 하나 이상의 프리프레그(prepreg) 층을 포함할 수 있다. 상기 금속 배선층을 이루는 금속은 예를 들어 구리(Cu), 금(Au), 백금(Pt), 은(Ag), 니켈(Ni), 알루미늄(Al) 등일 수 있으나, 이에 한정되는 것은 아니다.
도시되지는 않았지만, 기판(110) 상면 상에 솔더 레지스트(solder resist)층이 더 형성될 수 있다. 상기 솔더 레지스트층은 기판(110)의 상면 및 하면 모두에 형성될 수도 있고, 상면과 하면 중 어느 한 면에만 형성될 수도 있다. 상기 솔더 레지스트층은 아크릴계 수지, 에폭시계 수지, 우레탄계 수지, 실리콘(silicone)계 수지, 파라자일렌계 수지, 파릴렌(parylene)계 수지 등일 수 있다. 상기 솔더 레지스트층은 기판(110)을 기계적으로 보호하고 부식을 방지하며 전기적인 특성을 개선하는 역할을 할 수 있다.
기판(110)의 상면에는 상기 상면 상에 실장되는 반도체 칩과의 전기적 연결을 위한 제1 접속 패드(112A)가 형성될 수 있다.
제1 접속 패드(112A)는 전도성의 패드로서, 예를 들어 금속 패드일 수 있다. 예시적인 실시예들에 있어서, 제1 접속 패드(112A)는 구리(Cu), 니켈(Ni), 알루미늄(Al), 금(Au), 백금(Pt) 및 은(Ag) 중 적어도 하나를 포함할 수 있다. 예를 들어, 제1 접속 패드(112A)는 구리(Cu)를 포함할 수 있다. 예를 들어, 제1 접속 패드(112A)는 니켈(Ni) 및 금(Au)의 이중층 구조로 형성될 수도 있다.
또한, 기판(110)의 하면에는 외부 장치와의 전기적 연결을 위한 제2 접속 패드(112B)가 형성될 수 있다. 제2 접속 패드(112B) 또한 제1 접속 패드(112A)와 마찬가지로 전도성의 패드로서 예를 들어 금속 패드일 수 있다. 예시적인 실시예들에 있어서, 제2 접속 패드(112B)는 구리(Cu), 니켈(Ni), 알루미늄(Al), 금(Au), 백금(Pt) 및 은(Ag) 중 적어도 하나를 포함할 수 있다. 예를 들어, 제2 접속 패드(112B)는 구리(Cu)를 포함할 수 있다. 예를 들어, 제2 접속 패드(112B)는 니켈(Ni) 및 금(Au)의 이중층 구조로 형성될 수도 있다.
선택적으로, 제1 및 제2 도전 패드(112A, 112B)의 상면 상에는 유기 솔더 보존제(organic solderability preservative, OSP)를 포함하는 패시베이션층(도시 생략)이 더 형성될 수 있다. 예를 들어 접속 패드(112A, 112B)이 구리를 포함하고 접속 패드(112A, 112B)의 최상부면에 구리 표면이 노출될 때, 상기 패시베이션층은 상기 구리 표면에 부착되어 구리 원소와 화학 결합을 형성할 수 있는 벤조트리아졸(benzotriazole) 또는 이미다졸(imidazole) 등의 유기 화합물을 포함할 수 있다. 상기 패시베이션층은 접속 패드(112A, 112B)의 표면에 원치 않는 산화 반응이 발생하거나 접속 패드(112A, 112B) 표면의 손상이 발생하는 것으로부터 보호하도록 작용할 수 있다. 예를 들어, 상기 패시베이션층은 약 수십 내지 수백 나노미터의 두께를 가질 수 있다.
도 2를 참조하면, 제1 접속 패드(112A) 상에 플럭스(120)가 도포될 수 있다.
플럭스(120)는 제1 접속 패드(112A) 상에 형성된 산화막, 예를 들어 구리의 산화막 등을 제거하고 제1 접속 패드(112A)의 재산화를 방지하여, 플럭스(120) 상에 놓여질 솔더볼과 제1 접속 패드(112A) 사이에 안정된 접합을 형성할 수 있게 한다.
예시적인 실시예들에 있어서, 플럭스(120)는 탄소 나노 튜브(carbon nanotube, CNT)(122)(도 12 참조)가 소정의 농도로 함유된 플럭스제(flux agent)를 포함할 수 있다. 상기 플럭스제는 활성 로진(rosin) 또는 비활성 로진과 같은 로진계 플럭스; 염류, 산류, 아민류와 같은 수용성 플럭스; 그루타민산 염산염, 에틸렌디아민 스테아린산 염산염과 같은 유기계 플럭스; 염화 아연계, 염화아연-염화암모니아계와 같은 무기계 플럭스일 수 있다. 그러나 상기 플럭스제의 종류가 이에 한정되는 것은 아니다.
예를 들어 상기 플럭스제가 로진계 플럭스일 때, 상기 플럭스제는 수지, 활성화제 및 용매를 포함할 수 있다. 상기 수지는 로진, 또는 로진 유도체일 수 있고, 예를 들어 상기 플럭스제의 약 10 내지 50 wt%의 함량을 가질 수 있다. 상기 활성화제는 카르복실산, 술폰산, 포스폰산, 아미노산 및 알칸올 아민 중 적어도 하나일 수 있고, 예를 들어 상기 플럭스제의 약 0.1 내지 10 wt%의 함량을 가질 수 있다. 상기 용매는 글리콜 에테르 에스테르계 화합물, 글리콜 에테르계 화합물, 에스테르계 화합물, 케톤계 화합물 및 시클릭 에스테르계 화합물 중 적어도 하나일 수 있고, 예를 들어 상기 플럭스제의 약 10 내지 90 wt%의 함량을 가질 수 있다. 그러나, 상기 플럭스제의 종류 및 조성이 이에 한정되는 것은 아니다.
예시적인 실시예들에 있어서, 플럭스(120)는 탄소 나노 튜브(122)가 약 0.01 내지 1 wt%의 함량으로 함유된 상기 플럭스제를 포함할 수 있다. 예를 들어, 플럭스(120)는 탄소 나노 튜브(122)가 약 0.4 내지 약 0.8 wt% 함량으로 함유된 상기 플럭스제를 포함할 수 있다. 플럭스(120)가 약 0.4 내지 약 0.8 wt%의 탄소 나노 튜브(122)를 포함할 때, 플럭스(120)의 젖음 특성(wettability)이 더욱 향상되어 후속 공정에 수행되는 솔더볼의 리플로우 과정에서 접속 패드(112A, 112B)와 솔더볼 사이의 접착 불량이 방지될 수 있다. 한편, 탄소 나노 튜브(122)의 함량과 플럭스(120)의 젖음 특성에 관련된 내용은 이후 도 13a 내지 도 14b를 참조로 하여 상세히 설명한다.
예시적인 실시예들에 있어서, 플럭스(120)는 친수성 작용기들이 부착된 탄소 나노 튜브(122)를 포함할 수 있다. 예를 들어, 탄소 나노 튜브(122)가 상기 플럭스제 내에서 균일하게 분산될 수 있도록 탄소 나노 튜브(122)의 표면에 친수성 작용기들이 부착될 수 있다.
예시적인 실시예들에 있어서, 탄소 나노 튜브(122)는 단일벽 탄소 나노 튜브(single wall CNT), 이중벽 탄소 나노 튜브(double wall CNT), 다중벽 탄소 나노 튜브(multi-wall CNT), 탄소 나노 튜브 로프(CNT rope) 등을 포함할 수 있다. 탄소 나노 튜브(122)의 직경은 약 수 내지 수백 나노미터일 수 있고, 탄소 나노 튜브(122)의 길이는 약 수십 나노미터 내지 수십 마이크로미터일 수 있다. 그러나, 탄소 나노 튜브(122)의 직경 및 길이가 이에 한정되는 것은 아니다.
예시적인 실시예들에 있어서, 상기 친수성 작용기는 히드록시기, 알콕시기, 니트로기, 시아노기, 아미노기, 아지도기(azido group), 아미디노기(amidino group), 히드라지노기(hydrazino group), 히드라조노기(hydrazono group), 카르보닐기(carbonyl group), 카르바밀기(carbamyl group), 티올기(thiol group), 알릴아민기(allylamin group), 에테르기(ether group), 에스테르기(ester group), 카르복실기(carboxyl group), 카르복실기의 염, 술폰산기(sulfonic acid group), 트리메톡시실란기(-Si(OCH3)3), 트리클로로실란기(-SiCl3), 등일 수 있으나, 본 발명의 기술적 사상이 전술한 바에 한정되는 것은 아니다.
도 12에는 예시적인 실시예들에 따른 탄소 나노 튜브(122)의 구조를 나타내는 개략도가 도시된다. 도 12에 예시적으로 도시된 것과 같이, 플럭스(120)는 그 측벽 및 말단에 카르복실기(-COOH)가 부착된 단일벽 탄소 나노 튜브(122)를 포함할 수 있다. 그러나, 본 발명의 기술적 사상이 이에 한정되는 것은 아니다. 도 12에 도시된 것과는 달리, 탄소 나노 튜브(122)에는 전술한 친수성 작용기들 중 카르복실기를 제외한 다른 친수성 작용기들 중 하나의 종류가 부착될 수도 있다. 또한, 도 12에 도시된 것과는 달리, 탄소 나노 튜브(122)에는 전술한 친수성 작용기들 중 선택된 2개 이상의 종류들이 부착될 수도 있다.
예시적인 실시예들에 있어서, 탄소 나노 튜브가 분산된 분산 용액을 산처리함에 의해 친수성 작용기가 부착된 탄소 나노 튜브(122)를 준비할 수 있다. 예를 들어, 상기 분산 용액은 유기 용매에 소정 농도의 탄소 나노 튜브를 분산시켜 형성할 수 있다. 이후, 상기 분산 용액에 질산, 황산, 염산 및 과염소산 중에서 선택된 1종 이상을 첨가하여 상기 산처리를 수행할 수 있다. 상기 산처리는 예를 들어 20℃ 내지 200℃의 온도에서 수십 분 내지 수 시간동안 수행될 수 있다. 상기 산처리 동안에 탄소 나노 튜브(122)의 말단 또는 측벽 상에 친수성 작용기가 부착될 수 있다. 이후, 상기 산처리한 용액을 여과하고, 잔류하는 비정질 탄소 등을 제거하기 위한 열처리를 선택적으로 수행함으로써 친수성 작용기가 부착된 탄소 나노 튜브(122)를 얻을 수 있다.
카르복실기가 부착된 탄소 나노 튜브(122)를 제조하기 위한 예시적인 공정에 따르면, 단일벽 탄소 나노 튜브를 질산 및 황산을 1 : 3의 몰비로 포함하는 분산 용액에 넣고, 상기 분산 용액을 100℃ 내지 140℃에서 1 내지 3시간 동안 초음파 믹싱할 수 있다. 그러나, 친수성 작용기가 부착된 탄소 나노 튜브를 제조하기 위한 공정이 이에 한정되는 것은 아니다.
다시 도 2를 참조하면, 플럭스(120)는 제1 접속 패드(112A) 상면 전체 면적 상에 배치될 수 있다. 도 2에는 플럭스(120)가 제1 접속 패드(112A)의 상면 전체 면적 상에 배치되고, 제1 접속 패드(112A) 주위의 기판(110) 표면 상에는 배치되지 않은 것으로 예시적으로 도시되었으나, 본 발명의 기술적 사상이 이에 한정되는 것은 아니다. 도 2에 도시된 것과는 달리, 플럭스(120)가 제1 접속 패드(112A)의 상면 전체 면적을 커버하고, 제1 접속 패드(112A) 주위의 기판(110) 상면 부분 또한 커버하도록 배치될 수도 있다.
도 2에 도시된 것과 같이, 플럭스(120)는 제1 접속 패드(112A) 및/또는 기판(110) 상면과 약 60도보다 작은 접촉각을 갖도록 배치될 수 있다. 그러나, 플럭스(120)의 접촉각이 이에 한정되는 것은 아니다. 플럭스(120)의 접촉각 특성에 대하여 이후 도 13a 및 도 13b를 참조로 설명하도록 한다.
일반적으로 탄소 나노 튜브는 소수성을 가지며, 용매 또는 점성 폴리머 용액(melt) 내에서 고르게 분산되지 않고 서로 뭉쳐지는(agglomerate) 경향이 있다. 따라서, 탄소 나노 튜브는 수용성 플럭스 내에 첨가되더라도 고르게 분산되지 않는다. 그러나, 전술한 방법에 따라 제조된, 그 말단 또는 측벽에 친수성 작용기가 부착된 탄소 나노 튜브(122)는 수용성 플럭스 내에 고르게 분산될 수 있다. 또한, 친수성 작용기가 부착된 탄소 나노 튜브(122)를 0.01 내지 1 wt% 포함한 플럭스(120)는 젖음 특성이 향상될 수 있다. 따라서, 예를 들어 플럭스(120) 도팅(dotting) 설비의 공차에 의하여 제1 접속 패드(112A) 상부에 상대적으로 작은 양의 플럭스(120)가 놓여지더라도, 플럭스(120)의 우수한 젖음 특성에 기인하여 도 2에 도시된 것과 같이 플럭스(120)는 제1 접속 패드(112A)의 상면 전체 면적을 커버하도록 배치될 수 있다. 따라서, 후속 공정에서 솔더볼(130)(도 3 참조)의 오정렬(misalign) 또는 위치 이동이 발생하더라도, 솔더볼과 플럭스(120) 사이의 접촉이 보장될 수 있다.
도 3을 참조하면, 플럭스(120)가 도포된 제1 접속 패드(112A) 상에 솔더볼(130)이 배치될 수 있다.
예시적인 실시예들에 있어서, 솔더볼(130)은 구형 또는 볼 형상을 가질 수 있다. 솔더볼(130)은 주석(Sn), 인듐(In), 비스무트(Bi), 안티모니(Sb), 구리(Cu), 은(Ag), 아연(Zn), 납(Pb) 및/또는 이들의 합금을 포함할 수 있다. 예를 들어, 솔더볼(130)은 Sn, Pb, Sn-Pb, Sn-Ag, Sn-Au, Sn-Cu, Sn-Bi, Sn-Zn, Sn-Ag-Cu, Sn-Ag-Bi, Sn-Ag-Zn, Sn-Cu-Bi, Sn-Cu-Zn, Sn-Bi-Zn 등을 포함할 수 있다.
솔더볼(130)이 플럭스(120)가 도포된 제1 접속 패드(112A) 상에 놓여짐에 따라 솔더볼(130)의 측벽 하측은 플럭스(120)와 접촉할 수 있고, 플럭스(120)가 우수한 젖음 특성을 가지므로 솔더볼(130)과 플럭스(120)의 접촉 면적이 상대적으로 클 수 있다. 플럭스(120)의 점도가 더 작은 경우, 도 3에 도시된 것과는 달리 플럭스(120)가 솔더볼(130)의 표면의 실질적으로 전체를 커버하도록 플럭스(120)가 솔더볼(130) 표면을 둘러쌀 수도 있다.
도 4를 참조하면, 리플로우 공정을 수행하여 제1 접속 패드(112A) 상에 제1 솔더층(130R)을 형성할 수 있다.
상기 리플로우 공정은 약 200℃ 내지 약 280℃의 온도에서 수십 초 내지 수 분 동안 수행될 수 있다. 예를 들어, 예열 온도 150℃ 내지 180℃를 수십 초 동안 유지하고, 피크 온도를 260℃로 하여 200℃에서 수십 초 동안 유지할 수 있다. 상기 리플로우 공정의 조건은 제1 솔더층(130R)의 합금 조성에 따라 적절히 선택될 수 있다.
상기 리플로우 공정에 의해, 제1 솔더층(130R)과 제1 접속 패드(112A)의 접촉 계면에는 중간층(도시 생략)이 형성될 수 있다. 상기 중간층은 제1 솔더층(130R)과 제1 접속 패드(112A) 내에 포함된 금속 물질들이 상대적으로 높은 온도에서 반응하여 형성된 금속간 화합물(intermetallic compound, IMC)을 포함할 수 있다. 예를 들어, 제1 접속 패드(112A)가 구리 및/또는 니켈을 포함하고, 제1 솔더층(130R)이 주석 및/또는 구리를 포함할 때, 상기 중간층은 (Cu,Ni)6Sn5, (Cu,Ni)3Sn4 또는 (Cu,Ni)3Sn 중 적어도 하나를 포함할 수 있다. 그러나, 상기 중간층의 물질 또는 조성은 이에 한정되는 것이 아니며, 제1 솔더층(130R)과 제1 접속 패드(112A)의 물질, 리플로우 공정의 온도 및 시간 등에 따라 달라질 수 있다.
플럭스(120)는 제1 솔더층(130R)과 제1 접속 패드(112A) 사이의 접촉 계면에서, 제1 접속 패드(112A)의 산화 등에 의해 형성된 산화막을 제거하여 제1 솔더층(130R)과 제1 접속 패드(112A) 사이에 안정한 중간층이 형성될 수 있도록 할 수 있다.
특히, 제1 접속 패드(112A) 상에 유기 솔더 보존제(OSP)를 포함하는 패시베이션층이 더 형성된 경우에, 상기 패시베이션층은 예를 들어 제1 접속 패드(112A) 내에 포함된 구리 원소와 배위 결합하여 형성된 구리 착화합물(complex compound)을 포함할 수 있다. 상기 리플로우 공정 이전에 상기 패시베이션층이 완전히 제거되지 않는 경우에, 솔더볼(130)과 제1 접속 패드(112A) 사이의 접촉 면적이 감소되어 솔더볼(130)과 제1 접속 패드(112A) 사이에 안정한 접합이 형성되기 어려울 수 있다.
그러나, 예시적인 실시예들에 따르면 플럭스(120)는 친수성 작용기가 부착된 탄소 나노 튜브(122)를 포함할 수 있고, 이에 따라 플럭스(120)는 상대적으로 우수한 젖음 특성을 가질 수 있다. 따라서, 플럭스(120)가 제1 접속 패드(112A)의 전체 면적 상에 놓여짐에 따라 제1 접속 패드(112A) 상에 형성된 산화막, 또는 상기 패시베이션층을 완전히 제거하여 제1 접속 패드(112A)와 제1 솔더층(130R) 사이의 접촉 면적이 증가될 수 있다. 또한 플럭스(120)가 솔더볼(130)의 측벽 하측 상에도 놓여짐에 따라 제1 솔더층(130R) 측벽에 원치 않게 형성된 산화막 등이 제거될 수 있다. 따라서, 제1 솔더층(130R)과 제1 접속 패드(112A) 사이에 더욱 안정한 접합이 가능할 수 있다.
예시적인 실시예들에 따르면, 플럭스(120)는 친수성 작용기가 부착된 탄소 나노 튜브(122)를 포함할 수 있고, 이에 따라 플럭스(120)는 상대적으로 높은 열전도도를 가질 수 있다. 일반적으로, 탄소 나노 튜브는 약 3000W/m · K의 높은 열전도도를 가지므로, 폴리머 매트릭스 내에 탄소 나노 튜브가 약 1 wt% 이내로 첨가된 경우 탄소 나노 튜브가 첨가되지 않은 경우에 비하여 약 50% 내지 200% 가량 열전도도가 증가될 수 있다. 한편, 탄소 나노 튜브의 함량이 약 1 wt%보다 큰 경우에, 폴리머 매트릭스 내에 다량으로 함유된 탄소 나노 튜브가 균일하게 분산되지 않을 수 있고, 탄소 나노 튜브 간의 접촉 열저항(thermal resistance)이 증가하여 열 전달이 방해될 수 있으므로, 상기 폴리머 매트릭스의 열전도도가 오히려 감소될 수 있다. 예시적인 실시예들에 따르면, 플럭스(120)는 약 0.01 내지 1.0 wt%의 탄소 나노 튜브(122)를 포함할 수 있고, 상기 조성 범위의 탄소 나노 튜브(122)를 포함하는 플럭스(120)는 증가된 열전도도를 가질 수 있다. 따라서, 상기 리플로우 공정에서, 플럭스(120)를 통해 솔더볼(130) 표면에 열 전달이 빠르게 될 수 있고, 이에 따라 제1 솔더층(130R)과 제1 접속 패드(112A) 사이에 더욱 안정한 접합이 가능할 수 있다.
상기 리플로우 공정 이후에 플럭스 잔류층(120R1)이 제1 솔더층(130R) 측벽 일부 상에 잔류할 수 있다. 플럭스 잔류층(120R1)은 제1 접속 패드(112A) 상면 및/또는 제1 접속 패드(112A) 주위의 기판(110) 상면 부분에도 잔류할 수 있다. 도 4에 도시된 것과 같이, 플럭스 잔류층(120R1)은 제1 솔더층(130R) 측벽 일부 상에 배치되는 측벽 부분(120RS) 및 기판(110) 상면 부분에 배치되는 바닥 부분(120RB)을 포함할 수 있다. 플럭스 잔류층(120R1)은 상기 리플로우 공정의 높은 온도에 의해 플럭스(120)에 포함된 플럭스제, 예를 들어 수지, 활성화제 및 용매가 증발된 후 남은 잔류물을 포함할 수 있다. 또한, 플럭스(120) 내에 분산되어 존재하던 탄소 나노 튜브(122) 또한 플럭스 잔류층(120R1) 내에 포함될 수 있다.
예시적인 실시예들에 있어서, 플럭스 잔류층(120R1)의 측벽 부분(120RS)은 제1 솔더층(130R)의 높이(t1)보다 작은 높이(t2)를 가지며, 제1 솔더층(130R)의 측벽 상에 배치될 수 있다. 플럭스 잔류층(120R1)의 측벽 부분(120RS)의 높이(t2)는 제1 솔더층(130R)의 높이(t1)의 70%보다 작을 수 있으나, 본 발명의 기술적 사상이 이에 한정되는 것은 아니다. 예를 들어, 플럭스(120)가 우수한 젖음 특성을 가질수록 플럭스 잔류층(120R1)의 측벽 부분(120RS)의 높이(t2)가 클 수 있다.
도 4에서는 제1 솔더층(130R) 측벽 및 기판(110) 상면 상에 플럭스 잔류층(120R1)이 상당한 두께로 연속적으로 형성된 것으로 도시되었으나, 이는 설명의 편의를 위하여 과장되게 도시된 것이다. 도 4에 도시된 것과는 다르게, 플럭스 잔류층(120R1)의 두께는 매우 얇게 형성될 수 있으며, 또한 플럭스 잔류층(120R1)이 제1 솔더층(130R) 측벽 및 기판(110) 상면 상에 불연속적으로 형성될 수도 있다.
선택적으로, 플럭스 잔류층(120R1) 세정 공정이 수행되어, 기판(110) 상면 및 제1 솔더층(130R) 측벽 상에 부착된 플럭스 잔류층(120R1) 부분이 제거될 수도 있다. 상기 세정 공정에서 공지의 플럭스 세정제가 사용될 수 있다.
도 5를 참조하면, 기판(110) 상에 반도체 칩(140)이 실장될 수 있다.
반도체 칩(140)은 반도체 기판(142)과 그 활성면 쪽에 구비된 접속 패드(144)를 포함할 수 있다.
예시적인 실시예들에 있어서, 반도체 기판(142)은 실리콘(Si) 기판일 수 있다. 다른 실시예들에 있어서 반도체 기판(142)은 Ge (germanium)과 같은 반도체 원소, 또는 SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), 및 InP (indium phosphide)와 같은 화합물 반도체를 포함할 수 있다. 적어도 하나의 실시예에서, 반도체 기판(142)은 SOI (silicon on insulator) 구조를 가질 수 있다. 예를 들면, 반도체 기판(142)은 BOX 층 (buried oxide layer)을 포함할 수 있다. 일부 실시예들에서, 반도체 기판(142)은 도전 영역, 예를 들면 불순물이 도핑된 웰 (well), 또는 불순물이 도핑된 구조물을 포함할 수 있다. 또한, 반도체 기판(142)은 STI (shallow trench isolation) 구조와 같은 다양한 소자분리 구조를 가질 수 있다.
반도체 기판(142)의 활성면에는 다양한 반도체 소자들이 제공될 수 있다. 상기 반도체 소자들은 메모리 소자, 코어 회로 소자, 주변 회로 소자, 로직 회로 소자 또는 제어 회로 소자를 포함할 수 있다. 상기 메모리 소자의 예로서는, 예를 들어 DRAM, SRAM 등과 같은 휘발성 반도체 메모리 소자와 예를 들어 EPROM, EEPROM, Flash EEPROM 등과 같은 비휘발성 메모리 소자를 들 수 있다. 선택적으로, 반도체 기판(142)의 활성면에는 시스템 LSI(large-scale integration), CIS (CMOS imaging sensor) 등과 같은 이미지 센서, MEMS (micro-electro-mechanical system), 능동 소자, 수동 소자 등을 포함할 수 있다.
또한, 반도체 기판(142)의 활성면에는 상기 반도체 소자들 위에 배선층이 구비될 수 있다. 상기 배선층은 배선 패턴과 절연층을 포함할 수 있다. 또한 상기 배선 패턴은 전극 단자인 접속 패드(144)와 전기적으로 연결될 수 있다.
도 5에 도시된 것과 같이, 접속 패드(144)가 제1 솔더층(130R)을 마주보도록 반도체 칩(140)의 활성면이 아래 방향을 향해 놓여질 수 있다.
이후, 리플로우 공정을 수행하여 제1 솔더층(130R)과 접속 패드(144)가 서로 접합될 수 있다.
도 6을 참조하면, 반도체 칩(140)과 기판(110) 사이의 공간에 언더필층(152)이 형성될 수 있다. 언더필층(152)은 제1 솔더층(130R) 및/또는 플럭스 잔류층(120R1)의 측벽을 둘러싸며 서로 인접한 제1 솔더층(130R) 사이의 공간을 채울 수 있다.
도 7을 참조하면, 반도체 칩(140)의 상면 및 측벽을 둘러싸는 몰딩재(154)를 형성할 수 있다. 몰딩재(154)는 에폭시 몰드 컴파운드(epoxy mold compound, EMC) 등을 사용하여 형성될 수 있다.
한편, 도 6 및 도 7을 참조로 설명한 것과는 달리, 언더필층(152)이 형성되지 않고, 몰딩재(154)가 반도체 칩(140)의 상면 및 측벽, 제1 솔더층(130R) 및/또는 플럭스 잔류층(120R1)의 측벽 상에 형성되어 반도체 칩(140)과 기판(110) 사이의 공간을 채울 수도 있다.
도 8을 참조하면, 기판(110)의 하면, 즉 제2 접속 패드(112B)가 노출된 기판(112) 표면이 위를 향하도록 기판(110)과 반도체 칩(140)의 접합 구조를 뒤집는다.
이후, 제2 접속 패드(112B) 상에 플럭스(120)를 도포할 수 있다. 예시적인 실시예들에 있어서, 플럭스(120)는 친수성 작용기가 부착된 탄소 나노 튜브(122)를 포함할 수 있다. 플럭스(120)에 대한 기술적 특징은 앞서 도 2를 참조로 한 설명을 참조할 수 있다.
도 9를 참조하면, 플럭스(120)가 도포된 제2 접속 패드(112B) 상에 솔더볼(도시 생략)이 놓여질 수 있다. 이후, 리플로우 공정을 수행하여 상기 솔더볼이 제2 접속 패드(112B)와 부착되어, 제2 접속 패드(112B) 상에 제2 솔더층(160)이 형성될 수 있다. 한편, 제2 솔더층(160) 측벽 및 제2 접속 패드(112B) 주위의 기판(110) 표면 상에 플럭스 잔류층(120R2)이 형성될 수 있다. 플럭스 잔류층(120R2)에 대한 특징은 앞서 도 5를 참조로 설명한 플럭스 잔류층(120R1)의 특징과 유사할 수 있다.
전술한 공정을 수행하여 반도체 패키지(100)가 완성될 수 있다.
상기 반도체 패키지(100)의 제조 방법에 따르면, 친수성 작용기가 부착된 탄소 나노 튜브(122)를 포함하는 플럭스를 접속 패드 상에 도포한다. 친수성 작용기가 부착된 탄소 나노 튜브(122)를 포함하는 플럭스는 향상된 젖음 특성(wettability)을 가질 수 있고, 따라서 솔더볼의 리플로우 공정에서 접속 패드와 솔더볼 사이의 접착 불량이 방지될 수 있다. 또한, 탄소 나노 튜브(122)를 포함하는 플럭스는 향상된 열 전도도를 가질 수 있다. 따라서, 솔더볼의 리플로우 공정에서 플럭스와 닿는 솔더볼 표면이 더욱 빠르게 용융될 수 있으므로 접속 패드와 솔더볼 사이의 접착 불량이 방지될 수 있다. 상기 반도체 패키지의 제조 방법에 따르면, 반도체 칩과 기판 사이에서 신뢰성 있는 전기적 연결을 제공할 수 있다.
이하에서는 탄소 나노 튜브를 포함하는 플럭스의 표면 특성을 도 13a 내지 도 14b를 참조로 설명하도록 한다.
도 13a 및 도 13b는 탄소 나노 튜브를 포함하는 플럭스의 젖음성 테스트 결과를 나타내는 그래프이다. 도 13a 및 도 13b에는 탄소 나노 튜브를 포함하지 않는 플럭스(WA1), 탄소 나노 튜브를 0.4 wt% 포함하는 플럭스(WA2) 및 탄소 나노 튜브를 0.8 wt% 포함하는 플럭스(WA3)에 대하여 측정된 물 접촉각을 도시하였다.
도 13a 및 도 13b를 참조하면, 탄소 나노 튜브를 포함하는 플럭스(WA2, WA3)는 각각 θ2 = 27.7 ± 0.7˚ 및 θ3 = 26.7 ± 0.5˚의 접촉각을 가짐이 측정되었으며, 반면 탄소 나노 튜브를 포함하지 않는 플럭스(WA1)는 θ1 = 30.5 ± 0.3˚의 접촉각을 가짐이 측정되었다. 도 13b에 예시적으로 도시된 것과 같이, 탄소 나노 튜브를 0.4 wt% 포함하는 플럭스(WA2, b-2)의 경우에, 탄소 나노 튜브를 포함하지 않는 플럭스(WA1, b-1)의 경우보다 더 작은 접촉각을 가지며, 탄소 나노 튜브를 0.8 wt% 포함하는 플럭스(WA3, b-3)의 경우에 가장 작은 접촉각을 가짐을 확인할 수 있다. 따라서, 탄소 나노 튜브를 0.4 wt% 및 0.8 wt% 포함하는 플럭스는 젖음 특성이 향상됨을 확인할 수 있다.
도 14a 및 도 14b는 탄소 나노 튜브를 포함하는 플럭스의 웨팅 밸런스 테스트 결과를 나타내는 그래프이다. 도 14a에는 탄소 나노 튜브를 포함하지 않는 플럭스(WB1), 탄소 나노 튜브를 0.8 wt% 포함하는 플럭스(WB2) 및 탄소 나노 튜브를 0.4 wt% 포함하는 플럭스(WB3)에 대하여 시간에 따라 측정된 젖음 시간(wetting time, t0) 및 최대 젖음 힘(maximum wetting force, Fmax)을 도시하였다.
도 14a 및 도 14b를 참조하면, 탄소 나노 튜브를 0.4 wt% 포함하는 플럭스(WB2) 및 탄소 나노 튜브를 0.4 wt% 포함하는 플럭스(WB3)는 탄소 나노 튜브를 포함하지 않는 플럭스(WB1)보다 작은 젖음 시간(t0)을 갖는다. 젖음 시간(t0)은 시편에 솔더가 얼마나 빨리 젖어 올라가는가를 나타내는 척도이며, 젖음 시간(t0)이 1초 이내의 값인 경우 유리하다. 또한 최대 젖음 힘(Fmax)은 충분히 젖은 솔더가 시편을 당기는 힘을 나타내며, 최대 젖음 힘(Fmax)이 클수록 유리하다. 도 14b에 도시된 것과 같이, 탄소 나노 튜브를 포함하는 플럭스(WB2, WB3)가 탄소 나노 튜브를 포함하지 않는 플럭스(WB1)에 비하여 더욱 작은 젖은 시간(t0) 및 더욱 큰 최대 젖음 힘(Fmax)을 가지므로, 탄소 나노 튜브를 포함하는 플럭스(WB2, WB3)가 향상된 젖음 특성을 가짐을 확인할 수 있다.
도 10은 예시적인 실시예들에 따른 반도체 패키지(100A)를 나타내는 단면도이다.
도 10을 참조하면, 우선 도 1 내지 도 9를 참조로 설명한 공정을 수행하여 반도체 칩(140)과 기판(110)의 접합 구조를 형성한 후에, 기판(110)의 하면(또는 제2 접속 패드(112B)가 노출되는 기판(110) 표면) 상에 부착된 플럭스 잔류층(120R2)(도 9 참조)을 세정하기 위한 세정 공정을 수행할 수 있다.
상기 세정 공정은 공지의 플럭스 세정제를 사용하여 수행될 수 있다. 예를 들어, 상기 플럭스 세정제는 수계 플럭스 세정제일 수 있다. 예를 들어, 상기 세정 공정은 약 20℃ 내지 약 50℃의 세정제 온도에서, 수십 초 내지 수분 간 수행될 수 있다.
상기 세정 공정에 의해, 기판(110)의 하면(또는 제2 접속 패드(112B)가 노출되는 기판 표면) 및 제2 솔더층(160) 측벽 상에 형성된 플럭스 잔류층(120R2)이 제거될 수 있다.
한편, 도 10에서는, 기판(110)의 상면(또는 제1 접속 패드(112A)가 노출되는 기판(110) 표면) 상에 부착된 플럭스 잔류층(120R1)은 제거되지 않은 것이 예시적으로 도시되었다. 그러나, 도 10에 도시된 것과는 달리, 반도체 칩(140)을 기판(110) 상에 실장하기 위한 공정 이전에, 또는 이후에 추가의 세정 공정이 수행되어 기판(110)의 상면 및 제1 솔더층(130R) 측벽 상에 부착된 플럭스 잔류층(120R1) 또한 제거될 수도 있다. 이러한 경우에, 언더필층(152)과 제1 솔더층(130R) 사이에 플럭스 잔류층(120R1)이 배치되지 않을 수도 있다.
도 11은 예시적인 실시예들에 따른 반도체 패키지(200)를 나타내는 단면도이다.
도 11을 참조하면, 기판(210) 위에 제1 반도체 칩(220)과 제2 반도체 칩(240)이 순차 적층될 수 있다. 여기서, 제1 반도체 칩(220)은 기판 관통 비아(through substrate via, TSV) 전극을 가질 수 있고, 제2 반도체 칩(240)은 제1 반도체 칩(220) 상에 플립 칩 실장될 수 있다.
기판(210)은 인쇄회로 기판 또는 연성 인쇄회로 기판일 수 있다. 기판(210)의 상부 표면에는 제1 반도체 칩(220)과의 전기적인 연결을 위한 접속 패드(216)가 구비될 수 있다.
접속 패드(216)는 전도성의 패드로서 예를 들면 금속 패드일 수 있다. 보다 구체적으로, 접속 패드(216)는 예를 들면, 구리(Cu) 패드이거나 니켈(Ni) 패드이거나 니켈이 도금된 알루미늄(Al) 패드일 수 있다. 그러나 여기에 한정되는 것은 아니다.
또한, 기판(210)의 하부 표면에는 외부 장치와의 전기적 연결을 위한 접속 패드(214)가 구비될 수 있다. 기판(210)의 하부 표면에 구비된 접속 패드(214)도 상부 표면에 구비된 접속 패드(216)와 마찬가지로 전도성의 패드이며, 중복되는 설명은 여기에서 생략한다.
접속 패드(214) 상에는 외부 장치와 접속되기 위한 솔더층(290)이 구비될 수 있다. 솔더층(290)은 주석(Sn)계의 솔더 범프일 수 있다. 보다 구체적으로, 솔더층(290)은 은(Ag) 및/또는 구리(Cu)를 포함하고 주석(Sn)을 주성분으로 하는 솔더 범프일 수 있다. 그러나, 여기에 한정되는 것은 아니다.
제1 반도체 칩(220)은 반도체 층(221), 관통 전극(222), 및 배선층(225)을 포함한다. 배선층(225) 내에는 관통 전극(222)과 접속되는 비아 패드(224), 상기 제2 반도체 칩(240)과의 전기적인 연결을 위한 접속 패드(226), 및 비아 패드(224)와 접속 패드(226)를 전기적으로 연결하기 위한 내부 배선이 구비될 수 있다.
반도체 층(221)은 도 5의 반도체 기판(142)를 참조하여 상세하게 설명하였으므로, 여기서는 중복되는 설명을 생략한다.
관통 전극(222)은 절연층, 시드층 및 도전층이 순차적으로 형성된 구조일 수 있다. 상기 절연층은 상기 도전층을 반도체 층(221)으로부터 전기적으로 절연할 수 있다. 상기 절연층은 산화물, 질화물, 또는 산질화물을 포함할 수 있고, 예를 들어 실리콘 산화물, 실리콘 질화물, 또는 실리콘 산질화물을 포함할 수 있다. 상기 도전층은 예를 들어 금속을 포함할 수 있다. 상기 도전층은, 예를 들어 알루미늄(Al), 금(Au), 베릴륨(Be), 비스무트(Bi), 코발트(Co), 구리(Cu), 하프늄(Hf), 인듐(In), 망간(Mn), 몰리브덴(Mo), 니켈(Ni), 납(Pb), 팔라듐(Pd), 백금(Pt), 로듐(Rh), 레늄(Re), 루테늄(Ru), 탄탈륨(Ta), 텔륨(Te), 티타늄(Ti), 텅스텐(W), 아연(Zn), 지르코늄(Zr) 중의 하나 또는 그 이상을 포함할 수 있다. 관통 전극(222)을 구성하는 상기 절연층, 시드층, 및 도전층은 화학기상 증착법(chemical vapor deposition, CVD), 플라즈마 강화 CVD(plasma enhanced CVD, PE-CVD), 고밀도 플라즈마 CVD(high density plasma CVD, HDP-CVD), 스퍼터링, 유기금속 화학기상 증착법(metal organic CVD, MOCVD), 또는 원자층 증착법(atomic layer deposition, ALD)을 이용하여 형성될 수 있다.
도 11에 도시된 것과 같이, 관통 전극(222)의 상부와 하부에는 각각 비아 패드들(223, 224)이 구비되는데, 이들은 관통 전극(222)과 일체로 형성될 수도 있고, 또는 별개로 형성될 수도 있다. 또한, 비아 패드들(223, 224)은 관통 전극(222)과 동일한 물질로 이루어질 수도 있고 상이한 물질로 이루어질 수도 있다.
기판(210)과 제1 반도체 칩(220)은 솔더층(230a)에 의하여 전기적으로 연결될 수 있다. 솔더층(230a)에 대해서는 도 4를 참조하여 상세하게 설명하였으므로 여기서는 상세한 설명을 생략한다.
도 11에 도시된 것 바와 같이, 제1 반도체 칩(220)의 상부에는 제2 반도체 칩(240)이 플립-칩 실장될 수 있다. 제1 반도체 칩(220)의 상부에 제공되는 제2 반도체 칩(240)은 반도체 기판(242)과 그의 활성면에 제공된 접속 패드(244)를 포함할 수 있다. 반도체 기판(242)은 도 5의 반도체 기판(142)를 참조하여 설명한 바와 같은 다양한 물질로 제조될 수 있다. 또한, 반도체 기판(242)의 활성면에는 도 5의 반도체 기판(142)를 참조하여 설명한 바와 같은 다양한 반도체 소자들이 제공될 수 있다.
제1 반도체 칩(220)의 상부면과 제2 반도체 칩(240)의 하부면에는 접속 패드들(226, 244)이 각각 서로 대응되도록 제공될 수 있다. 또한, 서로 대응되는 접속 패드들(226, 244)은 솔더층(230b)에 의하여 전기적으로 연결될 수 있다. 솔더층(230b)에 대해서는 도 4를 참조하여 상세하게 설명하였으므로 여기서는 상세한 설명을 생략한다.
솔더층(230a, 230b) 측벽과, 솔더층(230a, 230b) 주위의 제1 반도체 칩(220) 상부 표면 및 하부 표면 상에 플럭스 잔류층(250a, 250b)이 배치될 수 있다. 플럭스 잔류층(250a, 250b)에 대해서는 도 4를 참조하여 상세하게 설명하였으므로 여기서는 상세한 설명을 생략한다.
기판(210)과 제1 반도체 칩(220)의 사이, 및/또는 제1 반도체 칩(220)과 제2 반도체 칩(240)의 사이에는 언더필층(260a, 260b)이 형성될 수 있다.
도 15는 예시적인 실시예들에 따른 반도체 패키지를 포함하는 메모리 모듈(1000)의 평면도이다.
구체적으로, 메모리 모듈(1000)은 인쇄 회로 기판(1100) 및 복수의 반도체 패키지(1200)를 포함할 수 있다.
복수의 반도체 패키지(1200)는 예시적인 실시예들에 따른 반도체 패키지이거나 이를 포함할 수 있다. 특히, 복수의 반도체 패키지(1200)는 앞에서 설명한 예시적인 실시예들에 따른 반도체 패키지들 중에서 선택되는 적어도 하나의 반도체 패키지를 포함할 수 있다.
예시적인 실시예들에 따른 메모리 모듈(1000)은 인쇄 회로 기판의 한쪽 면에만 복수의 반도체 패키지(1200)를 탑재한 SIMM (single in-lined memory module), 또는 복수의 반도체 패키지(1200)가 양면에 배열된 DIMM (dual in-lined memory module)일 수 있다. 또한, 예시적인 실시예들에 따른 메모리 모듈(1000)은 외부로부터의 신호들을 복수의 반도체 패키지(1200)에 각각 제공하는 AMB (advanced memory buffer)를 갖는 FBDIMM (fully buffered DIMM)일 수 있다.
도 16은 예시적인 실시예들에 따른 반도체 패키지를 포함하는 메모리 카드(2000)의 개략도이다.
구체적으로, 메모리 카드(2000)는 제어기(2100)와 메모리(2200)가 전기적인 신호를 교환하도록 배치될 수 있다. 예를 들면, 제어기(2100)에서 명령을 내리면, 메모리(2200)는 데이터를 전송할 수 있다.
메모리(2200)는 예시적인 실시예들에 따른 반도체 패키지를 포함할 수 있다. 특히, 메모리(2200)는 앞에서 설명한 예시적인 실시예들에 따른 반도체 패키지들 중에서 선택되는 적어도 하나의 반도체 패키지의 구조를 포함할 수 있다.
메모리 카드(2000)는 다양한 종류의 카드, 예를 들어 메모리 스틱 카드 (memory stick card), 스마트 미디어 카드 (smart media card: SM), 씨큐어 디지털 카드 (secure digital card: SD), 미니-씨큐어 디지털 카드 (mini-secure digital card: 미니 SD), 및 멀티미디어 카드 (multimedia card: MMC) 등과 같은 다양한 메모리 카드를 구성할 수 있다.
도 17은 예시적인 실시예들에 따른 반도체 패키지를 포함하는 전자 시스템(3000)의 일 예를 도시한 블록도이다.
도 17을 참조하면, 예시적인 실시예들에 따른 전자 시스템(3000)은 컨트롤러(3110), 입출력 장치(3120, I/O), 메모리 장치(3130, memory device), 인터페이스(3140) 및 버스(3150, bus)를 포함할 수 있다. 상기 컨트롤러(3110), 입출력 장치(3120), 메모리 장치(3130) 및/또는 인터페이스(3140)는 상기 버스(3150)를 통하여 서로 결합될 수 있다. 상기 버스(3150)는 데이터들이 이동되는 통로(path)에 해당한다.
상기 컨트롤러(3110)는 마이크로프로세서, 디지털 신호 프로세스, 마이크로 컨트롤러, 및 이들과 유사한 기능을 수행할 수 있는 논리 소자들 중에서 적어도 하나를 포함할 수 있다. 상기 입출력 장치(3120)는 키패드(keypad), 키보드 및 디스플레이 장치 등을 포함할 수 있다. 상기 메모리 장치(3130)는 데이터 및/또는 커맨드 등을 저장할 수 있다. 상기 메모리 장치(3130)는 상술된 실시예들에 개시된 반도체 패키지들 중에서 적어도 하나를 포함할 수 있다. 또한, 상기 메모리 장치(3130)는 다른 형태의 반도체 메모리 소자(예를 들면, 비휘발성 메모리 장치 및/또는 에스램 장치등)를 더 포함할 수 있다. 상기 인터페이스(3140)는 통신 네트워크로 데이터를 전송하거나 통신 네트워크로부터 데이터를 수신하는 기능을 수행할 수 있다. 상기 인터페이스(3140)는 유선 또는 무선 형태일 수 있다. 예컨대, 상기 인터페이스(3140)는 안테나 또는 유무선 트랜시버 등을 포함할 수 있다. 도시하지 않았지만, 상기 전자 시스템(3000)은 상기 컨트롤러(3110)의 동작을 향상시키기 위한 동작 메모리 소자로서, 고속의 디램 소자 및/또는 에스램 소자 등을 더 포함할 수도 있다.
상기 전자 시스템(3000)은 개인 휴대용 정보 단말기(PDA, personal digital assistant) 포터블 컴퓨터(portable computer), 웹 타블렛(web tablet), 무선 전화기(wireless phone), 모바일 폰(mobile phone), 디지털 뮤직 플레이어(digital music player), 메모리 카드(memory card), 또는 정보를 무선환경에서 송신 및/또는 수신할 수 있는 모든 전자 제품에 적용될 수 있다.
한편, 예시적인 실시예들에 따른 반도체 패키지의 제조 방법은 전술한 바에 한정되는 것은 아니며, 다양한 반도체 패키지의 제조 방법에 적용될 수 있다. 예를 들면, 예시적인 실시예들에 따른 반도체 패키지의 제조 방법은 PoP(Package on Package), Ball grid arrays(BGAs), Chip scale packages(CSPs), Plastic Leaded Chip Carrier(PLCC), Plastic Dual In-Line Package(PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board(COB), Ceramic Dual In-Line Package(CERDIP), Plastic MetricQuad Flat Pack(MQFP), Thin Quad Flatpack(TQFP), Small Outline(SOIC), Shrink Small Outline Package(SSOP), Thin Small Outline(TSOP), Thin Quad Flatpack(TQFP), System In Package(SIP), Multi Chip Package(MCP), Wafer-level Fabricated Package(WFP), Wafer-Level Processed Stack Package(WSP) 등과 같은 패키지들의 제조 방법에 또한 적용될 수 있다.
이상, 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 사상 및 범위 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러가지 변형 및 변경이 가능하다.
100: 반도체 패키지 110: 기판
112A, 112B: 접속 패드 120: 플럭스
120R1, 120R2: 플럭스 잔류층 122: 탄소 나노 튜브
130: 솔더볼 130R, 160: 솔더층
140: 반도체 칩 142: 반도체 기판
144: 접속 패드 152: 언더필층
154: 몰딩재

Claims (10)

  1. 제1 면 상에 접속 패드를 구비하는 기판의 상기 접속 패드 상에 탄소 나노 튜브를 포함하는 플럭스를 도포하는 단계;
    상기 플럭스가 도포된 접속 패드 상에 솔더볼을 배치하는 단계;
    리플로우 공정에 의해 상기 솔더볼로부터 상기 접속 패드에 부착된 솔더층을 형성하는 단계; 및
    상기 리플로우된 솔더볼이 반도체 칩에 구비된 접속 패드와 마주보도록 상기 반도체 칩을 상기 기판 상에 실장하는 단계;를 포함하고,
    상기 플럭스는 약 0.01 wt% 내지 약 1.0 wt%의 탄소 나노 튜브를 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.
  2. 제1항에 있어서,
    상기 플럭스는 친수성 작용기가 부착된 탄소 나노 튜브를 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.
  3. 제2항에 있어서,
    상기 친수성 작용기는 히드록시기, 알콕시기, 니트로기, 시아노기, 아미노기, 아지도기 (azido group), 아미디노기 (amidino group), 히드라지노기 (hydrazino group), 히드라조노기 (hydrazono group), 카르보닐기 (carbonyl group), 카르바밀기 (carbamyl group), 티올기 (thiol group), 알릴아민기(allylamin group), 에테르기(ether group), 에스테르기 (ester group), 카르복실기 (carboxyl group), 카르복실기의 염, 술폰산기 (sulfonic acid group), 트리메톡시실란기(-Si(OCH3)3), 및 트리클로로실란기(-SiCl3)로 구성된 군으로부터 선택된 적어도 하나인 것을 특징으로 하는 반도체 패키지의 제조 방법.
  4. 삭제
  5. 제1항에 있어서,
    상기 플럭스는 약 0.4 wt% 내지 약 0.8 wt%의 탄소 나노 튜브를 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.
  6. 제1항에 있어서,
    상기 탄소 나노 튜브는 단일벽 탄소 나노 튜브, 이중벽 탄소 나노 튜브, 다중벽 탄소 나노 튜브 및 탄소 나노 튜브 로프(rope)로 구성된 군으로부터 선택된 적어도 하나를 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.
  7. 제1항에 있어서,
    상기 플럭스를 도포하는 단계에서, 상기 접속 패드와 상기 플럭스 사이의 접촉각이 60도보다 작은 것을 특징으로 하는 반도체 패키지의 제조 방법.
  8. 제1항에 있어서,
    상기 기판은 인쇄 회로 기판, 연성 인쇄 회로 기판 또는 인터포저인 것을 특징으로 하는 반도체 패키지의 제조 방법.
  9. 제1항에 있어서,
    상기 솔더층을 형성하는 단계 이후에, 상기 솔더볼의 측벽 상에 또는 상기 접속 패드의 상면 상에 상기 탄소 나노 튜브를 포함하는 플럭스 잔류층이 형성되는 것을 특징으로 하는 반도체 패키지의 제조 방법.
  10. 제9항에 있어서,
    상기 솔더층을 형성하는 단계 이후에, 상기 플럭스 잔류층을 제거하기 위한 세정 공정이 더 수행되는 것을 특징으로 하는 반도체 패키지의 제조 방법.
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