201222754 六、發明說明： 【發明所屬之技術領域】 [0001] , _ 尤指一種 本發明係有關於一種封裝基板及其製法 之封裝基板及其製法。 【先前技術】 隨著電子產業的蓬勃發展，電子產品在型態上趨於 輕薄紐小，在功能上則朝高性能、高功能、高速化的研 發方向。因此，為滿足半導體裝置之高積集度（Integ_ ration)以及微型化（Miniaturizati〇n)需求，各種 半導體封裝結構，例如：打線式（Wire b〇nding)或混 合式（hybrid，即覆晶式配合打線式），均具有高密度 及細間距之線路需求。 請參閱第1A、1 A’ 、1B、1C及1D圖，係為習知封裝 基板的示意圖。如第1A圖所示，習知封裝基板係包括： 基板本體10、設於該基板本體1〇上之内層線路11、設於 該基板本體10及内層線路Π上之介電層12、設於該介電 層12上且具有複數打線墊130及覆晶焊墊131之線路層j 3 、設於該介電層12中且電性連接該内層線路丨丨及打線墊 1 3 0之圓形導電盲孔1 4、以及設於該覆晶焊墊1 31及打線 墊130上之防焊層15。 如第1A及1A ’圖所示’該防焊層1 5具有外露全部打 線墊130之一開口 150及對應外露各該覆晶焊墊131之複 數圓形開孔151 ’且於該覆晶焊墊131及打線墊130上形 成表面處理層16 ’以令堆疊晶片組17之底部晶片1 7a以焊 錫凸塊170覆晶結合各該覆晶焊墊131，而頂部晶片i7b 099141313 表單編號A0101 第4頁/共21頁 0992071874-0 201222754 以線（金線或銅線）1 8電性連接各該打線墊1 3 〇。 [0005] [0006] 如第1B圖所示，該導電盲孔1 4之圓形面積小於該打 線塾130之對應該防焊層15表面之面積。 惟，如第1C圖所示’因該導電盲孔丨4為圓形，故該 内層線路11之線寬a需大於該圓形之導電盲孔1 4之直徑d ，使該内層線路11將受限於該導電盲孔之位置，導致 該基板本體1 〇上可使用的面積減少，而不利於細間距佈 線。201222754 VI. Description of the Invention: [Technical Field of the Invention] [0001] _ In particular, the present invention relates to a package substrate and a method of manufacturing the same, and a method of manufacturing the same. [Prior Art] With the rapid development of the electronics industry, electronic products tend to be thinner and lighter in terms of type, and the function is toward high-performance, high-function, high-speed research and development. Therefore, in order to meet the high integration (Integation) and miniaturization requirements of semiconductor devices, various semiconductor package structures, such as wire b〇nding or hybrid (blind) In line with the wire type), they all have high-density and fine-pitch line requirements. Please refer to Figures 1A, 1 A', 1B, 1C and 1D for a schematic view of a conventional package substrate. As shown in FIG. 1A, the conventional package substrate includes: a substrate body 10, an inner layer 11 disposed on the substrate body 1 , a dielectric layer 12 disposed on the substrate body 10 and the inner layer via, and The dielectric layer 12 has a circuit layer j 3 of a plurality of bonding pads 130 and a pad soldering pad 131, a circular layer disposed in the dielectric layer 12 and electrically connected to the inner layer wiring layer and the wire bonding pad 130 a conductive blind via 14 and a solder resist layer 15 disposed on the flip chip 1 31 and the bonding pad 130. As shown in FIGS. 1A and 1A', the solder resist layer 15 has an opening 150 for exposing all of the bonding pads 130 and a plurality of circular openings 151' corresponding to the respective exposed pads 131, and the soldering is performed. A surface treatment layer 16' is formed on the pad 131 and the wire pad 130 such that the bottom wafer 17a of the stacked wafer group 17 is flip-chip bonded with the solder bumps 131 by the solder bumps 170, and the top wafer i7b 099141313 Form No. A0101 No. 4 Page / Total 21 pages 0992071874-0 201222754 Connect each wire pad 1 3 以 with a wire (gold wire or copper wire) 1 8 . [0006] As shown in FIG. 1B, the circular area of the conductive via hole 14 is smaller than the area of the surface of the soldering layer 15 corresponding to the solder resist layer 15. However, as shown in FIG. 1C, because the conductive blind via 4 is circular, the line width a of the inner layer 11 needs to be larger than the diameter d of the circular conductive via 14 such that the inner wiring 11 will Limited by the position of the conductive blind hole, the area available for use on the substrate body 1 is reduced, which is disadvantageous for fine pitch wiring.
[0007] [0008] ❹ [0009] 再者’如第1B及1D圖所示，該圓形導電盲孔14之直 控d亦大於該線路層〗3之線寬，故該線路層】3將受限於該 導電盲孔14之位置，導致該介電層42土可使用的面積減 少，因而不易細間距佈線。 又，若欲不受限於該導電盲孔14而進行細間距佈線 ’則需將各該打線墊130之間的間距縮小（如：3〇um或 更小）’但因而需將各鵁打線墊13〇之面積一同縮小，故 於後續製程中，將不易使金線或銅線接合至該打線墊丨3〇 上’導致生產困難且品質不穩定。 另外’當縮小各該打線墊130之間的間距與各該打線 墊130之面積後’若於該打線墊13〇上形成表面處理層16 時，因該打線墊13〇之間的距離過近及各該打線墊13〇之 面積較小，將導致各該打線墊13〇之間容易產生橋接，因 而發生短路之問題，以致於細間距線路之品質良率降低 [0010] 099141313 因此’如何克服習知技術中上述之種種問題，實已 表單編號A0101 第5頁/共21頁 0992071874-0 201222754 [0011] [0012] [0013] 成目前亟欲解決的課題。 【發明内容】 鑑於上述習知技術之種種缺失，本發明之一目的係 在提供一種利於細間距佈線之封裝基板及其製法。 本發明之又一目的係在提供一種提升產品可靠度之 封裝基板及其製法。 本發明之另一目的係在提供一種避免發生短路之封 裝基板及其製法。 [0014] [0015] 馬這上返及具他目的，本發明揭露一種封裝基板， 係包括：基板本體，係具有内層線路及設於該基板本體 與内層線路上之介電層；線路層，係設於該基板本體之 介電層上，且具有複數打線墊；橢圓形導電盲孔，係設 於該介電層巾以電性連接該内層線路與該線路層；以及 絕緣保護層，係設於該基板本體之介電層及線路層上， 且具有開口，以令各該打線墊外露於該開口中。 本發明《露-種封裝基板之製法，係包括：提供 -基板本體’且該基板切上具有内層料衫於該臭 板本體與内層線路上之介電層；於該基板本體之介電: 上形成線職，該線路層具有複數㈣墊，且於該介; ^中形成電性連接該内層線路與該線路層^圓形導電 孔，於該基板本體之_層及線路層均成絕緣保講 ΓΓ及於該絕緣保護層中形成開σ，以令該打線料 路於該開口中。 [0016] 099141313 月1J 表單編號Α0101 述之封裝基板及其製法中，該導電盲孔之短轴長 第6頁/共21頁 _2071874 201222754 係小於該線路層之線寬。該導電盲孔之橢圓形面積小於 該打線塾之對應該介電層表面之面積。 [0017] 前述之封裝基板及其製法中，該線路層復具有電性 接觸墊，且該絕緣保護層復具有開孔，以令該電性接觸 墊外露於該開孔中。 [0018] 前述之製法中，該開孔係以雷射鑽孔形成之。 [0019] 前述之封裝基板及其製法復包括於該打線墊上形成 表面處理層，且形成該表面處理層之材料係選自由電鍍 鎳/金、化學鑛鎳/金、化鎮浸金（ENIG)、化鎳把浸金 (ENEPIG)、化學鐘錫（Inrnersion Tin)及有機保焊 劑（0SP)所組成之群組中之其中一者。 [0020] 由上可知，本發明之封裝基板及其製法，藉由橢圓 形之導電盲孔，使該内層線路之線寬僅需配合其短軸長 ，當該内層線路縮小線距時，並不受限該導電盲孔，俾 有利於細間距佈線之設計。 [0021] 再者，藉由橢圓形之導電盲孔之短軸長小於該線路 層之線寬，使該線路層不受限於該導電盲孔之位置，不 僅有利於細間距佈線之設計，且當各該打線墊之間的間 距縮小時，不需縮小該打線墊之面積，以易於打線製程 ，有效提升產品之可靠度。 [0022] 另外，當於各該打線墊上形成表面處理層時，各該 打線墊之間不會產生橋接，有效避免發生短路。 【實施方式】 [0023] 以下藉由特定的具體實施例說明本發明之實施方式 099141313 表單編號 A0101 第 7 頁/共 21 頁 0992071874-0 201222754 [0024] [0025] [0026] [0027] [0028] ，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 請參閱第2A至2E圖，係為本發明所揭露之封裝基板 的製法之剖視示意圖。 如第2A圖所示，首先，提供一基板本體20，且該基 板本體20上具有内層線路21及設於該基板本體20與内層 線路21上之介電層22。再者，該基板本體20内部之線路 可依需求佈設多層，並不限於圖式。 如第2B圖所示，於該介電層22中以雷射鑽孔之方式 形成橢圓形盲孔220，以令該内層線路21之部分表面外露 於該橢圓形盲孔220中。 如第2C圖所示，於該介電層22上形成最外層之線路 層23，且該線路層23具有複數打線墊230及複數電性接觸 墊231，又於該橢圓形盲孔220中形成電性連接該内層線 路21及打線墊230之橢圓形導電盲孔24。於本實施例中， 該電性接觸墊231係用以覆晶方式結合晶片。 如第2D及2D’圖所示，於該介電層22及線路層23上 形成例如為防焊層之絕緣保護層25，且該絕緣保護層25 上具有外露全部打線墊230之一開口 250及以雷射鑽孔之 方式形成複數開孔251，以令各該電性接觸墊231對應外 露於各該開孔2 51。 如第2E圖所示，於各該打線墊230及電性接觸墊231 上形成表面處理層2 6，且形成該表面處理層2 6之材料係 選自由電鍍錄/金、化學鍍錄/金、化錄浸金（ENIG)、 099141313 表單編號A0101 第8頁/共21頁 0992071874-0 [0029] 201222754 [0030] [0031] [0032] Ο [0033][0008] [0009] Further, as shown in FIGS. 1B and 1D, the direct control d of the circular conductive blind via 14 is also greater than the line width of the circuit layer 〖3, so the circuit layer] The position of the conductive via 14 will be limited, resulting in a reduction in the area available for the dielectric layer 42 and thus less fine pitch routing. Moreover, if the fine pitch wiring is to be performed without being limited to the conductive blind vias 14 , the pitch between the bonding pads 130 needs to be reduced (for example, 3 〇 um or less), but thus each ramming line needs to be The area of the pad 13 is reduced together, so that in the subsequent process, it will be difficult to bond the gold wire or the copper wire to the wire pad 3', resulting in production difficulties and unstable quality. In addition, when the distance between each of the wire bonding pads 130 and the area of each of the wire bonding pads 130 is reduced, if the surface treatment layer 16 is formed on the wire bonding pads 13, the distance between the wire bonding pads 13 is too close. And the smaller area of each of the wire mats 13〇 will cause bridging between the wire mats 13〇, thus causing a short circuit problem, so that the quality of the fine pitch lines is reduced [0010] 099141313 Therefore how to overcome The above-mentioned various problems in the prior art, the actual form number A0101, page 5 / 21 pages 0992071874-0 201222754 [0011] [0013] [0013] The problem that is currently being solved. SUMMARY OF THE INVENTION In view of the above various deficiencies of the prior art, it is an object of the present invention to provide a package substrate which facilitates fine pitch wiring and a method of fabricating the same. Still another object of the present invention is to provide a package substrate and a method of manufacturing the same that improve product reliability. Another object of the present invention is to provide a package substrate which avoids occurrence of a short circuit and a method of manufacturing the same. [0015] [0015] The present invention discloses a package substrate, comprising: a substrate body having an inner layer line and a dielectric layer disposed on the substrate body and the inner layer line; The utility model is disposed on the dielectric layer of the substrate body and has a plurality of wire bonding pads; the elliptical conductive blind holes are disposed on the dielectric layer to electrically connect the inner layer and the circuit layer; and the insulating protective layer The utility model is disposed on the dielectric layer and the circuit layer of the substrate body, and has an opening so that each of the wire bonding pads is exposed in the opening. The method for manufacturing a dew-type package substrate comprises: providing a substrate body and the substrate is cut with a dielectric layer having an inner layer on the body of the odor board and the inner layer; and dielectric of the substrate body: Forming a line, the circuit layer has a plurality of (four) pads, and is electrically connected to the inner layer line and the circuit layer, and is electrically insulated from the layer and the circuit layer of the substrate body. And maintaining an opening σ in the insulating protective layer to make the wire feeding material in the opening. [0016] 099141313 1J Form No. Α0101 In the package substrate and its manufacturing method, the short axis length of the conductive blind hole is 6 pages/total 21 pages _2071874 201222754 is less than the line width of the circuit layer. The elliptical area of the conductive blind hole is smaller than the area of the surface of the dielectric layer corresponding to the wire. [0017] In the above package substrate and method of manufacturing the same, the circuit layer has an electrical contact pad, and the insulating protection layer has an opening to expose the electrical contact pad in the opening. [0018] In the foregoing method, the opening is formed by laser drilling. [0019] The foregoing package substrate and the manufacturing method thereof are further included on the wire bonding pad to form a surface treatment layer, and the material forming the surface treatment layer is selected from the group consisting of electroplated nickel/gold, chemical mineral nickel/gold, and eutrophic gold (ENIG). One of a group of nickel immersion gold (ENEPIG), chemical tin tin (Inrnersion Tin) and organic solder resist (0SP). [0020] It can be seen from the above that the package substrate of the present invention and the manufacturing method thereof have the elliptical conductive blind holes, so that the line width of the inner layer line only needs to match the short axis length, when the inner layer line reduces the line pitch, and The conductive blind hole is not limited, and the design of the fine pitch wiring is facilitated. [0021] Furthermore, since the short axis length of the elliptical conductive blind hole is smaller than the line width of the circuit layer, the circuit layer is not limited to the position of the conductive blind hole, which is not only advantageous for the design of the fine pitch wiring. Moreover, when the spacing between the wire mats is reduced, the area of the wire mat is not required to be reduced, so that the wire manufacturing process is easy, and the reliability of the product is effectively improved. [0022] In addition, when a surface treatment layer is formed on each of the wire bonding pads, no bridging occurs between the wire bonding pads, thereby effectively preventing short circuit from occurring. [Embodiment] Hereinafter, an embodiment of the present invention will be described by way of a specific embodiment. 099141313 Form No. A0101 Page 7 of 21 0992071874-0 201222754 [0024] [0025] [0027] [0028] Other advantages and utilities of the present invention will be readily apparent to those skilled in the art from this disclosure. 2A to 2E are schematic cross-sectional views showing the manufacturing method of the package substrate disclosed in the present invention. As shown in Fig. 2A, first, a substrate body 20 is provided, and the substrate body 20 has an inner layer line 21 and a dielectric layer 22 disposed on the substrate body 20 and the inner layer line 21. Furthermore, the wiring inside the substrate body 20 can be arranged in multiple layers as required, and is not limited to the drawings. As shown in Fig. 2B, an elliptical blind hole 220 is formed in the dielectric layer 22 by laser drilling so that a part of the surface of the inner layer line 21 is exposed in the elliptical blind hole 220. As shown in FIG. 2C, a circuit layer 23 of the outermost layer is formed on the dielectric layer 22, and the circuit layer 23 has a plurality of wire pads 230 and a plurality of electrical contact pads 231, and is formed in the elliptical blind holes 220. The inner layer line 21 and the elliptical conductive blind hole 24 of the wire pad 230 are electrically connected. In this embodiment, the electrical contact pad 231 is used to bond the wafer in a flip chip manner. As shown in FIGS. 2D and 2D', an insulating protective layer 25 such as a solder resist layer is formed on the dielectric layer 22 and the wiring layer 23, and the insulating protective layer 25 has an opening 250 for exposing all of the bonding pads 230. A plurality of openings 251 are formed in a manner of laser drilling so that each of the electrical contact pads 231 is correspondingly exposed to each of the openings 2 51. As shown in FIG. 2E, a surface treatment layer 2 6 is formed on each of the wire bonding pads 230 and the electrical contact pads 231, and the material forming the surface treatment layer 26 is selected from the group consisting of plating/gold, chemical plating/gold. , ENIG, 099141313 Form No. A0101 Page 8 / 21 pages 0992071874-0 [0029] 201222754 [0030] [0032] [0033]
[0034] [0035] 化鎳纪浸金（ΕΝΕΡI G )、化學链錫（I miners i on Τ i η ) 及有機保焊劑（OSP)所组成之群組中之其中一者。 於後續製程中，可令堆疊晶片組27之底部晶片27a以 焊錫凸塊270覆晶結合各該電性接觸墊231，而頂部晶片 27b以導線（金線或銅線）28電性連接各該打線墊230。 請參閱第3A、3B及3C圖，係顯示該橢圓形導電盲孔 24之不同實施態樣。 如第3A圖所示，因該導電盲孔24為橢圓形，故該内 層線路21之線寬a僅需配合該導電盲孔24之短軸長h，而 無需配合該導電盲孔24之長軸長（相當於習知技術之圓 形直徑），使各該内層線路21之間的間距有效縮小，因 而有效增加該基板本體20上之佈線面積，俾有助於細間 距佈線之設計。 再者，如第3B及3C圖所示，該橢圓形導電盲孔24之 短軸長h係小於該線路層23之線寬b，且該導電盲孔24之 橢圓形面積小於該打線墊230之對應該介電層22表面之面 積。因此，該打線墊230不受限於該橢圓形導電盲孔24之 位置，使該介電層2 2上可運用的面積增加，而利於細間 距佈線之設計，以符合微小化需求。 又，因該線路層23不受限於該導電盲孔24之位置， 故當各該打線墊230之間的間距縮小時，不需縮小各該打 線墊230之面積，因而於後續製程中，金線或銅線易於接 合至各該打線墊230上，俾易於生產且品質穩定。 另外，當縮小各該打線墊230之間的間距時，因無需 099141313 表單編號A0101 第9頁/共21頁 0992071874-0 201222754 [0036] [0037] 縮小各該打線墊230之面積，故於各該打線墊230上形成 表面處理層26時，相較於習知技術，本發明之各該打線 墊230之間不會產生橋接，有效避免發生短路之問題，因 而大幅提高細間距線路之產品品質之良率。 本發明復提供一種封裝基板，係包括：具有内層線 路21及介電層22之基板本體20、設於該基板本體20之介 電層22上之線路層23、設於該介電層22中之橢圓形導電 盲孔24、以及設於該基板本體20之介電層22及線路層23 上之絕緣保護層25。 所述之線路層23具有複數打線墊2 30及複數電性接觸 墊 231。 [0038] [0039] [0040] [0041] 所述之橢圓形導電盲孔24電性連接該内層線路21與 該線路層23。 所述之絕緣保護層25具有外露全部打線墊230之一開 口 250及複數開孔251，以令各該電性接觸墊231對應外 露於各該開孔251。 該橢圓形導電盲孔24之短轴長h係可小於該線路層23 之線寬，且該導電盲孔24之橢圓形面積小於該打線墊230 之對應該介電層22表面之面積，如第3B圖所示。 所述之封裝基板亦可包括表面處理層26，係設於該 打線墊230及電性接觸墊231上，且形成該表面處理層26 之材料係選自由電鑛鎳/金、化學鑛鎳/金、化鎳浸金（ ENIG)、化鎳鈀浸金（ENEPIG)、化學鍍錫（Immersion Tin) 及有機保焊劑 （OSP) 所組成之群組中之其中 099141313 表單編號A0101 第10頁/共21頁 0992071874-0 201222754 [0042] [0043] Ο [0044] ❹ [0045] [0046] 一者。 另外，本發明封裝基板若應用在混合式（hybrid， 即覆晶式配合打線式之堆疊晶片組27)結構時，可同時 完成打線墊及覆晶焊墊，不僅生產性佳且良率品質高、 及成本低。 綜上所述，本發明封裝基板及其製法，藉由橢圓形 之導電盲孔，使該内層線路之線寬僅需配合其短軸長， 故當該内層線路縮小線距時，並不受限該導電盲孔之尺 寸，俾有利於細間距佈線之設計。 再者，藉由橢圓形之導電盲孔之短轴長小於該線路 層之線寬，使該線路層不受限於該導電盲孔之位置，亦 有利於細間距佈線之設計。又，因該線路層不受限於該 導電盲孔之位置，故各該打線墊之間的間距縮小時，不 需縮小各該打線墊之面積，因而易於打線製程，有效提 升產品之可靠度。 另外，當於各該打線墊上形成表面處理層時，各該 線路層之間不會產生橋接，有效避免發生短路。 上述實施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均 可在不違背本發明之精神及範疇下，對上述實施例進行 修改。因此本發明之權利保護範圍，應如後述之申請專 利範圍所列。 【圖式簡單說明】 第1A圖係為習知封裝基板的剖視示意圖；第1A’圖 099141313 表單編號A0101 第11頁/共21頁 0992071874-0 [0047] 201222754 係為第1 A圖之上視示意圖； [0048] 第1B及1C圖係為習知封裝基板的導電盲孔之上視示 意圖， [0049] 第1D圖係為習知封裝基板的導電盲孔之立體示意圖 > [0050] 第2A至2E圖係為本發明封裝基板的製法剖視示意圖 :第2D’圖係為第2D圖的局部上視示意圖； [0051] 第3A及3B圖係為本發明封裝基板的導電盲孔之上視 示意圖；以及 [0052] 第3C圖係為本發明封裝基板的導電盲孔之立體示意 圖。 【主要元件符號說明】 [0053] 10, 20 基板本體 [0054] 11,21 内層線路 [0055] 12, 22 介電層 [0056] 13, 23 線路層 [0057] 1 30, 230 打線墊 [0058] 131 覆晶焊墊 [0059] 14, 24 導電盲孔 [0060] 15 防焊層 [0061] 150,250 開口 表單編號A0101 099141313 第12頁/共21頁 0992071874-0 201222754 ❹ [0062] 151，251 開孔 [0063] 16, 26 表面處理層 [0064] 17, 27 堆疊晶片組 [0065] 17a,27a 底部晶片 [0066] 17b,27b 頂部晶月 [0067] 170,270 焊錫凸塊 [0068] 18, 28 導線 [0069] 220 橢圓形盲孔 [0070] 231 電性接觸墊 [0071] 25 絕緣保護層 [0072] a, b 線寬 [0073] d 直徑 [0074] h 短軸長 099141313 表單編號A0101 第13頁/共21頁 0992071874-0[0035] one of a group consisting of nickel immersion gold (ΕΝΕΡI G ), chemical chain tin (I miners i on Τ i η ), and organic solder resist (OSP). In the subsequent process, the bottom wafer 27a of the stacked wafer group 27 can be flip-chip bonded to each of the electrical contact pads 231 by solder bumps 270, and the top wafers 27b are electrically connected by wires (gold or copper wires) 28. Line pad 230. Referring to Figures 3A, 3B and 3C, different embodiments of the elliptical conductive blind via 24 are shown. As shown in FIG. 3A, since the conductive via 24 is elliptical, the line width a of the inner layer 21 only needs to match the short axis length h of the conductive via 24 without the length of the conductive via 24 The axial length (corresponding to the circular diameter of the prior art) effectively reduces the spacing between the inner layer lines 21, thereby effectively increasing the wiring area on the substrate body 20, and contributing to the design of the fine pitch wiring. Furthermore, as shown in FIGS. 3B and 3C, the short axis length h of the elliptical conductive blind via 24 is smaller than the line width b of the circuit layer 23, and the elliptical area of the conductive blind via 24 is smaller than the bonding pad 230. This corresponds to the area of the surface of the dielectric layer 22. Therefore, the wire pad 230 is not limited to the position of the elliptical conductive blind hole 24, so that the area available for the dielectric layer 22 is increased, which facilitates the design of the fine pitch wiring to meet the miniaturization requirement. Moreover, since the circuit layer 23 is not limited to the position of the conductive blind hole 24, when the spacing between the wire bonding pads 230 is reduced, the area of each of the wire bonding pads 230 does not need to be reduced, and thus, in the subsequent process, The gold wire or the copper wire is easily joined to each of the wire bonding pads 230, and is easy to produce and stable in quality. In addition, when the spacing between the wire pads 230 is reduced, it is not necessary for 099141313 Form No. A0101 Page 9 / Total 21 Pages 0992071874-0 201222754 [0037] [0037] The area of each of the wire bonding pads 230 is reduced, so When the surface treatment layer 26 is formed on the wire bonding pad 230, no bridging occurs between the wire bonding pads 230 of the present invention, which effectively avoids the problem of short circuit, thereby greatly improving the product quality of the fine pitch circuit. Yield. The present invention provides a package substrate, comprising: a substrate body 20 having an inner layer line 21 and a dielectric layer 22, and a circuit layer 23 disposed on the dielectric layer 22 of the substrate body 20, and disposed in the dielectric layer 22. An elliptical conductive blind via 24 and an insulating protective layer 25 disposed on the dielectric layer 22 and the wiring layer 23 of the substrate body 20. The circuit layer 23 has a plurality of wire pads 2 30 and a plurality of electrical contact pads 231. [0040] [0041] The elliptical conductive blind via 24 is electrically connected to the inner layer line 21 and the wiring layer 23. The insulating protective layer 25 has an opening 250 and a plurality of openings 251 for exposing all of the bonding pads 230 so that the electrical contact pads 231 are correspondingly exposed to the openings 251. The short axis length h of the elliptical conductive blind hole 24 can be smaller than the line width of the circuit layer 23, and the elliptical area of the conductive blind hole 24 is smaller than the area of the surface of the dielectric pad 22 corresponding to the wire pad 230, such as Figure 3B shows. The package substrate may further include a surface treatment layer 26 disposed on the wire bonding pad 230 and the electrical contact pad 231, and the material forming the surface treatment layer 26 is selected from the group consisting of electro-mineral nickel/gold, chemical mineral nickel/ Among the groups consisting of gold, nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG), electroless tin plating (Immersion Tin) and organic solder resist (OSP), 099141313 Form No. A0101 Page 10 / Total 21 pages 0992071874-0 201222754 [0043] [0044] [0046] [0046] One. In addition, if the package substrate of the present invention is applied to a hybrid (that is, a flip-chip type of stacked wafer group 27) structure, the wire pad and the flip chip can be simultaneously completed, which is not only good in productivity but also high in yield quality. And low cost. In summary, the package substrate of the present invention and the method for manufacturing the same are characterized in that the line width of the inner layer line only needs to match the short axis length by the elliptical conductive blind hole, so when the inner layer line is reduced in line pitch, it is not Limiting the size of the conductive blind hole, it is advantageous for the design of fine pitch wiring. Moreover, the short axis length of the elliptical conductive via hole is smaller than the line width of the circuit layer, so that the circuit layer is not limited to the position of the conductive blind hole, and the design of the fine pitch wiring is also facilitated. Moreover, since the circuit layer is not limited to the position of the conductive blind hole, when the spacing between the wire bonding pads is reduced, the area of each wire bonding pad is not required to be reduced, thereby facilitating the wire bonding process and effectively improving the reliability of the product. . Further, when the surface treatment layer is formed on each of the wire bonding pads, bridging is not generated between the respective wiring layers, and short-circuiting is effectively prevented. The above-described embodiments are intended to illustrate the principles of the invention and its advantages, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the application patents which will be described later. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a cross-sectional view of a conventional package substrate; FIG. 1A' FIG. 099141313 Form No. A0101 Page 11 of 21 0992071874-0 [0047] 201222754 is above the 1st A picture 1B and 1C are top views of conductive blind holes of a conventional package substrate, and FIG. 1D is a perspective view of a conductive blind hole of a conventional package substrate. [0050] 2A to 2E are schematic cross-sectional views showing a method of manufacturing a package substrate of the present invention: FIG. 2D is a partial top view of FIG. 2D; [0051] FIGS. 3A and 3B are conductive blind holes of the package substrate of the present invention. FIG. 3C is a perspective view showing a conductive blind hole of the package substrate of the present invention. [Main component symbol description] [0053] 10, 20 substrate body [0054] 11, 21 inner layer [0055] 12, 22 dielectric layer [0056] 13, 23 circuit layer [0057] 1 30, 230 wire pad [0058 ] 131 Foiled solder pad [0059] 14, 24 Conductive blind hole [0060] 15 Solder mask [0061] 150,250 Open form number A0101 099141313 Page 12 of 21 0992071874-0 201222754 ❹ [0062] 151,251 On Hole [0063] 16, 26 surface treatment layer [0064] 17, 27 stacked wafer set [0065] 17a, 27a bottom wafer [0066] 17b, 27b top crystal [0067] 170, 270 solder bump [0068] 18, 28 wire 220 elliptical blind hole [0070] 231 electrical contact pad [0071] 25 insulation protective layer [0072] a, b line width [0073] d diameter [0074] h short axis length 099141313 form number A0101 page 13 / Total 21 pages 0992071874-0