KR102380442B1 - Memory device and operation method thereof - Google Patents

Abstract

[Objective] The present invention provides a memory device and an operating method thereof.
[Solution] The memory device includes an input/output data latch circuit and a bit line sense amplifier circuit. The input/output data latch circuit is coupled between the main input/output line pair and the local input/output line pair. The local input/output line pair is coupled to a plurality of bit line pairs through a bit line sense amplifier circuit. When the memory device performs either a read operation or a write operation, the memory device executes a two-step operation to input or output data of a selected bit line pair among these bit line pairs, and the selected bit line pair is connected to the local input/output line pair in only one stage operation of the two-stage operation, and in another stage operation of the two-stage operation, the data of the selected bit line pair latched in the input/output data latch circuit is the main input/output transmitted to the line pair.

Description

MEMORY DEVICE AND OPERATION METHOD THEREOF

The present invention relates to a memory device, and more particularly, to a memory device capable of improving access speed and a method of operating the same.

Since the operating speed of dynamic RAM (Dynamic Random Access Memory, DRAM) is limited by its own access mechanism, how to improve the access speed of DRAM, in particular, Error-correcting code (ECC) For DRAMs with circuits, it is always an important research subject. Although the ECC circuit can improve data reliability, it causes an increase in the delay time (Column-to-Column 　 Delay, tCCD) between column addresses of DRAM. Accordingly, how to provide a memory device having high reliability and high speed has become an important task in the development of current memory technology.

The present invention provides a memory device having a pipeline structure and capable of shortening an operation cycle of the memory device and an operating method thereof.

An embodiment of the present invention provides a memory device including an input/output data latch circuit and a bitline sense amplifier circuit. The input/output data latch circuit is coupled between the main input/output line pair and the local input/output line pair. The local input/output line pair is coupled to a plurality of bit line pairs through a bit line sense amplifier circuit. When the memory device performs either a read operation or a write operation, the memory device executes a two-step operation to input or output data of a selected bitline pair among these bitline pairs, and the selected bitline pair is connected to the local input/output line pair only in one stage operation of the two-stage operation, and in another stage operation of the two-stage operation, the data of the selected bit line pair latched by the input/output data latch circuit is the main transmitted to the input/output line.

An embodiment of the present invention provides a method of operating a memory device comprising the following steps. In the first stage operation, the data of the selected bit line pair held in the sense amplifier data latch is latched in the input/output data latch circuit. In the second stage operation, data of the selected bit line pair latched by the input/output data latch circuit is transmitted to the main input/output line pair, and a read operation is performed.

Based on the above, the present invention proposes a memory device and an operating method thereof. An input/output data latch circuit is provided between the main input/output line pair and the local input/output line pair to latch data to be written or read. By temporarily storing the target data between the main input/output line pair and the local input/output line pair, the access operation can be divided into the first stage operation and the second stage operation, thereby achieving a pipelined structure for the access operation. .

1 is a circuit explanatory diagram of a memory device according to an embodiment of the present invention.
[ Fig. 2A ] A timing diagram of a read operation according to an embodiment of the present invention.
[Fig. 2B] A timing diagram of a write operation according to an embodiment of the present invention.
3 is a timing diagram of a write/read synchronization operation according to an embodiment of the present invention.
4 is a circuit explanatory diagram of a memory device according to another embodiment of the present invention.
5 is a timing diagram of a masked-write operation according to an embodiment of the present invention.
6 is a timing diagram of a write mask operation according to another embodiment of the present invention.
[Fig. 7] Fig. 7 is a flowchart of a method of operating a memory device according to an embodiment of the present invention.
8 is a flowchart of a method of operating a memory device according to another embodiment of the present invention.

In order to make it easy to understand the said characteristic and advantage of this invention, embodiment is given as an example, and according to drawing, the detail is demonstrated as follows.

In order to make this invention easy to understand, embodiment is given below as an example, and let this invention be an example which can be implemented based on it. In addition, within the scope possible, elements/members/steps using the same reference numerals in the drawings and embodiments indicate the same or similar components.

In the following embodiments, a memory device and an operation method thereof of the present invention will be described using DRAM as an example. However, the present invention does not limit the type of memory device.

1 is a circuit explanatory diagram of a memory device according to an embodiment of the present invention. Referring to FIG. 1 , the memory device 100 includes at least an input/output data latch circuit 110 , a bit line sense amplifier circuit BLSA, and a memory cell array MA. The memory cell array MA is constituted by a plurality of memory cells arranged in an array. These memory cells connect a plurality of word lines and a plurality of bit line pairs. For simplicity of explanation, the memory cell array MA of FIG. 1 shows only two memory cells MC1 and MC2 on the word line WL as an example. The memory cell MC1 is coupled to the bit line pair BL1. The bit line pair BL1 includes a bit line BLT1 and a complementary bit line BLB1. The memory cell MC2 is coupled to the bit line pair BL2. The bit line pair BL2 includes a bit line BLT2 and a complementary bit line BLB2.

The input/output data latch circuit 110 is coupled between a main input/output line pair MIO and a local input/output line pair LIO. The main input/output line pair MIO includes a main input/output line MIOT and a complementary main input/output line MIOB. The local input/output line pair LIO includes a local input/output line LIOT and a complementary local input/output line LIOB. The input/output data latch circuit 110 is used to latch data written to the memory cell array MA or data of the memory cell array MA outputted from the local input/output line pair LIO.

The local input/output line pair LIO is coupled to a plurality of bit line pairs, for example, the bit line pairs BL1 and BL2 through the bit line sense amplifier circuit BLSA. The column selection signal CSLn controls the switch TC to conduct the local input/output line pair LIO and the bit line pair BLn, where n is an integer. The bit line sense amplifier circuit BLSA is used to sense and amplify the potential signal of the bit line pair. The bit line sense amplifier circuit BLSA further includes a plurality of sense amplifier data latches SADL. These sense amplifier data latches SADL are connected between these bit line pairs and are used to hold data of these bit line pairs.

The main sensing driving circuit 120 is coupled to the main input/output line pair MIO and is controlled by the driving enable signal DR_EN and the sensor enable signal SA_EN. When the driving enable signal DR_EN validates the main sensing driving circuit 120 , the memory device 100 performs a write operation on the memory cell array MA. The main input/output line pair MIO receives write data from the main sensing driving circuit 120 , and the local input/output line pair LIO writes write data from the main input/output line pair MIO through the input/output data latch circuit 110 . Receive data and send write data to the sense amplifier data latch SADL of the corresponding bitline pair. When the sensor enable signal SA_EN validates the main sensing driving circuit 120 , the memory device 100 performs a read operation on the memory cell array MA. The read data stored in the sense amplifier data latch SADL is transmitted to the input/output data latch circuit 110 through the local input/output line pair LIO, and is latched by the input/output data latch circuit 110 . Next, read data is transmitted from the input/output data latch circuit 110 to the main input/output line pair MIO. Finally, the main sensing driving circuit 120 senses read data of the main input/output line pair MIO.

In other words, in the present embodiment, when the memory device performs either a read operation or a write operation, the memory device 100 performs a two-step operation, Input or output data. For example, since the memory cell to be accessed is the memory cell MC1, the bit line pair is selected as the bit line pair BL1. The selected bit line pair BL1 is connected to the local input/output line pair LIO only in one stage operation of the two-step operation. In another stage operation of the two-step operation, data of the selected bit line pair BL1 latched by the input/output data latch circuit 110 is transmitted to the main input/output line pair MIO.

More specifically, the above-described two-step operation includes a first stage operation and a second stage operation. When the memory device 100 executes a read operation on the memory cell MC1 , in the first stage operation, the data of the selected bit line pair BL1 is transferred from the corresponding sense amplifier data latch SADL to the input/output data latch circuit ( 110 , and in the second stage operation, the data latched by the input/output data latch circuit 110 is transferred to the main input/output line pair MIO. When the memory device 100 executes the write operation in the memory cell MC1 , in the first stage operation, write data is latched from the main input/output line pair MIO to the input/output data latch circuit 110 , and in the second stage operation In , the write data latched by the input/output data latch circuit 110 is transmitted to the sense amplifier data latch SADL corresponding to the selected bit line pair BL1.

Hereinafter, the details of implementation are further described.

Fig. 2A is a timing diagram of a read operation according to an embodiment of the present invention, and Fig. 2B is a timing diagram of a write operation according to an embodiment of the present invention. Reference is also made to FIGS. 1-2B together. In the present embodiment, the input/output data latch circuit 110 includes a read data latch circuit RDL and a write data latch circuit WDL. The read data latch circuit RDL is coupled between the main input/output line pair MIO and the local input/output line pair LIO, and is controlled by the read input signal RDIN and the read output signal RDOUT. The write data latch circuit WDL is coupled between the main input/output line pair MIO and the local input/output line pair LIO, and is controlled by the write input signal WDIN and the write output signal WDOUT.

Referring to FIG. 2A , when the memory device 100 executes the read operation READ, each time the read operation READ is performed in two stages, a first stage operation ST1 and a second stage operation ST2 . is divided In the first stage operation ST1 , the column selection signal CSL1 selectively conducts the bit line pair BL1 and the local input/output line pair LIO. The sense amplifier data latch SADL between the bit line BLT1 and the complementary bit line BLB1 transmits the read data RD to the local input/output line pair LIO. In addition, the read input signal RDIN is received from the local input/output line pair LIO to the read data latch circuit RDL to latch the read data RD. In the second stage operation ST2, the read output signal RDOUT transmits the read data RD latched by the read data latch circuit RDL to the main input/output line pair MIO, and the sensor enable signal RDOUT SA_EN) causes the main sensing driving circuit 120 to sense the read data RD of the main input/output line pair MIO.

It should be particularly described, in the second stage operation ST2 of the read operation READ, the column selection signal CSL1 is already in an invalid state, and the bit line pair BL1 and the local input/output line pair LIO is non-conductive. In the read operation READ of the present embodiment, the length of time of the first stage operation ST1 is the same as that of the second stage operation ST2, the length of time is tCOR, and the length of time tCOR is , equal to the column selection period of the memory device 100 . The column selection period is the pulse period at which each column is initiated.

Referring to FIG. 2B , when the memory device 100 executes the write operation WRITE, each time the write operation WRITE is similarly performed in two stages of the first stage operation ST1 and the second stage operation ST2. divided into stages. In the first stage operation ST1 , the driving enable signal DR_EN is in an effective state, and the main sensing driving circuit 120 transmits the write data WD to the main input/output line pair MIO. The write input signal WDIN receives the write data WD from the main input/output line pair MIO to the write data latch circuit WDL, and latches the write data WD. In the second stage operation ST2 , the write output signal WDOUT outputs the write data WD latched by the write data latch circuit WDL to the local input/output line pair LIO. In addition, the column selection signal CSL1 conducts the bit line pair BL1 to the local input/output line pair LIO. The write data WD is transmitted to the sense amplifier data latch SADL corresponding to the bit line pair BL1. Finally, the write data WD is written into the memory cell MC1 .

It should be particularly described, in the first stage operation ST1 of the write operation WRITE, the column selection signal CSL1 is in an invalid state, and the bit line pair BL1 is connected to the local input/output line pair LIO. not connected In the write operation WRITE of the present embodiment, the length of time of the first stage operation ST1 is the same as that of the second stage operation ST2, the length of time is tCOW, and the length of time tCOW is , equal to the column selection period of the memory device 100 .

In the present embodiment, regardless of whether the write operation WRITE or the read operation READ is a two-step operation, the length of time for each stage operation is the same. The times of the first stage operation ST1 and the second stage operation ST2 of the read operation READ are both tCOR. The times of the first stage operation ST1 and the second stage operation ST2 of the write operation WRITE are both tCOW. In addition, the length of time of the two-step operation of the present embodiment is the same in the write operation WRITE and the read operation READ. The length of time tCOR of the read operation READ is equal to the length of time tCOW of the write operation WRITE. Here, the length of time of each stage operation is any one column selection period.

The write data WD and the read data RD are latched through the input/output data latch circuit 110 , and the memory device 100 , regardless of whether the write operation WRITE or the read operation READ is performed, is 2 Since stepwise operation can be employed, the memory device 100 has a pipeline structure and can execute a plurality of commands in parallel.

3 is a timing diagram of a read-while-write (RWW) operation according to an embodiment of the present invention. Referring to FIG. 3 , when the memory device 100 executes the write/read synchronization operation RWW, each time the write/read synchronization operation RWW is performed between the first stage operation ST1 and the second stage operation ST2. It is divided into two stages. In the first stage operation ST1 , the driving enable signal DR_EN is in an effective state, and the main sensing driving circuit 120 transmits the write data WD to the main input/output line pair MIO. The write input signal WDIN validates the write data latch circuit WDL, receives the write data WD from the main input/output line pair MIO, and latches the write data WD. At the same time, the read input signal RDIN activates the read data latch circuit RDL to receive and latch the read data RD from the local input/output line pair LIO. In the first stage operation ST1 , the column selection signal CSL1 selectively conducts the bit line pair BL1 to the local input/output line pair LIO. The read data RD is transmitted from the sense amplifier data latch SADL connected to the bit line pair BL1 to the read data latch circuit RDL.

In other words, in the first stage operation ST1 , the memory device 100 inputs the write data WD to the write data latch circuit WDL and reads the read data RD from the memory cell MC1 . Inputs to the read data latch circuit RDL can be executed in parallel.

In the second stage operation ST2 , the write output signal WDOUT controls the write data latch circuit WDL to output the latched write data WD to the local input/output line pair LIO. At the same time, the read output signal RDOUT controls the read data latch circuit RDL to output the read data RD to the main input/output line pair MIO, and the memory cell MC1 to the main sensing driving circuit 120 . The read data RD is sensed from In addition, the column selection signal CSL2 selectively conducts the bit line pair BL2 to the local input/output line pair LIO. The write data WD is transmitted to the sense amplifier data latch SADL corresponding to the bit line pair BL2. The write data WD is written into the memory cell MC2 .

Simply put, in the second stage operation ST2 , the memory device 100 outputs the write data WD from the write data latch circuit WDL and the memory cell MC1 from the read data latch circuit RDL. ) of the read data RD can be outputted in parallel. The memory device 100 may write the write data WD into the memory cell MC2 while sensing the read data of the memory cell MC1 in the second stage operation ST2 .

In the present embodiment, the length of time of the first stage operation ST1 of the write/read synchronization operation RWW is the same as the length of the time of the second stage operation ST2, and may be one column selection period. For example, the length of time of the write/read synchronization operation RWW may be equal to twice the length of time tCOR (2*tCOR) or twice the length of time tCOW (2*tCOW). can

4 is a circuit explanatory diagram of a memory device according to another embodiment of the present invention. Referring to FIG. 4 , memory device 200 is similar to memory device 100 and may implement the various embodiments described above. The difference between the memory device 200 and the memory device 100 is that the memory device 200 further includes an error correction (ECC) circuit 210 . The ECC circuit 210 is used to perform error checking and correction on data from the selected bit line pair.

5 is a timing diagram of a masked-write operation according to an embodiment of the present invention. Memory device 200 may implement the embodiment of FIG. 5 , reference is made to FIG. 5 in conjunction with FIG. 4 . The memory device 200 receives the first mask write command MWR1 and the second mask write command MWR2 in order, and performs a read-modify-write operation 301 and a read-modify operation. - Execute the write operation 302 correspondingly. In the process of executing the read-correction-write operation 301 or 302 , after the read operation READ is executed, the ECC circuit 210 executes an error check and correction step 310 on the read data. In addition, before executing the write operation WRITE, the memory device 200 also needs to execute the data transmission step 320 and the parity data generation step 330 . For details of implementation of the read operation READ and the write operation WRITE, reference may be made to the description of the above embodiment. Starting from the mask write command MWR1 or MWR2 and for the first time after time T0 has elapsed, the memory device 200 starts executing the data transmission step 320 and the parity data generation step 330 . In the parity data generation step 330, for example, read data and written data are combined to generate parity.

In the present embodiment, the cycle lengths of the read operation READ and the write operation WRITE are the same, and both are the length of time T. The length of time T is equal to two column selection periods, for example 2*tCOR or 2*tCOW. With respect to the read operation READ and the write operation WRITE, the length of time of each stage operation of the two-step operation may be the same as any one column selection period. When the memory device 200 executes the read-modify-write operation 301 or 302 on the selected bitline pair, the start time for performing the read operation READ of the selected bitline pair is the write operation of the selected bitline pair. At least twice as fast as the length of time T than the start time of performing the operation WRITE, that is, the memory device 200, after the read operation READ starts to execute, at least four column selection periods have elapsed, Then, execution of the write operation WRITE is started. In other words, in the read-modify-write operation of the present embodiment, the time point at which the read operation READ starts is earlier than the time point at which the write operation WRITE starts by m*T, where m is an integer of 2 or more am.

It should be noted that the time interval tCCD between the first mask write command MWR1 and the second mask write command MWR2 can be shortened to n*T, where n is an integer greater than or equal to 1 . That is, since the delay time between the minimum column addresses according to the present embodiment can be shortened by at least two column selection cycles, the operation speed of the memory device 200 can be improved.

6 is a timing diagram of a write mask operation according to an embodiment of the present invention. The memory device 200 can implement the embodiment of FIG. 6 , reference is made to FIG. 6 in conjunction with FIG. 4 . The memory device 200 sequentially receives the first mask write command MWR1 and the second mask write command MWR2 , and performs a read-modify-write operation 401 and a read-modify-write operation 402 . act accordingly. In the process of executing the read-correction-write operation 401 or 402 , after the read operation READ is executed, the ECC circuit 210 executes an error check and correction step 310 on the read data. Similar to the flow of the embodiment of FIG. 5 , the memory device 200 executes the data transmission step 320 and the parity data generation step 330 before data is written back to the memory cell.

In the present embodiment, the memory device 200 has a read/write function. The memory device 200 executes a write/read synchronization operation RWW after step 330 . When the memory device 200 executes an operation for writing data back to the memory cell in the read-modify-write operation 401 , it simultaneously writes data from the memory cell in the read-modify-write operation 402 . A read operation can be executed. In this way, the access speed of the memory device 200 can be accelerated. For details of the implementation of the write/read synchronization operation RWW, the read operation READ, and the write operation WRITE, the above embodiments may be referred to.

In the present embodiment, the period lengths of the write/read synchronization operation RWW, the read operation READ, and the write operation WRITE are the same, and all of them are the length of time T. Here, the length of time T is equal to two column selection periods, for example 2*tCOR or 2*tCOW. When the memory device 200 executes the read-modify-write operation 401 or 402 on the selected bit line, the time point of the start of the read operation READ is the write read synchronization operation RWW or the write operation WRITE. faster than m*T, where m is an integer greater than or equal to 2.

It should be mentioned that the time interval tCCD between the first mask write command MWR1 and the second mask write command MWR2 is also shortened to m*T. That is, the delay time between the minimum column addresses according to the present embodiment can be shortened by at least four column selection cycles.

7 is a flowchart of a method of operating a memory device according to an embodiment of the present invention. Referring to FIG. 7 , the operation method of FIG. 7 is applied to the read operation READ of the embodiments of FIGS. 1 to 6 . Hereinafter, the operation method of FIG. 7 is demonstrated using the member code|symbol of the said embodiment.

In step S710 , data of the selected bit line pair stored in the sense amplifier data latch SADL in the first stage operation ST1 is latched in the input/output data latch circuit 110 . In step S720, the data of the selected bit line pair latched by the input/output data latch circuit 110 in the second stage operation ST2 is transmitted to the main input/output line pair MIO, and the read operation READ is performed. run

8 is a flowchart of a method of operating a memory device according to another embodiment of the present invention. Referring to FIG. 8 , the operation method of FIG. 8 is applied to the write operation WRITE of the embodiments of FIGS. 1 to 6 . Hereinafter, the operation method of FIG. 8 is demonstrated using the reference numerals of the above embodiments.

In step S810 , the write data of the main input/output line pair MIO is latched in the input/output data latch circuit 110 in the first stage operation ST1 . In step S820, the write data latched by the input/output data latch circuit 110 in the second stage operation ST2 is transmitted to the sense amplifier data latch SADL corresponding to the selected bit line pair to perform the write operation. run

Each of the steps in Figs. 7 and 8 is described in detail in the embodiment of Figs. 1 to 6, and since those skilled in the art can obtain sufficient suggestions and teachings from the above description, they will not be described again here.

In summary, in the memory device of the present invention, an access operation is performed by an input/output data latch circuit provided between a main input/output line pair and a local input/output line pair, and data is transferred from a sense amplifier data latch of a bit line pair to an input/output data latch circuit. It is divided into two stages: transmitting and transmitting data latched in the input/output data latch circuit to the main input/output line pair. Accordingly, the memory device has a pipeline structure and can execute a plurality of commands in parallel. Accordingly, the access speed of the memory device is improved. The embodiment of the present invention also suggests an operation direction applied to the above-mentioned memory device.

Although the present invention has disclosed the embodiment as described above, it is not intended to limit the present invention, and those skilled in the art can make some changes and modifications within the range that does not deviate from the spirit of the present invention, and therefore the protection of the present invention The scope is based on the claims described below.

100: memory device
110: input/output data latch circuit
120: main sensing driving circuit
210: ECC circuit
301, 302, 401, 402: read-modify-write operations
310: error check correction step
320: data transmission step
330: parity data generation step
BLSA: Bitline Sense Amplifier Circuit
BL1, BL2: bit line pair
BLT1, BLBT2: bit line
BLB1, BLB2: Complementary bit line
CSL1, CSL2: column select signal
DR_EN: drive enable signal
LIO: local input/output line pair
LIOT: local input/output line
LIOB: Complementary local input/output line
MA: memory cell array
MIO: main input/output wire pair
MIOT: main input/output line
MIOB: Complementary main input/output line
MC1, MC2: memory cells
MWR1: first mask write command
MWR2: second mask write command
M: integer
RD: read data
RDIN: read input signal
RDOUT: read output signal
RDL: read data latch circuit
READ: read operation
RWW: Write/Read Synchronous Operation
SADL: Sense Amplifier Data Latch
SA_EN: sensor enable signal
ST1: first stage operation
ST2: second stage operation
TC: switch
T0: time
tCCD: time interval
tCOR, tCOW, T: length of time
WL: word line
WD: write data
WDL: Write Data Latch Circuit
WDIN: Write input signal
WDOUT: write output signal
WRITE: write operation
S710, S720, S810, S820: Steps of the operation method of the memory device

Claims (14)

an input/output data latch circuit coupled between the main input/output line pair and the local input/output line pair;
bitline sense amplifier circuit
including,
the local input/output line pair is coupled to a plurality of bit line pairs through the bit line sense amplifier circuit;
When the memory device performs either a read operation or a write operation, the memory device performs a two-step operation to input or output data of a selected bit line pair among the plurality of bit line pairs;
The selected bit line pair is conductive to the local input/output line pair only in one stage operation of the two-step operation, and in another stage operation of the two-step operation, the selected bit line pair latched to the input/output data latch circuit The data of the bit line pair is transmitted to the main input/output line pair,
The bit line sense amplifier circuit comprises:
a plurality of sense amplifier data latches for holding data of the plurality of bitline pairs
including,
The two-step operation includes a first stage operation and a second stage operation,
When the memory device performs a read operation, in the first stage operation, the data of the selected bit line pair is latched from the corresponding sense amplifier data latch to the input/output data latch circuit, and in the second stage operation , data latched in the input/output data latch circuit is transmitted to the main input/output line pair;
When the memory device executes a write operation, in the first stage operation, write data is latched from the main input/output line pair to the input/output data latch circuit, and in the second stage operation, write data is latched into the input/output data latch circuit. the write data is transmitted to the sense amplifier data latch corresponding to the selected bit line pair.
memory device. According to claim 1,
The input/output data latch circuit comprises:
a read data latch circuit coupled between the main input/output line pair and the local input/output line pair;
A write data latch circuit coupled between the main input/output line pair and the local input/output line pair
including,
When the memory device executes the read operation,
In the first stage operation, the read data latch circuit receives the data of the selected bit line pair, and in the second stage operation, the data latched in the read data latch circuit is transmitted to the main input/output line pair; ,
When the memory device executes the write operation,
In the first stage operation, the write data latch circuit receives write data, and in the second stage operation, the write data latched by the write data latch circuit is transferred to the sense amplifier data latch corresponding to the selected bit line pair. being sent
memory device. According to claim 1,
When the memory device executes a write/read synchronous operation,
The write-in-read cycle includes two column selection cycles,
the input/output data latch circuit includes a read data latch circuit and a write data latch circuit;
In the first column selection period of the write-time read period, the read data latch circuit receives data of a first bit line pair from a first sense amplifier data latch, and the write data latch circuit includes: receive write data from the line pair;
In the second column selection period of the read-on-write period, the write data latch circuit provides the write data to a second sense amplifier data latch, and the read data latch circuit includes: the first bit line pair transmits the data of the main input/output line pair,
The first bit line pair and the second bit line pair are two of the plurality of bit line pairs, and the first sense amplifier data latch and the second sense amplifier data latch include the first bit line pair and the second bit line pair, respectively. Preserving the data of the second bit line pair
memory device. 4. The method of claim 3,
An error correction circuit for performing error checking and correction on data of the selected bit line pair
further comprising,
The memory device is
performing the write read read synchronization operation in the process of performing the read-modify-write operation;
The start time of the read operation performed on the selected bit line pair is,
at least two times faster than a start time of the write/read synchronization operation or the write operation performed on the selected bit line pair by the read-in-write period
memory device. 5. The method of claim 4,
The delay between column addresses is
at least one read-time read cycle, which is an integer multiple of the write-time read cycle
memory device. According to claim 1,
An error correction circuit for performing error checking and correction on data of the selected bit line pair
further comprising,
The period lengths of the read operation and the write operation are both equal to two column selection periods, and the length of time of each of the stage operations of the two-step operation is equal to the column selection period of any one;
When the memory device executes the read-modify-write operation on the selected bit line pair, the start time of the read operation on the selected bit line pair is:
at least four column selection periods faster than the start time of the write operation to execute on the selected bitline pair
memory device. 7. The method of claim 6,
The delay between column addresses is
is equal to at least two cycles of the column selection period and is an integer multiple of two periods of the column selection period
memory device. According to claim 1,
The length of time of each stage operation of the two-step operation is the same
memory device. 9. The method of claim 8,
The length of time of the two-step operation is the same in the write operation and the read operation
memory device. When the memory device executes a read operation, in a first stage operation, the data of the selected bit line pair held by the sense amplifier data latch is latched into the input/output data latch circuit, and in the second stage operation, the data of the input/output data latch circuit is latched. transmitting data of the selected bit line pair to a main input/output line pair;
When the memory device executes the write operation, in the first stage operation, the write data of the main input/output line pair is latched to the input/output data latch circuit, and in the second stage operation, the write data of the main input/output line pair is latched to the input/output data latch circuit. sending write data to the sense amplifier data latch corresponding to the selected bitline pair;
A method of operating a memory device comprising a. 11. The method of claim 10,
When the memory device executes the read operation,
In the first stage operation, the read data latch circuit of the input/output data latch circuit receives the data of the selected bit line pair, and in the second stage operation, the data latched by the read data latch circuit is transferred to the main input/output line pair sending to the
When the memory device executes the write operation,
In the first stage operation, the write data latch circuit of the input/output data latch circuit receives the write data, and in the second stage operation, the write data latched by the write data latch circuit is transferred to the selected bit line pair. transmitted to the corresponding sense amplifier data latch.
An operation method further comprising a. 12. The method of claim 11,
A read period during write in a write read synchronization operation includes two column selection periods,
The method of operation is
In the first column selection period of the write-on-read period, the read data latch circuit receives data of a first bit line pair from a first sense amplifier data latch, and the write data latch circuit includes: receiving the write data from a line pair;
In the second column selection period of the read-on-write period, the write data latch circuit provides the write data to a second sense amplifier data latch, and the read data latch circuit includes: the first bit line pair transmitting the data of the main input/output line pair
further comprising,
wherein the first sense amplifier data latch and the second sense amplifier data latch hold data of the first bit line pair and the second bit line pair, respectively.
how it works. delete delete

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