CN113870919A - Memory device and operation method thereof - Google Patents

Abstract

The invention provides a memory device and an operation method thereof. The memory device comprises an input/output data latch circuit and a bit line sensing amplifying circuit. The input/output data latch circuit is coupled between the primary input/output line pair and the local input/output line pair. The local input/output line pairs are coupled to the bit line pairs through the bit line sense amplifying circuit. The memory device performs a two-phase operation to input or output data of a selected bit line pair of the bit line pairs, wherein the selected bit line pair is turned on with the local input-output line pair only in one phase operation of the two-phase operation, and data of the selected bit line pair latched in the input-output data latch circuit is transferred to the master input-output line pair in another phase operation of the two-phase operation.

Description

Memory device and operation method thereof

Technical Field

The present invention relates to a memory device, and more particularly, to a memory device capable of improving an access speed and an operating method thereof.

Background

The operation speed of a Dynamic Random Access Memory (DRAM) is limited by its Access mechanism, and therefore how to increase the Access speed of the DRAM has been an important research topic, especially for a DRAM having an Error Correction Code (ECC) circuit. Although the ECC circuit can improve the reliability of data, it will cause the Column address to Column address Delay time (tCCD) of DRAM to increase. Therefore, how to provide a memory device with high reliability and high speed becomes an important issue in the development of memory technology.

Disclosure of Invention

The invention provides a memory device and an operating method thereof, which have a pipeline (pipeline) structure and can shorten the operating period of the memory device.

An embodiment of the invention provides a memory device, which includes an input/output data latch circuit and a bit line sense amplifier circuit. The input/output data latch circuit is coupled between a main input/output line pair and a local input/output line pair. The local input/output line pair is coupled to a plurality of bit line pairs through a bit line sensing amplifying circuit. When the memory device performs a read operation or a write operation, the memory device performs a two-phase operation to input or output data of a selected bit line pair of the bit line pairs, wherein the selected bit line pair is turned on with the local input-output line pair only in one of the two-phase operation, and, in another one of the two-phase operation, data of the selected bit line pair latched in the input-output data latch circuit is transferred to the main input-output line pair.

An embodiment of the present invention provides a method for operating a memory device, including the following steps. In the first stage operation, the data of the selected bit line pair stored by the sense amplifying data latch is latched to an input-output data latch circuit. In the second stage operation, data latched in the selected bit line pair of the input-output data latch circuit is transferred to a main input-output line pair to perform a read operation.

Based on the foregoing, the invention provides a memory device and an operating method thereof. An input/output data latch circuit is provided between the pair of main input/output lines and the pair of area input/output lines to latch data to be written or read. The target data is temporarily stored between the main input-output line pair and the local input-output line pair, so that the access operation can be divided into a first stage operation and a second stage operation, and the access operation has a pipeline structure.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a circuit diagram of a memory device according to an embodiment of the invention;

FIG. 2A is a timing diagram of a read operation according to an embodiment of the invention;

FIG. 2B is a timing diagram of a write operation according to an embodiment of the invention;

FIG. 3 is a timing diagram of a read-write-synchronous (RWW) operation in accordance with one embodiment of the present invention;

FIG. 4 is a circuit diagram of a memory device according to another embodiment of the invention;

FIG. 5 is a timing diagram of a mask-write operation in accordance with one embodiment of the present invention;

FIG. 6 is a timing diagram of a write mask operation according to one embodiment of the invention;

FIG. 7 is a flow chart of a method of operation of a memory device according to an embodiment of the invention;

FIG. 8 is a flow chart of a method of operating a memory device according to another embodiment of the invention.

Description of the reference numerals

100 memory device

110 input/output data latch circuit

120 main sensing and driving circuit

ECC circuit (210)

301. 302, 401, 402 read-modify-write operation

Error checking and correcting step 310

320 data transmission step

330 step of generating verification data

BLSA bit line sense amplifier circuit

BL1, BL2 bit line pair

BLT1, BLT2 bit line

BLB1, BLB2 complementary bit lines

CSL1, CSL2 column select signals

DR _ EN drive enable signal

LIO regional input-output line pair

LIOT local input and output line

LIOB complementary region input-output line

Memory cell array

MIO main input/output line pair

MIOT main input-output line

MIOB complementary main input-output line

MC1, MC2 memory cell

MWR1 first write mask instruction

MWR2 second writemask instruction

m is an integer

RD read data

RDIN reading input signal

RDOUT read output signal

RDL read data latch circuit

READ operation

RWW read-write synchronous operation

SADL sense amplified data latch

SA _ EN sense enable signal

ST1 first stage operation

ST2 second stage operation

TC switch

T0 time

tCCD time interval

tCOR, tCOW, T time length

WD writing data

WDL write data latch circuit

WDIN write input signal

WDOUT write output signal

WL word line

WRITE operation

S710, S720, S810, S820 steps of method for operating memory device

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

In the following embodiments, a Dynamic Random Access Memory (DRAM) will be used as an implementation example to describe the Memory device and the operation method thereof of the present invention. However, the invention is not limited to the type of memory device.

Fig. 1 is a circuit diagram of a memory device according to an embodiment of the invention. Referring to fig. 1, the memory device 100 at least includes an input/output data latch circuit 110, a bit line sense amplifier circuit BLSA, and a memory cell array MA. The memory cell array MA is composed of a plurality of memory cells arranged in an array. The memory cells connect a plurality of word lines with a plurality of bit line pairs. For simplicity of illustration, the memory cell array MA of FIG. 1 only shows 2 memory cells MC1 and MC2 on a word line WL as an example. Memory cell MC1 is coupled to bit line pair BL 1. The bit line pair BL1 includes a bit line BLT1 and a complementary bit line BLB 1. Memory cell MC2 is coupled to bit line pair BL 2. The bit line pair BL2 includes a bit line BLT2 and a complementary bit line BLB 2.

The input/output data latch circuit 110 is coupled between the pair of main input/output lines MIO and the pair of local input/output lines LIO. The pair of main input-output lines MIO includes a main input-output line MIOT and a complementary main input-output line MIOB. The local input-output line pair LIO includes a local input-output line LIOT and a complementary local input-output line LIOB. The input/output data latch circuit 110 latches data to be written into the memory cell array MA or data of the memory cell array MA output from the local input/output line pair LIO.

The local input/output line pair LIO is coupled to a plurality of bit line pairs, such as bit line pair BL1, BL2, through a bit line sense amplifier circuit BLSA. The column selection signal CSLn controls the switch TC to turn on the local i/o line pair LIO and the bit line pair BLn, where n is an integer. The bit line sense amplifying circuit BLSA is used to sense and amplify a potential signal on the bit line pair. The bit line sense amplifying circuit BLSA further includes a plurality of sense amplifying data latches SADL. The sense amplifier data latches SADL are connected between the bit line pairs for storing data of the bit line pairs.

The main sensing and driving circuit 120 is coupled to the main input/output line pair MIO and controlled by a driving enable signal DR _ EN and a sensing enable signal SA _ EN. When the driving enable signal DR _ EN enables the main sensing and driving circuit 120, the memory device 100 performs a write operation on the memory cell array MA. The main input/output line pair MIO receives the write data from the main sensing and driving circuit 120, and the local input/output line pair LIO receives the write data from the main input/output line pair MIO through the input/output data latch circuit 110, and then transfers the write data to the sense amplifier data latch SADL on the corresponding bit line pair. When the sense enable signal SA _ EN enables the main sense and drive circuit 120, the memory device 100 performs a read operation on the memory cell array MA. The read data stored in the sense amplifier data latch SADL is transferred to the input/output data latch circuit 110 through the local input/output line pair LIO and latched in the input/output data latch circuit 110. Then, the read data is transferred to the pair of main input-output lines MIO by the input-output data latch circuit 110. Finally, the main sensing and driving circuit 120 senses the read data of the main input/output line pair MIO.

In short, in the present embodiment, when the memory device 100 performs a read operation or a write operation, the memory device 100 performs a two-phase operation to input or output data of a selected bit line pair of the bit line pairs. For example, the memory cell to be accessed is memory cell MC1, so the selected bit line pair is bit line pair BL 1. The selected bit line pair BL1 is turned on with the local input-output line pair LIO only in one of the two-phase operations. In the other of the two-stage operations, the data of the selected bit line pair BL1 latched in the input-output data latch circuit 110 is transferred to the primary input-output line pair MIO.

More specifically, the two-stage operation includes a first stage operation and a second stage operation. When the memory device 100 is to perform a read operation on the memory cell MC1, data of the selected bit line pair BL1 is latched from the corresponding sense amplified data latch SADL to the input-output data latch circuit 110 in the first stage operation, and the data latched in the input-output data latch circuit 110 is transferred to the main input-output line pair MIO in the second stage operation. When the memory device 100 is to perform a write operation on the memory cell MC1, in the first-stage operation, write data is latched from the main input-output line pair MIO to the input-output data latch circuit 110, and in the second-stage operation, the write data latched in the input-output data latch circuit 110 is transferred to the sense amplified data latch SADL corresponding to the selected bit line pair BL 1.

Implementation details will be further explained below.

FIG. 2A is a timing diagram of a read operation according to an embodiment of the invention, and FIG. 2B is a timing diagram of a write operation according to an embodiment of the invention. Please refer to fig. 1 to fig. 2B together. In the present embodiment, the input/output data latch circuit 110 includes a read data latch circuit RDL and a write data latch circuit WDL. The read data latch circuit RDL is coupled between the main input/output line pair MIO and the local input/output line pair LIO, and is controlled by a read input signal RDIN and a read output signal RDOUT. The write data latch circuit WDL is coupled between the pair of main input/output lines MIO and the pair of local input/output lines LIO, and is controlled by the write input signal WDIN and the write output signal WDOUT.

Referring to fig. 2A, when the memory device 100 performs a READ operation READ, each READ operation READ is divided into two phases: the first stage operation ST1 and the second stage operation ST 2. In the first stage operation ST1, the column selection signal CSL1 selects to turn on the bit line pair BL1 and the local input-output line pair LIO. The sense amplified data latch SADL between the bit line BLT1 and the complementary bit line BLB1 transfers the read data RD to the local input-output line pair LIO. In addition, the read input signal RDIN causes the read data latch circuit RDL to receive and latch the read data RD from the area input output line pair LIO. In the second stage operation ST2, the read output signal RDOUT allows the read data RD latched in the read data latch circuit RDL to be transferred to the pair of main input and output lines MIO, and the sense enable signal SA _ EN allows the main sensing and driving circuit 120 to sense the read data RD on the pair of main input and output lines MIO.

Specifically, in the second stage operation ST2 of the READ operation READ, the column selection signal CSL1 is already in the disabled state, and the bit line pair BL1 disconnects the local input-output line pair LIO. In the READ operation READ of the present embodiment, the time length of the first stage operation ST1 is the same as that of the second stage operation ST2, the time lengths are both tCOR, and the time length tCOR is the same as the column selection period of the memory device 100. The column selection period is a pulse period in which each column (column) is activated.

Referring to fig. 2B, when the memory device 100 performs a WRITE operation WRITE, each WRITE operation WRITE is also divided into two phases: the first stage operation ST1 and the second stage operation ST 2. In the first stage operation ST1, the driving enable signal DR _ EN is in an enabled state, and the main sensing and driving circuit 120 transfers the write data WD to the pair of main input-output lines MIO. The write input signal WDIN causes the write data latch circuit WDL to receive the write data WD from the main input-output line pair MIO and latch it. In the second stage operation ST2, the write output signal WDOUT causes the write data latch circuit WDL to output the latched write data WD to the local input-output line pair LIO. In addition, the column selection signal CSL1 turns on the bit line pair BL1 and inputs the output line pair LIO. The write data WD is transferred to the sense amplified data latch SADL corresponding to the bit line pair BL 1. Finally, write data WD is written to memory cell MC 1.

Specifically, in the first-stage operation ST1 of the WRITE operation WRITE, the column selection signal CSL1 is in a disabled state, and the bit line pair BL1 is not yet connected to the local input-output line pair LIO. In the WRITE operation WRITE of the present embodiment, the time length of the first stage operation ST1 is the same as that of the second stage operation ST2, the time lengths are tCOW, and the time length tCOW is the same as the column selection period of the memory device 100.

In this embodiment, the time duration of each phase operation is the same regardless of whether the WRITE operation WRITE or the READ operation READ is a two-phase operation. The times of the first stage operation ST1 and the second stage operation ST2 of the READ operation READ are both tCOR. The times of the first stage operation ST1 and the second stage operation ST2 of the WRITE operation WRITE are both tCOW. In addition, the time length of the two-phase operation of the present embodiment is the same in the WRITE operation WRITE as in the READ operation READ. The time length tCOR of the READ operation READ is the same as the time length tCOW of the WRITE operation WRITE. Here, the time length of each phase operation is one column selection period.

Since the WRITE data WD and the READ data RD are latched by the i/o data latch circuit 110, the memory device 100 can perform a two-stage operation regardless of whether the WRITE operation WRITE or the READ operation READ is performed, so that the memory device 100 has a pipeline architecture and can execute a plurality of instructions in parallel.

FIG. 3 is a timing diagram of a read-write-while-write (RWW) operation according to an embodiment of the invention. Referring to fig. 3, when the memory device 100 executes the read-write synchronous operation RWW, each time the read-write synchronous operation RWW is divided into two phases: the first stage operation ST1 and the second stage operation ST 2. In the first stage operation ST1, the driving enable signal DR _ EN is in an enabled state, and the main sensing and driving circuit 120 transfers the write data WD to the pair of main input-output lines MIO. The write input signal WDIN enables the write data latch circuit WDL to receive the write data WD from the main input-output line pair MIO and latch the write data WD. Meanwhile, the read input signal RDIN enables the read data latch circuit RDL to receive and latch the read data RD from the area input output line pair LIO. In the first stage operation ST1, the column selection signal CSL1 selects the bit line pair BL1 to turn on the local input-output line pair LIO. The read data RD is transferred from the sense amplified data latch SADL connected to the bit line pair BL1 to the read data latch circuit RDL.

In short, in the first stage operation ST1, the memory device 100 may perform the input of the write data WD to the write data latch circuit WDL and the input of the read data RD of the memory cell MC1 to the read data latch circuit RDL in parallel.

In the second stage operation ST2, the write output signal WDOUT controls the write data latch circuit WDL to output the latched write data WD to the local input-output line pair LIO. Meanwhile, the read output signal RDOUT controls the read data latch circuit RDL to output the read data RD to the main input-output line pair MIO, so that the main sensing and driving circuit 120 senses the read data RD from the memory cell MC 1. In addition, the column selection signal CSL2 selects the bit line pair BL2 to turn on the local input-output line pair LIO. The write data WD is transferred to the sense amplified data latch SADL corresponding to the bit line pair BL 2. Write data WD is written to memory cell MC 2.

In short, in the second stage operation ST2, the memory device 100 may perform outputting the write data WD from the write data latch circuit WDL and outputting the read data RD of the memory cell MC1 from the read data latch circuit RDL in parallel. In the second stage operation ST2, the memory device 100 can write the write data WD to the memory cell MC2 while sensing the read data of the memory cell MC 1.

In the present embodiment, the time length of the first stage operation ST1 of the read-write synchronizing operation RWW is the same as the time length of the second stage operation ST2, and may be one column selection period. For example, the time length of the read-write synchronization operation RWW may be equal to 2 times the time length tCOR (2 × tCOR) or 2 times the time length tCOW (2 × tCOW).

FIG. 4 is a circuit diagram of a memory device according to another embodiment of the invention. Referring to FIG. 4, the memory device 200 is similar to the memory device 100 and can implement the various embodiments described above. Memory device 200 differs from memory device 100 in that memory device 200 also includes error correction (ECC) circuitry 210. The ECC circuit 210 is used to perform error checking and correction on data from a selected bit line pair.

FIG. 5 is a timing diagram of a mask-write operation in accordance with one embodiment of the present invention. The memory device 200 can implement the embodiment of fig. 5, please refer to fig. 5 in conjunction with fig. 4. The memory device 200 receives the first write mask instruction MWR1 and the second write mask instruction MWR2 sequentially, and performs a read-modify-write (read-modify-write) operation 301 and a read-modify-write (read-modify-write) operation 302 correspondingly. During the READ-modify- write operation 301 or 302, after the READ operation READ is performed, the ECC circuit 210 performs an error checking and correcting step 310 on the READ data. Before performing the WRITE operation WRITE, the memory device 200 also needs to perform a data transfer step 320 and a parity generation step 330. The details of the READ operation READ and the WRITE operation WRITE can be referred to the description of the above embodiments. The memory device 200 does not start the data transfer 320 and the check data generation 330 until the time T0 elapses since the write mask command (MWR1 or MWR2) is received. In the generate check data step 330, for example, the write data and the read data are combined to generate check data.

In this embodiment, the cycle length of the READ operation READ is the same as that of the WRITE operation WRITE, and is the time length T. The time duration T here is equal to two column selection periods, for example 2 × tCOR 2 × tCOW. For the READ operation READ and the WRITE operation WRITE, the time length of each phase operation of the two-phase operation may be equal to one column selection period. When the memory device 200 performs the READ-modify- WRITE operation 301 or 302 on the selected bit line, the start time of the READ operation READ applied to the selected bit line pair is at least 2 times earlier than the start time of the WRITE operation WRITE applied to the selected bit line pair, that is, the memory device 200 starts the WRITE operation WRITE again through at least 4 column selection periods after the READ operation READ starts. In other words, in the READ-modify-WRITE operation of the present embodiment, the time point when the READ operation READ starts is m × T earlier than the time point when the WRITE operation WRITE starts, where m is an integer greater than or equal to 2.

It should be noted that the time interval tCCD between the first write mask instruction MWR1 and the second write mask instruction MWR2 can be shortened to n × T, where n is an integer greater than or equal to 1. That is, the delay time from the minimum column address to the column address in the present embodiment can be shortened to at least two column selection cycles, thereby increasing the operation speed of the memory device 200.

FIG. 6 is a timing diagram of a write mask operation according to an embodiment of the invention. The memory device 200 can implement the embodiment of fig. 6, please refer to fig. 6 in conjunction with fig. 4. The memory device 200 receives the first write mask instruction MWR1 and the second write mask instruction MWR2 sequentially, and performs a read-modify-write (read-modify-write) operation 401 and a read-modify-write (read-modify-write) operation 402 correspondingly. During the READ-modify- write operation 401 or 402, after the READ operation READ is performed, the ECC circuit 210 performs an error checking and correcting step 310 on the READ data. Similar to the process of the embodiment of FIG. 5, the memory device 200 performs a data transfer step 320 and a check data generation step 330 before the data is written back to the memory cells.

In the present embodiment, the memory device 200 has a read-write synchronization function. Memory device 200 may perform a read-write synchronous operation RWW after step 330. The memory device 200 is capable of performing the act of reading data from a memory cell in a read-modify-write operation 402 while performing the act of writing data back to the memory cell in a read-modify-write operation 401. In this way, the access speed of the memory device 200 can be accelerated. The details of the WRITE-READ synchronous operation RWW, the READ operation READ, and the WRITE operation WRITE can be found in the above embodiments.

In this embodiment, the cycle lengths of the READ-WRITE synchronous operation RWW, the READ operation READ, and the WRITE operation WRITE are all the same time length T. The time duration T here is equal to two column selection periods, for example 2 × tCOR 2 × tCOW. When the memory device 200 performs the READ-modify- WRITE operation 401 or 402 on the selected bit line, the READ operation READ starts m × T earlier than the READ-WRITE synchronous operation RWW or the WRITE operation WRITE, where m is an integer greater than or equal to 2.

It should be noted that the time interval tCCD between the first write mask instruction MWR1 and the second write mask instruction MWR2 is also shortened to m T. That is, the delay time from the minimum column address to the column address of the present embodiment can be shortened to at least 4 column selection periods.

FIG. 7 is a flow chart of a method of operating a memory device according to an embodiment of the invention. Referring to fig. 7, the operation method of fig. 7 is suitable for the READ operation READ of the embodiments of fig. 1 to 6. The operation of fig. 7 is described below with reference to the above embodiments.

In step S710, in the first stage operation ST1, the data of the selected bit line pair stored by the sense amplified data latch SADL is latched to the input-output data latch circuit 110. In step S720, in the second stage operation ST2, the data latched in the selected bit line pair of the input-output data latch circuit 110 is transferred to the main input-output line pair MIO to perform the READ operation READ.

FIG. 8 is a flow chart of a method of operating a memory device according to another embodiment of the invention. Referring to fig. 8, the operation method of fig. 7 is applied to the WRITE operation WRITE of the embodiments of fig. 1 to 6. The following description of the operation method of fig. 8 is provided with reference symbols of the above embodiments.

In step S810, in the first stage operation ST1, the write data of the pair of primary input-output lines MIO is latched to the input-output data latch circuit 110. In step S820, in the second stage operation ST2, the write data latched in the input-output data latch circuit 110 is transferred to the sense amplified data latch SADL corresponding to the selected bit line pair to perform a write operation.

Each step of fig. 7 and 8 has been described in detail in the embodiments of fig. 1 to 6, and those skilled in the art can make sufficient suggestions and teachings from the above description, and will not be repeated herein.

In summary, the memory device of the present invention divides the access operation into two stages by the input/output data latch circuit disposed between the main input/output line pair and the local input/output line pair: data is transferred from the sense amplified data latch on the bit line pair to the input-output data latch circuit and the data latched in the input-output data latch circuit is transferred to the master input-output line pair. The memory device may have a pipelined architecture to execute multiple instructions in parallel. Thereby improving the access speed of the memory device. An embodiment of the invention also provides an operating method applicable to the memory device.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (14)

1. A memory device, comprising:

an input/output data latch circuit coupled between the primary input/output line pair and the local input/output line pair; and

a bit line sense amplifying circuit, wherein the pair of local input and output lines is coupled to a plurality of bit line pairs through the bit line sense amplifying circuit,

wherein, when the memory device performs a read operation or a write operation, the memory device performs a two-phase operation to input or output data of a selected one of the bit line pairs,

wherein the selected bit line pair is turned on with the area input output line pair only in one of the two-phase operations, and data of the selected bit line pair latched in the input-output data latch circuit is transferred to the main input output line pair in the other one of the two-phase operations.

2. The memory device according to claim 1, wherein the bit line sense amplifying circuit comprises:

a plurality of sense amplified data latches to store data of the bit line pairs,

wherein the two-stage operation comprises a first stage operation and a second stage operation,

wherein, when the memory device performs the read operation, in the first stage operation, data of the selected bit line pair is latched from the corresponding sense amplifying data latch to the input-output data latch circuit, and in the second stage operation, data latched in the input-output data latch circuit is transferred to the main input-output line pair,

wherein, when the memory device performs the write operation, in the first-phase operation, write data is latched from the pair of primary input-output lines to the input-output data latch circuit, and in the second-phase operation, the write data latched in the input-output data latch circuit is transferred to the sense amplified data latch corresponding to the selected bit line pair.

3. The memory device according to claim 2, wherein the input-output data latch circuit includes:

a read data latch circuit coupled between the pair of primary input-output lines and the pair of local input-output lines, wherein when the memory device performs the read operation, the read data latch circuit receives data of the selected bit line pair in the first phase operation, and the data latched in the read data latch circuit is transferred to the pair of primary input-output lines in the second phase operation; and

a write data latch circuit coupled between the pair of primary input-output lines and the pair of local input-output lines, wherein when the memory device performs the write operation, the write data latch circuit receives the write data in the first phase operation, and the write data latched in the write data latch circuit is transferred to the sense amplified data latch corresponding to the selected bit line pair in the second phase operation.

4. The memory device according to claim 1, wherein the read-write synchronizing period includes two column selection periods and the input-output data latch circuit includes a read data latch circuit and a write data latch circuit when the memory device performs the read-write synchronizing operation,

wherein, in a first one of the column selection periods in the read-write synchronization period, the read data latch circuit receives data of a first bit line pair from a first sense amplifying data latch, and the write data latch circuit receives write data from the main input-output line pair, an

In a second one of the column selection periods in the read-write synchronization period, the write data latch circuit supplies the write data to a second sense amplifying data latch, and the read data latch circuit transfers data of the first bit line pair to the primary input-output line pair,

the first bit line pair and the second bit line pair are two of the bit line pair, and the first sense amplification data latch and the second sense amplification data latch respectively store data of the first bit line pair and the second bit line pair.

5. The memory device of claim 4, further comprising:

an error correction circuit for performing error checking and correction on data from the selected bit line pair,

wherein the memory device performs the read-write synchronization operation in a process of performing a read-modify-write operation, wherein a start time of the read operation applied to the selected bit line pair is earlier than a start time of the read-write synchronization operation or the write operation applied to the selected bit line pair by at least two read-write synchronization cycles.

6. The memory device of claim 5, wherein a column address to column address delay time is at least one of the read-write synchronization periods and is an integer multiple of the read-write synchronization period.

7. The memory device of claim 1, further comprising:

an error correction circuit for performing error checking and correction on data from the selected bit line pair,

wherein the period length of the read operation and the write operation is equal to two column selection periods, the time length of each of the phase operations of the two-phase operation is equal to one column selection period,

wherein, when the memory device performs a read-modify-write operation on the selected bit line, a start time of the read operation applied to the selected bit line pair is earlier than a start time of the write operation applied to the selected bit line pair by at least 4 column selection periods.

8. The memory device of claim 7, wherein a delay time from a column address to a column address is at least the two column selection periods and is an integer multiple of the two column selection periods.

9. The memory device of claim 1, wherein each of said phase operations of said two-phase operation has a same time duration.

10. The memory device of claim 9, wherein a time length of the two-stage operation is the same in the write operation as in the read operation.

11. A method of operating a memory device, comprising:

in the first stage operation, the data of the selected bit line pair stored by the sense amplifying data latch is latched to the input and output data latch circuit; and

in the second stage operation, data latched in the selected bit line pair of the input-output data latch circuit is transferred to a main input-output line pair to perform a read operation.

12. The method of operation of claim 11, further comprising:

in the first-stage operation, the write data of the pair of primary input-output lines is latched to the input-output data latch circuit; and

in the second stage operation, the write data latched in the input-output data latch circuit is transferred to the sense amplified data latch corresponding to the selected bit line pair to perform a write operation.

13. The method of claim 12, wherein the step of performing the read operation and the write operation further comprises:

when the memory device performs the read operation, in the first phase operation, data of the selected bit line pair is received by a read data latch circuit in the input-output data latch circuits, and in the second phase operation, the data latched in the read data latch circuit is transferred to the main input-output line pair; and

when the memory device performs the write operation, in the first-stage operation, the write data is received by a write data latch circuit among the input-output data latch circuits, and in the second-stage operation, the write data latched in the write data latch circuit is transferred to the sense amplified data latch corresponding to the selected bit line pair.

14. The method of operation of claim 13, further comprising:

the read-write synchronization period of the read-write synchronization operation comprises two column selection periods;

receiving, by the read data latch circuit, data of a first bit line pair from a first sense amplifier data latch, and receiving, by the write data latch circuit, the write data from the main input-output line pair, in a first one of the column selection periods in the read-write synchronization period; and

in a second one of the column selection periods in the read-write synchronization period, the write data is supplied to a second sense amplifying data latch by the write data latch circuit, and the read data latch circuit transfers data of the first bit line pair to the primary input-output line pair,

the first bit line pair and the second bit line pair are two of the bit line pair, and the first sense amplification data latch and the second sense amplification data latch respectively store data of the first bit line pair and the second bit line pair.

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