TWI736326B - Memory device and operation method thereof - Google Patents

Abstract

The invention provides a memory device and an operation method thereof. The memory device includes an input/output data latch circuit and a bit line sensing amplifier circuit. The input/output data latch circuit is coupled between a main input/output line pair and a local input/output line pair. A plurality of bit line pairs is coupled to the local input/output line pair through the bit line sensing amplifier circuit. The memory device performs a two-stage operation to input or output the data of the selected bit line pair among the bit line pairs, wherein the selected bit line pair connects to the local input/output line pair only during one stage operation of the two-stage operation, and the data of the selected bit line pair latched in the input/output data latch circuit is transmitted to the main input/output line pair during the other stage operation of the two-stage operation.

Description

Memory device and its operation method

The present invention relates to a memory device, and more particularly to a memory device capable of improving access speed and an operating method thereof.

The operating speed of Dynamic Random Access Memory (DRAM) is limited by its own access mechanism. Therefore, how to improve the access speed of DRAM has always been an important research topic, especially for error-correction (Error- correcting code (ECC) circuit for DRAM. Although the ECC circuit can improve the reliability of the data, it will increase the Column-to-Column Delay (tCCD) from the row address to the row address of the DRAM. Therefore, how to propose a memory device with high reliability and high speed has become an important issue in the development of current memory technology.

The present invention provides a memory device and an operation method thereof, which has a pipeline structure and can shorten the operation period of the memory device.

An embodiment of the present invention provides a memory device including an input/output data latch circuit and a bit line sense amplifier circuit. The input/output data latch circuit is coupled between a main input/output line pair and an area input/output line pair. The regional input and output line pairs are coupled to a plurality of bit line pairs through a bit line sensing and amplifying circuit. When the memory device performs a read operation or a write operation, the memory device performs a two-stage operation to input or output the data of the selected bit line pair among these bit line pairs. Among them, the selected bit line pair is only in the two-stage type. In one stage of the operation, it is connected to the regional I/O line pair, and in the other stage of the two-stage operation, the data of the selected line pair latched in the input/output data latch circuit is transmitted to Main input and output wire pair.

An embodiment of the present invention provides an operating method of a memory device, including the following steps. In the first stage of operation, the data of the selected line pair stored in the sense amplification data latch is latched to an input/output data latch circuit. In the second stage of operation, the data latched in the selected line pair of the input/output data latch circuit is transmitted to a main input/output line pair to perform a read operation.

Based on the above, the present invention provides a memory device and an operating method thereof. An input/output data latch circuit is provided between the main input/output line pair and the area input/output line pair to latch the data to be written or read. By temporarily storing the target data between the main I/O line pair and the area I/O line pair, the access action can be divided into the first stage operation and the second stage operation, so that the access operation has a pipeline structure.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

In order to make the present invention more comprehensible, the following embodiments are specifically cited as examples on which the present invention can be implemented. In addition, wherever possible, elements/components/steps with the same reference numbers in the drawings and embodiments represent the same or similar components.

In the following embodiments, a dynamic random access memory (Dynamic Random Access Memory, DRAM) will be used as an implementation example to illustrate the memory device and its operation method of the present invention. However, the present invention does not limit the type of the memory device.

FIG. 1 is a schematic circuit diagram of a memory device according to an embodiment of the invention. 1, the memory device 100 at least includes an input/output data latch circuit 110, a bit line sense amplifier circuit BLSA, and a memory cell array MA. The memory cell array MA is composed of a plurality of memory cells arranged in an array. These memory cells connect multiple word lines and multiple bit line pairs. To simplify the description, the memory cell array MA of FIG. 1 only shows the two memory cells MC1 and MC2 on the word line WL as an example. The memory cell MC1 is coupled to the bit line pair BL1. The bit line pair BL1 includes a bit line BLT1 and a complementary bit line BLB1. The memory cell MC2 is coupled to the bit line pair BL2. The bit line pair BL2 includes a bit line BLT2 and a complementary bit line BLB2.

The input/output data latch circuit 110 is coupled between the main input/output line pair MIO and the area input/output line pair LIO. The main input and output line pair MIO includes a main input and output line MIOT and a complementary main input and output line MIOB. The regional I/O line pair LIO includes a regional I/O line LIOT and a complementary regional I/O line LIOB. The input/output data latch circuit 110 is used for latching the data to be written into the memory cell array MA or the data of the memory cell array MA output from the regional input/output line to the LIO.

The regional input/output line pair LIO is coupled to a plurality of bit line pairs, such as the bit line pair BL1 and BL2, through the bit line sense amplifier circuit BLSA. The row selection signal CSLn controls the switch TC to turn on the regional input/output line pair LIO and the bit line pair BLn, where n is an integer. The bit line sense amplifier circuit BLSA is used to sense and amplify the potential signal on the bit line pair. The bit line sense amplifier circuit BLSA also includes a plurality of sense amplifier data latches SADL. These sense amplified data latches SADL are connected between these bit line pairs, and are used to store the data of these bit line pairs.

The main sensing and driving circuit 120 is coupled to the main input/output line pair MIO, and is controlled by the driving enable signal DR_EN and the sensing enable signal SA_EN. When the driving enable signal DR_EN enables the main sensing and driving circuit 120, the memory device 100 performs a write operation on the memory cell array MA. The main input and output line pair MIO receives the written data from the main sensing and driving circuit 120, and the regional input and output line pair LIO receives the written data from the main input and output line pair MIO through the input and output data latch circuit 110, and then writes The data is transmitted to the sense amplified data latch SADL on the corresponding bit line pair. When the sensing enable signal SA_EN enables the main sensing and driving circuit 120, the memory device 100 performs a read operation on the memory cell array MA. The read data stored in the sense amplified data latch SADL is transmitted to the input/output data latch circuit 110 via the regional input/output line pair LIO, and is latched in the input/output data latch circuit 110. Then, the input/output data latch circuit 110 transmits the read data to the main input/output line pair MIO. Finally, the main sensing and driving circuit 120 senses the data read by the main input/output line to the MIO.

In short, in this embodiment, when the memory device 100 performs a read operation or a write operation, the memory device 100 performs a two-stage operation to input or output a selected bit line of these bit line pairs Right information. For example, the memory cell to be accessed is the memory cell MC1, so the bit line pair BL1 is selected as the bit line pair. The selected positioning line pair BL1 is only connected to the regional input-output line pair LIO in one of the two-stage operations. In another stage of the two-stage operation, the data latched in the selected line pair BL1 in the input/output data latch circuit 110 is transmitted to the main input/output line pair MIO.

More specifically, the aforementioned two-stage operation includes a first-stage operation and a second-stage operation. When the memory device 100 is to perform a read operation on the memory cell MC1, in the first stage of operation, the data of the selected positioning line pair BL1 is latched from the corresponding sense amplification data latch SADL to the input/output data latch In the circuit 110, and in the second stage of operation, the data latched in the input/output data latch circuit 110 is transmitted to the main input/output line pair MIO. When the memory device 100 is to perform a write operation on the memory cell MC1, in the first stage of operation, the write data is latched from the main input/output line pair MIO to the input/output data latch circuit 110, and in the second stage In operation, the written data latched in the input/output data latch circuit 110 is transferred to the sense amplified data latch SADL corresponding to the selected bit line pair BL1.

The implementation details will be further explained below.

2A is a timing diagram of a read operation according to an embodiment of the present invention, and FIG. 2B is a timing diagram of a write operation according to an embodiment of the present invention. , Please refer to Figure 1 to Figure 2B together. In this embodiment, the input/output data latch circuit 110 includes a read data latch circuit RDL and a write data latch circuit WDL. The read data latch circuit RDL is coupled between the main input/output line pair MIO and the area input/output line pair LIO, and is controlled by the read input signal RDIN and the read output signal RDOUT. The write data latch circuit WDL is coupled between the main input/output line pair MIO and the area input/output line pair LIO, and is controlled by the write input signal WDIN and the write output signal WDOUT.

2A, when the memory device 100 performs a read operation READ, each read operation READ is divided into two stages: the first stage operation ST1 and the second stage operation ST2. In the first stage operation ST1, the row selection signal CSL1 selects and turns on the bit line pair BL1 and the area input/output line pair LIO. The sense amplified data latch SADL located between the bit line BLT1 and the complementary bit line BLB1 transmits the read data RD to the regional input-output line pair LIO. In addition, the read input signal RDIN allows the read data latch circuit RDL to receive and latch the read data RD from the regional input and output line pair LIO. In the second stage operation ST2, the read output signal RDOUT allows the read data RD latched in the read data latch circuit RDL to be transmitted to the main input and output line pair MIO, and the sensing enable signal SA_EN allows the main sensing and The driving circuit 120 senses the read data RD on the main input/output line pair MIO.

Specifically, in the second stage operation ST2 of the read operation READ, the row selection signal CSL1 is already in a disabled state, and the bit line pair BL1 disconnects the area input/output line pair LIO. In the read operation READ of this embodiment, the time length of the first phase operation ST1 is the same as the second phase operation ST2, the time length is both tCOR, and the time length tCOR is the same as the row selection period of the memory device 100. The row selection period is the pulse period at which each row (column) is activated.

2B, when the memory device 100 executes a write operation WRITE, each write operation WRITE is also divided into two stages: the first stage operation ST1 and the second stage operation ST2. In the first stage operation ST1, the drive enable signal DR_EN is in the enabled state, and the main sensing and driving circuit 120 transmits the write data WD to the main input/output line pair MIO. The write input signal WDIN allows the write data latch circuit WDL to receive the write data WD from the main input/output line to the MIO and latch it. In the second stage operation ST2, the write output signal WDOUT allows the write data latch circuit WDL to output the latched write data WD to the regional input-output line pair LIO. In addition, the row selection signal CSL1 makes the bit line pair BL1 turn on the area input/output line pair LIO. The write data WD is transferred to the sense amplification data latch SADL corresponding to the bit line pair BL1. Finally, the written data WD is written to the memory cell MC1.

In particular, in the first stage operation ST1 of the write operation WRITE, the row selection signal CSL1 is in a disabled state, and the bit line pair BL1 has not been connected to the regional input/output line pair LIO. In the write operation WRITE of this embodiment, the time length of the first phase operation ST1 is the same as the second phase operation ST2, the time length is both tCOW, and the time length tCOW is the same as the row selection period of the memory device 100.

In this embodiment, whether it is a two-stage operation of a write operation WRITE or a read operation READ, the time length of each stage operation is the same. The time of the first stage operation ST1 and the second stage operation ST2 of the read operation READ are both tCOR. The times of the first stage operation ST1 and the second stage operation ST2 of the write operation WRITE are both tCOW. In addition, the time length of the two-stage operation in this embodiment is the same in the write operation WRITE as in the read operation READ. The time length tCOR of the read operation READ is the same as the time length tCOW of the write operation WRITE. Here, the time length of each stage operation is a row selection period.

In view of the fact that the write data WD and the read data RD are latched by the input and output data latch circuit 110, the memory device 100 can adopt a two-stage operation regardless of whether the write operation WRITE or the read operation READ is performed, so that the memory The device 100 has a pipeline architecture and can execute multiple instructions in parallel.

3 is a sequence diagram of a read-while-write (read-while-write, RWW) operation according to an embodiment of the present invention. Referring to FIG. 3, when the memory device 100 performs a read-write synchronization operation RWW, each read-write synchronization operation RWW is divided into two phases: the first phase operation ST1 and the second phase operation ST2. In the first stage operation ST1, the drive enable signal DR_EN is in the enabled state, and the main sensing and driving circuit 120 transmits the write data WD to the main input/output line pair MIO. The write input signal WDIN enables the write data latch circuit WDL to receive the write data WD from the main input and output line to the MIO, and latch the write data WD. At the same time, the read input signal RDIN enables the read data latch circuit RDL to receive and latch the read data RD from the regional input and output line pair LIO. In the first stage operation ST1, the row selection signal CSL1 selects the bit line pair BL1 to turn on the area input/output line pair LIO. The read data RD is transferred from the sense amplified data latch SADL connected to the bit line pair BL1 to the read data latch circuit RDL.

In short, in the first stage of operation ST1, the memory device 100 can execute the input of the write data WD to the write data latch circuit WDL and the input of the read data RD of the memory cell MC1 to the read data latch in parallel. Circuit RDL.

In the second stage operation ST2, the write output signal WDOUT controls the write data latch circuit WDL to output the latched write data WD to the area input and output line pair LIO. At the same time, the read output signal RDOUT controls the read data latch circuit RDL to output the read data RD to the main input and output line pair MIO, so that the main sensing and driving circuit 120 senses the read data RD from the memory cell MC1. In addition, the row selection signal CSL2 selects the bit line pair BL2 to turn on the area input/output line pair LIO. The write data WD is transferred to the sense amplification data latch SADL corresponding to the bit line pair BL2. The written data WD will be written to the memory cell MC2.

In short, in the second stage operation ST2, the memory device 100 can execute in parallel the output of the write data WD from the write data latch circuit WDL and the output of the read data RD of the memory cell MC1 from the read data latch circuit RDL. . In the second stage operation ST2, the memory device 100 can sense the read data of the memory cell MC1 while writing the write data WD to the memory cell MC2.

In this embodiment, the time length of the first phase operation ST1 of the read-write synchronization operation RWW is the same as the time length of the second phase operation ST2, and may be a row selection period. For example, the time length of the read-write synchronization operation RWW can be equal to 2 times the time length tCOR (2*tCOR) or 2 times the time length tCOW (2*tCOW).

4 is a schematic circuit diagram of a memory device according to another embodiment of the invention. Referring to FIG. 4, the memory device 200 is similar to the memory device 100 and can implement the various embodiments described above. The difference between the memory device 200 and the memory device 100 is that the memory device 200 also includes an error correction (ECC) circuit 210. The ECC circuit 210 is used to perform error checking and correction on the data of the selected positioning line pair.

FIG. 5 is a timing diagram of a masked-write operation according to an embodiment of the present invention. The memory device 200 can implement the embodiment of FIG. 5, please refer to FIG. 5 in conjunction with FIG. 4. The memory device 200 successively receives the first write mask command MWR1 and the second write mask command MWR2, and correspondingly executes a read-modify-write operation 301 and a read-modify-write operation 302 . In the process of performing the read-modify-write operation 301 or 302, after the read operation READ is performed, the ECC circuit 210 performs error checking and correction step 310 on the read data. In addition, before performing the write operation WRITE, the memory device 200 also needs to perform a data transmission step 320 and a parity generation step 330. The implementation details of the read operation READ and the write operation WRITE can refer to the description of the above-mentioned embodiment. After the time T0 has elapsed since receiving the write mask command (MWR1 or MWR2), the memory device 200 will start to perform the data transmission step 320 and the verification data generation step 330. The step 330 of generating verification data includes, for example, combining the written data with the read data to generate verification data.

In this embodiment, the cycle length of the read operation READ and the write operation WRITE are the same, and both have a time length T. Here, the time length T is equal to two row selection periods, such as 2*tCOR or 2*tCOW. For the read operation READ and the write operation WRITE, the time length of each stage of the two-stage operation can be equal to one row selection period. When the memory device 200 performs a read-modify-write operation 301 or 302 on the selected bit line, the start time of the read operation READ applied on the selected bit line pair is longer than the write operation WRITE applied on the selected bit line pair. The start time is at least twice the time length T, that is, the memory device 200 will start the write operation WRITE after at least 4 row selection cycles after the read operation READ starts. In other words, in the read-modify-write operation of this embodiment, the time point when the read operation READ starts is m*T earlier than the time point when the write operation WRITE starts, where m is an integer greater than or equal to 2.

It is worth mentioning that the time interval tCCD between the first write mask command MWR1 and the second write mask command MWR2 can be shortened to n*T, where n is an integer greater than or equal to 1. In other words, the delay time from the minimum row address to the row address in this embodiment can be shortened to at least two row selection periods, so the operating speed of the memory device 200 can be improved.

FIG. 6 is a timing diagram of a write mask operation according to an embodiment of the present invention. The memory device 200 can implement the embodiment of FIG. 6, please refer to FIG. 6 in conjunction with FIG. 4. The memory device 200 successively receives the first write mask command MWR1 and the second write mask command MWR2, and correspondingly executes a read-modify-write operation 401 and a read-modify-write operation 402 . In the process of performing the read-modify-write operation 401 or 402, after the read operation READ is performed, the ECC circuit 210 performs error checking and correcting step 310 on the read data. Similar to the flow of the embodiment in FIG. 5, the memory device 200 performs a data transmission step 320 and a verification data generation step 330 before the data is written back to the memory cell.

In this embodiment, the memory device 200 has a read-write synchronization function. After step 330, the memory device 200 may perform a read and write synchronization operation RWW. When the memory device 200 performs the operation of writing data back to the memory cell in the read-modify-write operation 401, it can also perform the operation of reading data from the memory cell in the read-modify-write operation 402. In this way, the access speed of the memory device 200 can be accelerated. The implementation details of the read and write synchronization operation RWW, the read operation READ and the write operation WRITE can refer to the above-mentioned embodiments.

In this embodiment, the cycle lengths of the read-write synchronization operation RWW, read operation READ and write operation WRITE are the same, and they are all time length T. Here, the time length T is equal to two row selection periods, such as 2*tCOR or 2*tCOW. When the memory device 200 performs a read-modify-write operation 401 or 402 on the selected location line, the start time of the read operation READ is m*T earlier than the read-write synchronization operation RWW or the write operation WRITE, where m is An integer greater than or equal to 2.

It is worth mentioning that the time interval tCCD between the first write mask command MWR1 and the second write mask command MWR2 is also shortened to m*T. In other words, the delay time from the minimum row address to the row address in this embodiment can be shortened to at least 4 row selection cycles.

FIG. 7 is a flowchart of a method of operating a memory device according to an embodiment of the invention. Please refer to FIG. 7, the operation method of FIG. 7 is applicable to the read operation READ of the embodiments of FIGS. 1 to 6. The operation method of FIG. 7 will be described below in conjunction with the component symbols of the above-mentioned embodiment.

In step S710, in the first stage operation ST1, the data of the selected line pair stored in the sense amplification data latch SADL is latched to the input/output data latch circuit 110. In step S720, in the second stage operation ST2, the data latched in the selected line pair of the input/output data latch circuit 110 is transferred to the main input/output line pair MIO to perform the read operation READ.

FIG. 8 is a flowchart of a method of operating a memory device according to another embodiment of the present invention. Please refer to FIG. 8, the operation method of FIG. 7 is applicable to the write operation WRITE of the embodiments of FIG. 1 to FIG. 6. The operation method of FIG. 8 will be described below in conjunction with the component symbols of the above-mentioned embodiment.

In step S810, in the first stage operation ST1, the write data of the main input/output line pair MIO is latched to the input/output data latch circuit 110. In step S820, in the second stage operation ST2, the write data latched in the input/output data latch circuit 110 is transferred to the sense amplified data latch SADL corresponding to the selected positioning line pair to perform the write operation .

Each step of FIG. 7 and FIG. 8 has been described in detail in the embodiment of FIG. 1 to FIG.

In summary, the memory device of the present invention divides the access operation into two stages by the input/output data latch circuit arranged between the main input/output line pair and the area input/output line pair: data slave bit line pair The sensing and amplification data latch on the upper side is transmitted to the input and output data latch circuit and the data latched in the input and output data latch circuit is transmitted to the main input and output line pair. Therefore, the memory device can have a pipeline architecture to execute multiple instructions in parallel. This improves the access speed of the memory device. The embodiment of the present invention also provides an operating method suitable for the above-mentioned memory device.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100: Memory device 110: Input and output data latch circuit 120: Main sensing and driving circuit 210: ECC circuit 301, 302, 401, 402: read-modify-write operation 310: Error checking and correction steps 320: data transmission steps 330: Generate verification data step BLSA: bit line sense amplifier circuit BL1, BL2: bit line pair BLT1, BLT2: bit line BLB1, BLB2: complementary bit lines CSL1, CSL2: Row selection signal DR_EN: drive enable signal LIO: Regional input and output line pair LIOT: Regional input and output line LIOB: Complementary area input and output line MA: Memory cell array MIO: main input and output pair MIOT: main input and output line MIOB: Complementary main input and output line MC1, MC2: memory cell MWR1: The first write mask instruction MWR2: The second write mask instruction m: integer RD: read data RDIN: Read input signal RDOUT: read output signal RDL: Read data latch circuit READ: read operation RWW: Read and write synchronization operations SADL: Sense Amplified Data Latch SA_EN: Sense enable signal ST1: The first stage of operation ST2: second stage operation TC: switch T0: time tCCD: Time interval tCOR, tCOW, T: length of time WD: write data WDL: write data latch circuit WDIN: write input signal WDOUT: write output signal WL: word line WRITE: write operation S710, S720, S810, S820: the steps of the operation method of the memory device

FIG. 1 is a schematic circuit diagram of a memory device according to an embodiment of the invention. FIG. 2A is a timing diagram of a read operation according to an embodiment of the invention. FIG. 2B is a timing diagram of a write operation according to an embodiment of the invention. 3 is a sequence diagram of a read-while-write (read-while-write, RWW) operation according to an embodiment of the present invention. 4 is a schematic circuit diagram of a memory device according to another embodiment of the invention. FIG. 5 is a timing diagram of a masked-write operation according to an embodiment of the present invention. FIG. 6 is a timing diagram of a write mask operation according to an embodiment of the present invention. FIG. 7 is a flowchart of a method of operating a memory device according to an embodiment of the invention. FIG. 8 is a flowchart of a method of operating a memory device according to another embodiment of the present invention.

100: Memory device

110: Input and output data latch circuit

120: Main sensing and driving circuit

BLSA: bit line sense amplifier circuit

BL1, BL2: bit line pair

BLT1, BLT2: bit line

BLB1, BLB2: complementary bit lines

CSL1, CSL2: Row selection signal

DR_EN: drive enable signal

LIO: Regional input and output line pair

LIOT: Regional input and output line

LIOB: Complementary area input and output line

MA: Memory cell array

MIO: main input and output pair

MIOT: main input and output line

MIOB: Complementary main input and output line

MC1, MC2: memory cell

RDIN: Read input signal

RDOUT: read output signal

RDL: Read data latch circuit

SADL: Sense Amplified Data Latch

SA_EN: Sense enable signal

TC: switch

WDIN: write input signal

WDL: write data latch circuit

WDOUT: write output signal

WL: word line

Claims (12)

A memory device includes: an input and output data latch circuit, coupled between a main input and output line pair and a regional input and output line pair; and a bit line sensing and amplifying circuit, wherein the regional input and output line pair The bit line sense amplifier circuit is coupled to a plurality of bit line pairs, wherein when the memory device performs a read operation or a write operation, the memory device performs a two-stage operation to input or output the Data of a selected positioning line pair in some bit line pairs, wherein the selected positioning line pair is only connected to the input/output line pair of the area in one of the two-stage operations, and, in the two-stage operation In another stage of the operation, the data of the selected positioning line pair latched in the input/output data latch circuit is transmitted to the main input/output line pair, wherein the bit line sensing and amplifying circuit includes: a plurality of A sense-amplified data latch is used to store the data of the bit line pairs, wherein the two-stage operation includes a first stage operation and a second stage operation, wherein, when the memory device executes the read operation When, in the first stage of operation, the data of the selected positioning line pair is latched from the corresponding sense amplification data latch to the input and output data latch circuit, and in the second stage of operation, the The data stored in the input/output data latch circuit is transmitted to the main input/output line pair, wherein, when the memory device performs the write operation, the operation is performed in the first stage In operation, a write data is latched from the main input/output line pair to the input/output data latch circuit, and in the second stage of operation, the write data latched in the input/output data latch circuit is latched It is transmitted to the sensing and amplifying data latch corresponding to the selected positioning line pair. The memory device according to claim 1, wherein the input/output data latch circuit includes: a read data latch circuit coupled between the main input/output line pair and the regional input/output line pair, wherein, When the memory device performs the read operation, in the first stage of operation, the read data latch circuit receives the data of the selected positioning line pair, and in the second stage of operation, the read data is latched The data of the data latch circuit is transmitted to the main input/output line pair; and a write data latch circuit is coupled between the main input/output line pair and the input/output line pair of the area, wherein when the memory When the device executes the write operation, in the first stage operation, the write data latch circuit receives the write data, and in the second stage operation, the write data latched in the write data latch circuit The input data is transmitted to the sensing amplification data latch corresponding to the selected positioning line pair. The memory device according to claim 1, wherein when the memory device performs a read-write synchronization operation, a read-write synchronization period includes two row selection periods, and the input/output data latch circuit includes a read data A latch circuit and a write data latch circuit, wherein, in the first row selection period in the read and write synchronization period, the read data latch circuit receives a data latch from a first sense amplification data latch The first line pair Data, and the write data latch circuit receives a write data from the main input-output line pair, and in the second row selection period in the read and write synchronization period, the write data latch circuit writes The input data is provided to a second sense-amplified data latch, and the read data latch circuit transmits the data of the first bit line pair to the main input-output line pair, wherein the first bit line pair and A second bit line pair is two of the bit line pairs. The first sense-amplified data latch and the second sense-amplified data latch store the first bit line pair and the second bit line pair, respectively The data of the bit line pair. The memory device according to claim 3, further comprising: an error correction circuit for error checking and correction of data from the selected positioning line pair, wherein the memory device is performing a read-modify- The read-write synchronization operation is performed during the write operation, wherein the start time of the read operation applied to the selected positioning line pair is longer than the read-write synchronization operation or the write operation applied to the selected positioning line pair The start time is at least two such read and write synchronization cycles. The memory device according to claim 4, wherein the delay time from a row address to a row address is at least one read and write synchronization period, and is an integer multiple of the read and write synchronization period. The memory device according to claim 1, further comprising: an error correction circuit for error checking and correction of data from the selected positioning line pair, Wherein, the cycle length of the read operation and the write operation are both equal to two row selection periods, and the time length of each phase operation of the two-stage operation is equal to one row selection period, where, when the memory When the device performs a read-modify-write operation on the selected positioning line, the start time of the read operation applied to the selected positioning line pair is earlier than the start time of the write operation applied to the selected positioning line pair At least 4 cycles of the row selection. The memory device according to claim 6, wherein the delay time from a row address to a row address is at least the two row selection periods and is an integer multiple of the two row selection periods. The memory device according to claim 1, wherein each of the two-stage operations has the same length of time for the stage operation. The memory device according to claim 8, wherein the time length of the two-stage operation in the write operation is the same as that in the read operation. An operating method of a memory device includes: when the memory device performs a read operation, in a first stage of operation, latching data of a selected positioning line pair stored in a sensing amplification data latch To an input/output data latch circuit, in a second stage of operation, the data latched in the selected positioning line pair of the input/output data latch circuit is transmitted to a main input/output line pair; and when the memory device When a write operation is performed, in the first stage of operation, a write data of a main input/output line pair is latched to the input/output data latch circuit, and in the second stage of operation, it is latched in the Input and output data latch circuit The writing data is transmitted to the sensing and amplifying data latch corresponding to the selected positioning line pair. The operation method according to claim 10, wherein the steps of executing the read operation and the write operation further include: when the memory device executes the read operation, in the first stage operation, the input/output A read data latch circuit in the data latch circuit receives the data of the selected positioning line pair, and in the second stage operation, the data latched in the read data latch circuit is transmitted to the main input and output line Yes; and when the memory device performs the write operation, in the first stage of operation, the write data is received by a write data latch circuit in the input and output data latch circuit, and in the first phase In the two-stage operation, the write data latched in the write data latch circuit is transferred to the sense amplification data latch corresponding to the selected positioning line pair. The operation method according to claim 11, further comprising: a read-write synchronization period of a read-write synchronization operation includes two row selection periods; the first row selection period in the read-write synchronization period is determined by the read The data fetching latch circuit receives the data of a first bit line pair from a first sense-amplified data latch, and the write data latch circuit receives the write data from the main input/output line pair; and In the second row selection period of the read and write synchronization period, the write data latch circuit provides the write data to a second sense amplification data latch, and the read data latch circuit will The data of the first bit line pair is transmitted to the main input and output line Yes, where the first bit line pair and a second bit line pair are two of the bit line pairs, and the first sense-amplified data latch and the second sense-amplified data latch are respectively Store the data of the first bit line pair and the second bit line pair.

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