JP2022000832A - Memory device and operation method thereof - Google Patents

Abstract

To provide a memory device and an operation method thereof.SOLUTION: A memory device includes an input/output data latch circuit and a bit line sense amplifier circuit. The input/output data latch circuit is coupled between a main input/output line and a local input/output line pair. The local input/output line pair is coupled to a plurality of bit line pairs via the bit line sense amplifier circuit. When the memory device performs either a read operation or a write operation, the memory device performs a two-step type operation, and inputs or outputs the data of the selected bit line pair of these bit line pairs, the selected bit line pair is connected to the local input/output line pair only in one stage operation of the two-stage type operations, and the data of the selected bit line pair latched to the input/output data latch circuit is transmitted to the main input/output line pair in another stage operation of the two-stage type operation.SELECTED DRAWING: Figure 1

Description

The present invention relates to a memory device, and more particularly to a memory device capable of improving access speed and an operation method thereof.

Since the operating speed of a dynamic random access memory (DRAM) is limited by its own access mechanism, how to improve the access speed of a DRAM is particularly determined by an error correction code (Error-correcting code). , ECC) It has always been an important research subject for DRAMs equipped with circuits. The ECC circuit can improve the reliability of the data, but causes an increase in the delay time (Column-to-Column Delay, tCCD) between the column addresses of the DRAM. Therefore, how to provide a memory device having high reliability and high speed has become an important issue in the current development of memory technology.

The present invention provides a memory device having a pipeline structure and capable of shortening the operation cycle of the memory device, and an operation method thereof.

An embodiment of the present invention provides a memory device including an input / output data latch circuit and a bit line sense amplifier circuit. The input / output data latch circuit is coupled between the main input / output line pair and the local input / output line pair. The local input / output line pair is coupled to a plurality of bit line pairs via a bit line sense amplifier circuit. When the memory device performs either a read operation or a write operation, the memory device performs a two-step operation and inputs or outputs data of the selected bit line pair of these bit line pairs. The selected bit line pair is connected to the local I / O line pair only in one stage operation of the two-stage operation, and the selection latched in the input / output data latch circuit in the other stage operation of the two-stage operation. The data of the bit line pair is transmitted to the main input / output line.

Embodiments of the present invention provide a method of operating a memory device including the following steps. In the first stage operation, the data of the selected bit line pair stored in the sense amplifier data latch is latched in the input / output data latch circuit. In the second stage operation, the data of the selected bit line pair latched by the input / output data latch circuit is transmitted to the main input / output line pair, and the read operation is executed.

Based on the above, the present invention proposes a memory device and a method of operating the same. An input / output data latch circuit is provided between the main input / output line pair and the local input / output line pair to latch the data to be written or read. By temporarily storing the target data between the main I / O line pair and the local I / O line pair, the access operation can be divided into the first stage operation and the second stage operation, and the access operation has a pipeline structure. Achieve to have.

It is a circuit explanatory drawing of the memory device by embodiment of this invention. It is a timing diagram of the reading operation by embodiment of this invention. It is a timing diagram of the writing operation by embodiment of this invention. It is a write-reading synchronous operation timing diagram by embodiment of this invention. It is a circuit explanatory drawing of the memory device by another embodiment of this invention. It is a timing diagram of the mask writing (masked-write) operation by embodiment of this invention. It is a timing diagram of the writing mask operation by another embodiment of this invention. It is a flow diagram of the operation method of the memory device by embodiment of this invention. It is a flow diagram of the operation method of the memory device by another embodiment of this invention.

In order to make the above-mentioned features and advantages of the present invention easy to understand, embodiments will be given, and the details will be described below together with the drawings.

In order to make the present invention easier to understand, the following embodiments are given as examples in which the present invention can be carried out based on the embodiments. Also, wherever possible, elements / members / steps using the same reference numerals in drawings and embodiments represent the same or similar components.

In the following embodiment, DRAM is used as an embodiment, and the memory device of the present invention and its operation method will be described. However, the present invention does not limit the type of memory device.

FIG. 1 is a circuit explanatory diagram of a memory device according to an embodiment of the present invention. With reference to FIG. 1, the memory device 100 includes at least an input / output data latch circuit 110, a bit line sense amplifier circuit BLSA, and a memory cell array MA. The memory cell array MA is composed of a plurality of memory cells arranged in an array. These memory cells connect a plurality of word lines and a plurality of bit line pairs. For simplicity of explanation, the memory cell array MA in FIG. 1 shows only two memory cells MC1 and MC2 on the word line WL as an example. The memory cell MC1 is coupled to the bit line pair BL1. The bit line pair BL1 includes a bit line BLT1 and a complementary bit line BLB1. The memory cell MC2 is coupled to the bit line pair BL2. The bit line pair BL2 includes a bit line BLT2 and a complementary bit line BLB2.

The input / output data latch circuit 110 is coupled between the main input / output line pair MIO and the local input / output line pair LIO. The main input / output line pair MIO includes a main input / output line MIOT and a complementary main input / output line MIOB. The local I / O line pair LIOT includes a local I / O line LIOT and a complementary local I / O line LIOB. The input / output data latch circuit 110 is used to latch the data to be written to the memory cell array MA or the data of the memory cell array MA output from the local input / output line pair LIO.

The local input / output line pair LIO is coupled to a plurality of bit line pairs, for example, bit line pairs BL1 and BL2 via the bit line sense amplifier circuit BLSA. The column selection signal CSLn controls the switch TC to conduct the local input / output line pair LIO and the bit line pair BLn, where n is an integer. The bit line sense amplifier circuit BLSA is used to sense and amplify the potential signal of a bit line pair. The bit line sense amplifier circuit BLSA further includes a plurality of sense amplifier data latch SADLs. These sense amplifier data latch SADLs are connected between these bit line pairs and are used to store the data in these bit line pairs.

The main sensing drive circuit 120 is coupled to the main input / output line pair MIO and is controlled by the drive enable signal DR_EN and the sense enable signal SA_EN. When the drive enable signal DR_EN enables the main sensing drive circuit 120, the memory device 100 performs a write operation to the memory cell array MA. The main input / output line pair MIO receives write data from the main sensing drive circuit 120, and the local input / output line pair LIO receives write data from the main input / output line pair MIO via the input / output data latch circuit 110. Write data is transmitted to the sense amplifier data latch SADL of the corresponding bit line pair. When the sensor enable signal SA_EN enables the main sensing drive circuit 120, the memory device 100 performs a read operation on the memory cell array MA. The read data stored in the sense amplifier data latch SADL is transmitted to the input / output data latch circuit 110 via the local input / output line pair LIO and latched in the input / output data latch circuit 110. Next, read data is transmitted from the input / output data latch circuit 110 to the MIO of the main input / output line pair. Finally, the main sensing drive circuit 120 senses the read data of the main input / output line pair MIO.

In other words, in the present embodiment, when the memory device performs either a read operation or a write operation, the memory device 100 performs a two-step operation to select the selected bits of these bit line pairs. Input or output line pair data. For example, since the memory cell to be accessed is the memory cell MC1, the bit line pair is selected as the bit line pair BL1. The selected bit line pair BL1 is connected to the local I / O line pair LIO only in one stage operation of the two-stage operation. In another stage operation of the two-stage operation, the data of the selected bit line pair BL1 latched in the input / output data latch circuit 110 is transmitted to the main input / output line pair MIO.

More specifically, the above-mentioned two-stage operation includes a first stage operation and a second stage operation. When the memory device 100 performs a read operation to the memory cell MC1, in the first stage operation, the data of the selected bit line pair BL1 is latched from the corresponding sense amplifier data latch SADL to the input / output data latch circuit 110, and the first stage operation is performed. In the two-stage operation, the data latched by the input / output data latch circuit 110 is transferred to the main input / output line pair MIO. When the memory device 100 executes a write operation in the memory cell MC1, the write data is latched from the main input / output line MIO to the input / output data latch circuit 110 in the first stage operation, and the input / output data latch in the second stage operation. The write data latched in the circuit 110 is transmitted to the sense amplifier data latch SADL corresponding to the selected bit line BL1.

The details of the implementation will be further described below.

2A is a timing diagram of a read operation according to an embodiment of the present invention, and FIG. 2B is a timing diagram of a write operation according to an embodiment of the present invention. 1 to 2B are also referred to. In this embodiment, the input / output data latch circuit 110 includes a read data latch circuit RDL and a write data latch circuit WDL. The read data latch circuit RDL is coupled between the main input / output line pair MIO and the local input / output line pair LIO, and is controlled by the read input signal RDIN and the read output signal RDOUT. The write data latch circuit WDL is coupled between the main input / output line pair MIO and the local input / output line pair LIO, and is controlled by the write input signal WDIN and the write output signal WDOUT.

With reference to FIG. 2A, each time the memory device 100 executes the read operation READ, the read operation READ is divided into two stages, the first stage operation ST1 and the second stage operation ST2. In the first stage operation ST1, the column selection signal CSL1 selectively conducts the bit line pair BL1 and the local input / output line pair LIO. The sense amplifier data latch SADL between the bit line BLT1 and the complementary bit line BLB1 transmits the read data RD to the local I / O line pair LIO. In addition, the read input signal RDIN is received from the local input / output line pair LIO by the read data latch circuit RDL, and the read data RD is latched. In the second stage operation ST2, the read output signal RDOUT transmits the read data RD latched by the read data latch circuit RDL to the main input / output line pair MIO, and the sensor enable signal SA_EN is the main input / output to the main sensing drive circuit 120. The read data RD of the line pair MIO is sensed.

In particular, it should be explained that in the second stage operation ST2 of the read operation READ, the column selection signal CSL1 is already in an invalid state, and the bit line pair BL1 and the local input / output line pair LIO are non-conducting. In the read operation READ of the present embodiment, the time length of the first stage operation ST1 is the same as that of the second stage operation ST2, the time lengths are all tCOR, and the time length tCOR is. It is the same as the column selection cycle of the memory device 100. The column selection period is the pulse period at which each column is started.

With reference to FIG. 2B, each time the memory device 100 executes the write operation WRITE, the write operation WRITE is similarly divided into two stages, the first stage operation ST1 and the second stage operation ST2. In the first stage operation ST1, the drive enable signal DR_EN is in the enabled state, and the main sensing drive circuit 120 transmits the write data WD to the main input / output line pair MIO. The write input signal WDIN causes the write data latch circuit WDL to receive the write data WD from the main input / output line pair MIO and latch it. In the second stage operation ST2, the write output signal WDOUT causes the local input / output line pair LIO to output the write data WD latched by the write data latch circuit WDL. In addition, the column selection signal CSL1 conducts the bit line pair BL1 to the local input / output line pair LIO. The write data WD is transmitted to the sense amplifier data latch SADL corresponding to the bit line pair BL1. Finally, the write data WD is written to the memory cell MC1.

In particular, in the first stage operation ST1 of the write operation WRITE, the column selection signal CSL1 is in an invalid state, and the bit line pair BL1 is not connected to the local input / output line pair LIO. In the write operation WRITE of the present embodiment, the time length of the first stage operation ST1 is the same as that of the second stage operation ST2, the time lengths are all tCOW, and the time length tCOW is. It is the same as the column selection cycle of the memory device 100.

In the present embodiment, the length of time of each stage operation is the same regardless of whether the write operation is WRITE or the read operation is a two-step operation of READ. The time of the first stage operation ST1 and the second stage operation ST2 of the read operation READ are both tCOR. The time of the first stage operation ST1 and the second stage operation ST2 of the write operation WRITE is tCOW. Further, the length of time of the two-step operation of the present embodiment is the same in both the write operation WRITE and the read operation READ. The time length tCOR of the read operation READ is the same as the time length tCOW of the write operation WRITE. Here, the length of time for each stage operation is one column selection cycle.

The write data WD and the read data RD are latched via the input / output data latch circuit 110, and the memory device 100 adopts a two-step operation regardless of whether the write operation is WRITE or the read operation is READ. Therefore, the memory device 100 has a pipeline structure and can execute a plurality of commands in parallel.

FIG. 3 is a timing diagram of a read-write synchronous (read-while-write, RWW) operation according to an embodiment of the present invention. With reference to FIG. 3, each time the memory device 100 executes the write / read synchronous operation RWW, the write / read synchronous operation RWW is divided into two stages, the first stage operation ST1 and the second stage operation ST2. In the first stage operation ST1, the drive enable signal DR_EN is in the enabled state, and the main sensing drive circuit 120 transmits the write data WD to the main input / output line pair MIO. The write input signal WDIN enables the write data latch circuit WDL, receives the write data WD from the main input / output line pair MIO, and latches the write data WD. At the same time, the read input signal RDIN enables the read data latch circuit RDL to receive and latch the read data RD from the local I / O line pair LIO. In the first stage operation ST1, the column selection signal CSL1 selectively conducts the bit line pair BL1 to the local input / output line pair LIO. The read data RD is transmitted from the sense amplifier data latch SADL connected to the bit line pair BL1 to the read data latch circuit RDL.

In other words, in the first stage operation ST1, the memory device 100 inputs the write data WD to the write data latch circuit WDL and inputs the read data RD from the memory cell MC1 to the data latch circuit RDL in parallel. can do.

In the second stage operation ST2, the write output signal WDOUT controls the write data latch circuit WDL to output the latched write data WD to the local input / output line pair LIO. At the same time, the read output signal RDOUT controls the read data latch circuit RDL to output the read data RD to the main input / output line pair MIO, and causes the main sensing drive circuit 120 to sense the read data RD from the memory cell MC1. In addition, the column selection signal CSL2 selectively conducts the bit line pair BL2 to the local input / output line LIO. The write data WD is transmitted to the sense amplifier data latch SADL corresponding to the bit line pair BL2. The write data WD is written in the memory cell MC2.

Briefly, in the second stage operation ST2, the memory device 100 outputs the write data WD from the write data latch circuit WDL and outputs the read data RD of the memory cell MC1 from the read data latch circuit RDL in parallel. Can be run on. The memory device 100 can write the write data WD to the memory cell MC2 while sensing the read data of the memory cell MC1 in the second stage operation ST2.

In the present embodiment, the time length of the first stage operation ST1 of the write / read operation RWW is the same as the time length of the second stage operation ST2, and can be one column selection cycle. For example, the time length of the write / read synchronous operation RWW can be equal to twice the time length tCOR (2 * tCOR) or twice the time length tCOW (2 * tCOW).

FIG. 4 is a circuit explanatory diagram of a memory device according to another embodiment of the present invention. With reference to FIG. 4, the memory device 200 is similar to the memory device 100 and can implement the various embodiments described above. The difference between the memory device 200 and the memory device 100 is that the memory device 200 further includes an error correction (ECC) circuit 210. The ECC circuit 210 is used to perform error checking and correction on the data from the selected bit line pair.

FIG. 5 is a timing diagram of a masked-write operation according to the embodiment of the present invention. The memory device 200 can implement the embodiment of FIG. 5, with reference to FIG. 5 in conjunction with FIG. The memory device 200 receives the first mask write command MWR1 and the second mask write command MWR2 in order, and executes the read change-write (read-modify-write) operation 301 and the read-correction-write operation 302 correspondingly. .. In the process of executing the read-correction-write operation 301 or 302, after the read operation READ is executed, the ECC circuit 210 executes the error check correction step 310 for the read data. Further, the memory device 200 also needs to execute the data transmission step 320 and the parity generation step 330 before executing the write operation WRITE. For details of the read operation READ and the write operation WRITE, the description of the above embodiment can be referred to. After a lapse of time T0 starting from the mask write command (MWR1 or MWR2), the memory device 200 starts executing the data transmission step 320 and the parity data generation step 330 for the first time. In the parity generation step 330, for example, the read data and the write data are combined to generate the parity.

In the present embodiment, the cycle lengths of the read operation READ and the write operation WRITE are the same, and both are the length T of the time. The length T of time is equal to two column selection cycles, eg 2 * tCOR or 2 * tCOW. For the read operation READ and the write operation WRITE, the length of time of each stage operation of the two-stage operation can be equal to one column selection cycle. When the memory device 200 executes the read-correction-write operation 301 or 302 to the selected bit line pair, the start time for performing the read operation READ of the selected bit line pair is the write operation of the selected bit line pair. The memory device 200 executes the write operation WRITE after at least four column selection cycles have elapsed after the read operation READ starts execution, which is at least twice the time length T earlier than the start time for performing the WRITE. Start. In other words, in the read-correction-write operation of the present embodiment, the time point at which the read operation READ is started is m * T earlier than the time point at which the write operation WRITE is started, where m is 2 or more. Is an integer of.

It should be mentioned that the time interval tCDD of the first mask write command MWR1 and the second mask write command MWR2 can be shortened to n * T, where n is an integer greater than or equal to 1. That is, the delay time between the minimum column addresses of the present embodiment can be shortened to at least two column selection cycles, so that the operating speed of the memory device 200 can be improved.

FIG. 6 is a timing diagram of the writing mask operation according to the embodiment of the present invention. The memory device 200 can implement the embodiment of FIG. 6, with reference to FIG. 6 in conjunction with FIG. The memory device 200 receives the first mask write command MWR1 and the second mask write command MWR2 in order, and executes the read change-write operation 401 and the read-correction-write operation 402 in order. In the process of executing the read-correction-write operation 401 or 402, after the read operation READ is executed, the ECC circuit 210 executes the error check correction step 310 for the read data. Similar to the flow of the embodiment of FIG. 5, the memory device 200 executes the data transmission step 320 and the parity data generation step 330 before the data is written back to the memory cell.

In this embodiment, the memory device 200 has a read / write function. The memory device 200 executes a write / read synchronous operation RWW after step 330. When the memory device 200 executes the operation of writing back the data to the memory cell in the read-correction-write operation 401, the operation of reading the data from the memory cell can be executed at the same time in the read-correction-write operation 402. In this way, the access speed of the memory device 200 can be accelerated. For details of the implementation of the write / read synchronous operation RWW, the read operation READ, and the write operation WRITE, the above-described embodiment can be referred to.

In the present embodiment, the cycle lengths of the write / read synchronous operation RWW, the read operation READ, and the write operation WRITE are the same, and all of them have a time length T. Here, the length T of time is equal to two column selection cycles, eg, 2 * tCOR or 2 * tCOW. When the memory device 200 performs a read-correction-write operation 401 or 402 on the selected bit line, the start time point of the read operation READ is m * T earlier than the write-read synchronous operation RWW or the write operation WRITE. Here, m is an integer of 2 or more.

It should be mentioned that the time interval tCDD of the first mask writing command MWR1 and the second mask writing command MWR2 is also shortened to m * T. That is, the delay time between the minimum column addresses of the present embodiment can be shortened to at least four column selection cycles.

FIG. 7 is a flow chart of a memory device operation method according to the embodiment of the present invention. With reference to FIG. 7, the operation method of FIG. 7 is applied to the read operation READ of the embodiments of FIGS. 1 to 6. Hereinafter, the operation method of FIG. 7 will be described using the member reference numerals of the above-described embodiment.

In step S710, in the first stage operation ST1, the data of the selected bit line pair stored in the sense amplifier data latch SADL is latched in the input / output data latch circuit 110. In step S720, in the second stage operation ST2, the data of the selected bit line pair latched by the input / output data latch circuit 110 is transmitted to the main input / output line pair MIO, and the read operation READ is executed.

FIG. 8 is a flow chart of a method of operating a memory device according to another embodiment of the present invention. With reference to FIG. 8, the operation method of FIG. 7 is applied to the write operation WRITE of the embodiment of FIGS. 1 to 6. Hereinafter, the operation method of FIG. 8 will be described using the member reference numerals of the above-described embodiment.

In step S810, in the first stage operation ST1, the write data of the main input / output line pair MIO is latched to the input / output data latch circuit 110. In step S820, in the second stage operation ST2, the write data latched by the input / output data latch circuit 110 is transmitted to the sense amplifier data latch SADL corresponding to the selected bit line pair, and the write operation is executed.

Each step of FIGS. 7 and 8 is described in detail in the embodiments of FIGS. 1 to 6, and a person skilled in the art can obtain sufficient suggestions and teachings from the above description, and thus will be described again here. do not do.

In summary, the memory device of the present invention inputs the access operation by the input / output data latch circuit provided between the main input / output line pair and the local input / output line pair, and inputs the data from the sense amplifier data latch of the bit line pair. It is divided into two stages: transmitting to the output data latch circuit and transmitting the data latched in the input / output data latch circuit to the main input / output line pair. Therefore, the memory device has a pipeline structure and can execute a plurality of commands in parallel. This improves the access speed of the memory device. The embodiment of the present invention also presents an operating direction applied to the memory device.

The present invention has disclosed embodiments as described above, but is not intended to limit the invention, and one of ordinary skill in the art may make some modifications and modifications without departing from the spirit of the invention. Therefore, the scope of protection of the present invention is based on the scope of claims described later.

100 Memory device 110 Input / output data latch circuit 120 Main sensing drive circuit 210 ECC circuit 301, 302, 401, 402 Read-correction-write operation 310 Error check correction step 320 Data transmission step 330 Parity data generation step BLSA Bit line sense amplifier circuit BL1, BL2 bit line pair BLT1, BLBT2 bit line BLB1, BLB2 complementary bit line CSL1, CSL2 column selection signal DR_EN drive enable signal LIOT local input / output line pair LIOT local input / output line LIOB complementary local input / output line MA memory cell array MIO main Output line pair MIOT Main input / output line MIOB Complementary main input / output line MC1, MC2 Memory cell MWR1 First mask write command MWR2 Second mask write command M Integer RD Read data RDIN Read input signal RDOUT Read output signal RDL Read data Latch circuit READ Read operation RWW write read synchronous operation SADL sense amplifier data latch SA_EN sensor enable signal ST1 1st stage operation ST2 2nd stage operation TC switch T0 time tCDCD time interval tCOR, tCOW, T time length WL word line WD write data WDL write Data latch circuit WDIN write input signal WDOUT write output signal WRITE write operation S710, S720, S810, S820 Steps of operation method of memory device

Claims (14)

An I / O data latch circuit coupled between a main I / O line pair and a local I / O line pair,
Bit line sense amplifier circuit and
Including
The local input / output line pair is coupled to a plurality of bit line pairs via the bit line sense amplifier circuit.
When the memory device performs either a read operation or a write operation, the memory device performs a two-step operation and inputs data of a selected bit line pair from the plurality of bit line pairs. Or output
The selected bit line pair is conducted to the local input / output line pair only in one stage operation of the two-stage operation, and in the other stage operation of the two-stage operation, the input / output data latch circuit. The data of the selected bit line pair latched on the memory device is transmitted to the main input / output line pair. The bit line sense amplifier circuit includes a plurality of sense amplifier data latches for storing the data of the plurality of bit line pairs.
The two-stage operation includes a first stage operation and a second stage operation.
When the memory device performs a read operation, in the first stage operation, the data of the selected bit line pair is latched from the corresponding sense amplifier data latch to the input / output data latch circuit, and the second stage operation. In the stage operation, the data latched by the input / output data latch circuit is transmitted to the main input / output line pair.
When the memory device performs a write operation, the write data is latched from the main input / output line pair to the input / output data latch circuit in the first stage operation, and the input / output data in the second stage operation. The memory device according to claim 1, wherein the write data latched in the latch circuit is transmitted to the sense amplifier data latch corresponding to the selected bit line pair. The input / output data latch circuit is
A read data latch circuit coupled between the input / output line pair and the local input / output line pair,
A write data latch circuit coupled between the main I / O line pair and the local I / O line pair,
Including
When the memory device performs the read operation, in the first stage operation, the read data latch circuit receives the data of the selected bit line pair, and in the second stage operation, the read data latch. The data latched in the circuit is transmitted to the main input / output line pair and
When the memory device executes the write operation, in the first stage operation, the write data latch circuit receives write data, and in the second stage operation, the write data latched by the write data latch circuit is the write data. The memory device according to claim 2, which is transmitted to the sense amplifier data latch corresponding to the selected bit line pair. When the memory device performs a write-write synchronous operation, the write-time read cycle includes two column selection cycles, and the input / output data latch circuit includes a read data latch circuit and a write data latch circuit.
In the first column selection cycle of the write-on read cycle, the read data latch circuit receives data of the first bit line pair from the first sense amplifier data latch, and the write data latch circuit is the main. Receives write data from the input / output line pair and
In the second column selection cycle of the write-on read cycle, the write data latch circuit provides the write data to the second sense amplifier data latch, and the read data latch circuit is the first bit line pair. Data is transmitted to the main input / output line pair,
The first bit line pair and the second bit line pair are two of the plurality of bit line pairs, and the first sense amplifier data latch and the second sense amplifier data latch are the first bits, respectively. The memory device according to claim 1, wherein the data of the line pair and the second bit line pair are stored. The data of the selected bit line pair further includes an error correction circuit for performing error inspection and correction.
The memory device executes the write-read synchronous operation in the process of performing the read-correction-write operation, and the start time of the read operation executed for the selected bit line pair is executed for the selected bit line pair. The memory device according to claim 4, wherein at least two write-time read cycles are earlier than the start time of the write-read synchronous operation or the write operation. The memory device according to claim 5, wherein the delay time between the column addresses is at least one write-read synchronization cycle, which is an integral multiple of the write-read synchronization cycle. The data of the selected bit line pair further includes an error correction circuit for performing error inspection and correction.
The cycle lengths of the read operation and the write operation are both equal to the two column selection cycles, and the time length of each of the stage operations of the two-stage operation is equal to one of the column selection cycles.
When the memory device performs a read-correct-write operation on the selected bit line pair, the start time of the read operation performed on the selected bit line pair is performed on the selected bit line pair. The memory device according to claim 1, wherein at least four of the column selection cycles are earlier than the start time of the write operation. The memory device according to claim 7, wherein the delay time between the column addresses is at least two cycles of the column selection cycle, which is an integral multiple of the two cycles of the column selection cycle. The memory device according to claim 1, wherein the time length of each of the two-stage operations is the same. The memory device according to claim 9, wherein the length of time of the two-step operation is the same in the write operation and the read operation. In the first stage operation, the step of latching the data of the selected bit line pair stored by the sense amplifier data latch to the input / output data latch circuit, and
A method of operating a memory device, comprising a step of transmitting the data of the selected bit line pair latched on the input / output data latch circuit to the main input / output line pair and executing a read operation in the second stage operation. In the first stage operation, the step of latching the write data of the main input / output line pair to the input / output data latch circuit,
The second stage operation further comprises a step of transmitting the write data latched in the input / output data latch circuit to the sense amplifier data latch corresponding to the selected bit line pair and executing the write operation. Item 11. The operation method according to Item 11. The step of executing the read operation and the write operation is
When the memory device performs the read operation, in the first stage operation, the read data latch circuit of the input / output data latch circuit receives the data of the selected bit line pair, and in the second stage operation, the read data latch circuit receives the data of the selected bit line pair. The step in which the data latched by the read data latch circuit is transmitted to the main input / output line pair, and
When the memory device executes the write operation, the write data latch circuit of the input / output data latch circuit receives the write data in the first stage operation, and the write data latch circuit in the second stage operation. The step of transmitting the write data latched to to the sense amplifier data latch corresponding to the selected bit line pair, and
The operation method according to claim 12, further comprising. The write-time read cycle of the write-read synchronous operation includes two column selection cycles.
The operation method is
In the column selection cycle at the beginning of the write-on read cycle, the read data latch circuit receives the data of the first bit line pair from the first sense amplifier data latch, and the write data latch circuit is the main input. The step of receiving the write data from the output line pair and
In the second column selection cycle of the write-on read cycle, the write data latch circuit provides the write data to the second sense amplifier data latch, and the read data latch circuit is the first bit line pair. As a step of transmitting the data of the above to the main input / output line pair,
Including
The first bit line pair and the second bit line pair are two of the plurality of bit line pairs, and the first sense amplifier data latch and the second sense amplifier data latch are the first bits, respectively. The operation method according to claim 13, wherein the data of the line pair and the second bit line pair are stored.

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