JP7187721B2 - Memory device and method of operation - Google Patents

Description

TECHNICAL FIELD The present invention relates to memory devices, and more particularly, to memory devices and methods of operation thereof that can improve access speed.

Dynamic Random Access Memory
Memory, DRAM) is limited by its own access mechanism.
This is always an important research topic for DRAMs with error-correcting code (ECC) circuits. The ECC circuit can improve data reliability, but the delay time between column addresses of DRAM (Column-to-Column Delay)
y, tCCD). Therefore, how to provide a memory device with high reliability and high speed is an important issue in current memory technology development.

The present invention provides a memory device having a pipeline structure and capable of shortening the operation cycle of the memory device and an operating method thereof.

Embodiments of the present invention provide memory devices that include input/output data latch circuits and bitline sense amplifier circuits. An input/output data latch circuit is coupled between the main input/output line pair and the local input/output line pair. A local input/output line pair is coupled to a plurality of bit line pairs via bit line sense amplifier circuits. when the memory device performs either a read operation or a write operation, the memory device performs a two-step operation to input or output data on selected bit line pairs of those bit line pairs; The selected bit line pair is connected to the local input/output line pair only in one stage of the two-stage operation and the selection latched in the input/output data latch circuit in the other stage of the two-stage operation. The data on the bit line pair that has been set is transmitted to the main input/output lines. When the memory device performs a write-read synchronous operation, a write-time read cycle includes two column selection cycles, and the input/output data latch circuit includes a read data latch circuit and a write data latch circuit. In the first column select cycle during the read cycle during write, the read data latch circuit receives data on the first bit line pair from the first sense amplifier data latch, and the write data latch circuit receives data from the main input/output line pair. receiving write data, and in a second column select cycle of a read-at-write cycle, a write data latch circuit provides write data to a second sense amplifier data latch, and a read data latch circuit provides the write data to the first bit line; Send the data of the pair to the main I/O line pair. The first bit line pair and the second bit line pair are two of the plurality of bit line pairs, and the first sense amplifier data latch and the second sense amplifier data latch are respectively the first bit line pair and the second bit line pair. Save bit line pair data.

An embodiment of the present invention provides a memory device operating method including the following steps. In the first stage operation, the selected bit line pair data stored in the sense amplifier data latch is latched into the input/output data latch circuit. In the second stage operation, the data of the selected bit line pair latched in the input/output data latch circuit is transmitted to the main input/output line pair, and a read operation is performed. A read-on-write cycle of a write-read synchronous operation includes two column select cycles. In the memory device operation method, in the first column selection cycle of the read cycle during writing, the read data latch circuit of the input/output data latch circuit receives the data of the first bit line pair from the first sense amplifier data latch and inputs the data. The write data latch circuit of the output data latch circuit receives write data from the main input/output line pair; providing to the amplifier data latch and the read data latch circuit transmitting data on the first bit line pair to the main input/output line pair. The first bit line pair and the second bit line pair are two of the plurality of bit line pairs, and the first sense amplifier data latch and the second sense amplifier data latch are respectively the first bit line pair and the second bit line pair. Save bit line pair data.

Based on the above, the present invention proposes a memory device and its operating method. An input/output data latch circuit is provided between the main input/output line pair and the local input/output line pair to latch data to be written or read. By temporarily storing the target data between the main input/output line pair and the local input/output line pair, the access operation can be divided into a first stage operation and a second stage operation, and the access operation has a pipeline structure. to achieve

1 is a circuit diagram of a memory device according to an embodiment of the present invention; FIG. 4 is a timing diagram of a read operation according to an embodiment of the invention; FIG. 4 is a timing diagram of a write operation according to an embodiment of the invention; FIG. 4 is a timing diagram of write and read synchronous operations according to an embodiment of the present invention; FIG. FIG. 4 is a circuit diagram of a memory device according to another embodiment of the present invention; 4 is a timing diagram of a masked-write operation according to an embodiment of the invention; FIG. FIG. 5 is a timing diagram of a write mask operation according to another embodiment of the invention; 1 is a flow diagram of a method of operating a memory device according to an embodiment of the invention; FIG. 4 is a flow diagram of a method of operating a memory device according to another embodiment of the present invention; FIG.

In order to make the above features and advantages of the present invention comprehensible, the following detailed description is given by way of example and in conjunction with the drawings.

In order to facilitate the understanding of the invention, the following embodiments are provided as examples on which the invention can be practiced. Also, wherever possible, elements/members/steps using the same reference numerals in the drawings and embodiments represent the same or similar components.

In the following embodiments, a DRAM is used as an example to describe the memory device and method of operation of the present invention. However, the present invention does not limit the type of memory device.

FIG. 1 is a circuit diagram of a memory device according to an embodiment of the invention. Referring to Figure 1,
The memory device 100 includes at least an input/output data latch circuit 110, a bit line sense amplifier circuit BLSA and a memory cell array MA. The memory cell array MA is composed of a plurality of memory cells arranged in an array. These memory cells connect multiple word lines and multiple bit line pairs. For simplicity of explanation, the memory cell array MA of FIG. 1 shows only two memory cells MC1 and MC2 on the word line WL as an example.
Memory cell MC1 is coupled to bit line pair BL1. Bit line pair BL1 includes bit line BLT1 and complementary bit line BLB1. Memory cell MC2 is coupled to bit line pair BL2. Bit line pair BL2 includes bit line BLT2 and complementary bit line BLB2.

The input/output data latch circuit 110 includes a main input/output line pair MIO and a local input/output line pair LI.
O. Main input/output line pair MIO includes main input/output line MIOT and complementary main input/output line MIOB. Local input/output line pair LIO includes local input/output line LIOT and complementary local input/output line LIOB. The input/output data latch circuit 110 is connected to the memory cell array MA.
It is used to latch data to be written to the memory cell array MA or data to be output from the local input/output line pair LIO.

Local input/output line pair LIO is coupled to a plurality of bit line pairs, eg, bit line pairs BL1 and BL2, via bit line sense amplifier circuits BLSA. Column select signal CSLn
controls switch TC to conduct local input/output line pair LIO and bit line pair BLn, where n is an integer. The bit line sense amplifier circuit BLSA is used for sensing and amplifying the potential signal of the bit line pair. Bit line sense amplifier circuit BLS
A further includes a plurality of sense amplifier data latches SADL. These sense amplifier data latches SADL are connected between these bit line pairs and used to store the data of these bit line pairs.

The main sensing driver circuit 120 is coupled to the main input/output line pair MIO and controlled by a drive enable signal DR_EN and a sense enable signal SA_EN. When the drive enable signal DR_EN enables the main sensing drive circuit 120, the memory device 100
A write operation is performed on the memory cell array MA. The main input/output line pair MIO receives write data from the main sensing driving circuit 120, the local input/output line pair LIO receives write data from the main input/output line pair MIO through the input/output data latch circuit 110, Write data is transmitted to the sense amplifier data latch SADL of the corresponding bit line pair.
When the sensor enable signal SA_EN enables the main sensing driver circuit 120, the memory device 100 performs a read operation on the memory cell array MA. The read data stored in the sense amplifier data latch SADL is transmitted to the input/output data latch circuit 110 via the local input/output line pair LIO and latched by the input/output data latch circuit 110 . Next, read data is transmitted from the input/output data latch circuit 110 to MIO of the main input/output line pair. Finally, the main sensing drive circuit 120 senses read data on the main input/output line pair MIO.

In other words, in this embodiment, when the memory device performs either a read operation or a write operation, memory device 100 performs a two-step operation to read selected bits of these bit line pairs. Inputs or outputs line pair data. For example, since the memory cell to be accessed is the memory cell MC1, the bit line pair is the bit line pair BL
selected as 1. The selected bit line pair BL1 is connected to local input/output line pair LIO only in one stage of the two-stage operation. In another stage of the two-step operation, data on selected bit line pair BL1 latched in input/output data latch circuit 110 is transmitted to main input/output line pair MIO.

More specifically, the two-stage operation described above includes a first stage operation and a second stage operation. When the memory device 100 performs a read operation on the memory cell MC1, in the first stage operation, data on the selected bit line pair BL1 is latched from the corresponding sense amplifier data latch SADL to the input/output data latch circuit 110, and then latched into the input/output data latch circuit 110. In the 2-stage operation, the data latched by the input/output data latch circuit 110 is transferred to the main input/output line pair MIO. When the memory device 100 performs a write operation on the memory cell MC1, the write data is latched from the main input/output line MIO to the input/output data latch circuit 110 in the first stage operation, and the input/output data latch circuit 110 in the second stage operation. The write data latched in the circuit 110 is sent to the sense amplifier data latch SADL corresponding to the selected bit line BL1.

Implementation details are further described below.

Referring to FIG. 2A, which is a timing diagram of a read operation according to an embodiment of the present invention, FIG.
4 is a timing diagram of a write operation according to an embodiment of the present invention; FIG. Please also refer to FIGS. 1-2B. In this embodiment, the input/output data latch circuit 110 includes a read data latch circuit RDL and a write data latch circuit WDL. The read data latch circuit RDL is coupled between the main input/output line pair MIO and the local input/output line pair LIO, and is controlled by a read input signal RDIN and a read output signal RDOUT. The write data latch circuit WDL is coupled between the main input/output line pair MIO and the local input/output line pair LIO,
It is controlled by a write input signal WDIN and a write output signal WDOUT.

Referring to FIG. 2A, each time memory device 100 performs a read operation READ,
A read operation READ is divided into two stages, a first stage operation ST1 and a second stage operation ST2. In the first stage operation ST1, the column select signal CSL1 selectively renders the bit line pair BL1 and the local input/output line pair LIO conductive. A sense amplifier data latch SADL between bit line BLT1 and complementary bit line BLB1 transmits read data RD to local input/output line pair LIO. In addition, the read input signal RDIN causes the read data latch circuit RDL to receive from the local input/output line pair LIO and latch the read data RD. In the second stage operation ST2, the readout output signal RDOUT is
The read data RD latched in the read data latch circuit RDL is applied to the main input/output line pair MI.
O, and the sensor enable signal SA_EN causes the main sensing drive circuit 120 to sense the read data RD on the main input/output line pair MIO.

In particular, what should be explained is that in the second stage operation ST2 of the read operation READ,
Column select signal CSL1 is already in an invalid state, and bit line pair BL1 and local input/output line pair LIO are non-conductive. In the read operation READ of this embodiment, the length of time of the first stage operation ST1 is the same as that of the second stage operation ST2, and the length of time is tCOR. It is the same as the column selection period of memory device 100 . The column select period is the pulse period at which each column begins.

Referring to FIG. 2B, each time when the memory device 100 performs a write operation WRITE, the write operation WRITE similarly performs a first stage operation ST1 and a second stage operation ST2.
is divided into two stages. In the first stage operation ST1, the drive enable signal DR
_EN is in a valid state, and the main sensing drive circuit 120 transmits write data WD to the main input/output line pair MIO. The write input signal WDIN is applied to the write data latch circuit W
Let DL receive the write data WD from the main I/O line pair MIO and latch it.
In the second stage operation ST2, the write output signal WDOUT causes the write data WD latched by the write data latch circuit WDL to be output to the local input/output line pair LIO.
In addition, the column selection signal CSL1 conducts the bit line pair BL1 to the local input/output line pair LIO. The write data WD is sent to the sense amplifier data latch SADL corresponding to the bit line pair BL1. Finally, the write data WD are written to the memory cell MC1.

In particular, in the first stage operation ST1 of the write operation WRITE,
Column select signal CSL1 is in an invalid state, and bit line pair BL1 is not connected to local input/output line pair LIO. In the write operation WRITE of this embodiment, the length of time of the first stage operation ST1 is the same as that of the second stage operation ST2, and the length of time is tCOW. It is the same as the column selection period of memory device 100 .

In this embodiment, the length of time for each stage operation is the same regardless of whether it is a write operation WRITE or a two-step operation of a read operation READ. read operation R
Both the time of the first stage operation ST1 and the second stage operation ST2 of EAD are tCOR
is. First stage operation ST1 and second stage operation ST2 of write operation WRITE
are both tCOW. Also, the length of time of the two-stage operation of this embodiment is the same in both the write operation WRITE and the read operation READ. The length of time tCOR for the read operation READ is the same as the length of time tCOW for the write operation WRITE. Here, the length of time for each stage operation is one column selection period.

The write data WD and the read data RD are latched via the input/output data latch circuit 110, and the memory device 100 performs the write operation WRITE or the read operation R.
Since any EAD or not can employ a two-step operation, the memory device 100 has a pipeline structure and can execute multiple commands in parallel.

FIG. 3 illustrates a read-while-write scheme according to an embodiment of the present invention.
te, RWW) is a timing diagram of the operation. Referring to FIG. 3, each time the memory device 100 performs a write-read synchronous operation RWW, the write-read synchronous operation RWW is:
It is divided into two stages, a first stage operation ST1 and a second stage operation ST2. first
In stage operation ST1, drive enable signal DR_EN is in a valid state, and main sensing drive circuit 120 transmits write data WD to main input/output line pair MIO. The write input signal WDIN enables the write data latch circuit WDL and the main input/output line pair M
Receive write data WD from IO and latch write data WD. at the same time,
Read input signal RDIN enables read data latch circuit RDL to receive and latch read data RD from local input/output line pair LIO. In the first stage operation ST1, the column select signal CSL1 selectively conducts the bit line pair BL1 to the local input/output line pair LIO. The read data RD is transmitted from the sense amplifier data latch SADL connected to the bit line pair BL1 to the read data latch circuit RDL.

In other words, in the first stage operation ST1, the memory device 100 inputs the write data WD to the write data latch circuit WDL and inputs the read data RD from the memory cell MC1 to the read data latch circuit RDL in parallel. can do.

In the second stage operation ST2, the write output signal WDOUT controls the write data latch circuit WDL to transfer the latched write data WD to the local input/output line pair LIO.
output to At the same time, the read output signal RDOUT is applied to the read data latch circuit RDL.
to output the read data RD to the main input/output line pair MIO, causing the main sensing drive circuit 120 to sense the read data RD from the memory cell MC1. In addition, column select signal CSL2 selectively conducts bit line pair BL2 to local input/output line LIO. Write data WD is stored in sense amplifier data latch SA corresponding to bit line pair BL2.
sent to the DL. The write data WD is written to the memory cell MC2.

Briefly, in the second stage operation ST2, the memory device 100 outputs write data WD from the write data latch circuit WDL and outputs read data RD of the memory cell MC1 from the read data latch circuit RDL in parallel. can run to The memory device 100 can write the write data WD to the memory cell MC2 while sensing the read data of the memory cell MC1 in the second stage operation ST2.

In this embodiment, the length of time of the first stage operation ST1 of the read during write operation RWW is the same as the length of time of the second stage operation ST2, and can be one column selection cycle. For example, the length of time of the write read synchronous operation RWW is the length of time t
It can be equal to twice the COR (2*tCOR) or twice the length of time tCOW (2*tCOW).

FIG. 4 is a circuit diagram of a memory device according to another embodiment of the invention. Referring to FIG. 4, memory device 200 is similar to memory device 100 and is capable of implementing various embodiments described above. The difference between memory device 200 and memory device 100 is that memory device 200 further includes error correction (ECC) circuitry 210 . EC
C circuit 210 is used to perform error checking and correction on data from selected bit line pairs.

FIG. 5 is a timing diagram of a masked-write operation according to an embodiment of the invention. Memory device 200 may implement the embodiment of FIG.
Please refer to FIG. 5 in conjunction with FIG. The memory device 200 sequentially receives a first masked write command MWR1 and a second masked write command MWR2, and correspondingly performs a read-modify-write operation 301 and a read-modify-write operation 302. . In the course of performing a read-modify-write operation 301 or 302, after performing a read operation READ, the ECC circuit 210 performs an error checking and correction step 310 on the read data. Also, before performing a write operation WRITE, the memory device 200 performs a data transmission step 320 and parity generation (par
identity generation) step 330 must also be performed. read operation R
For implementation details of EAD and write operation WRITE, reference can be made to the description of the above embodiments. Starting with the mask write command (MWR1 or MWR2) and after time T0, the memory device 200 begins executing the data transmission step 320 and the parity data generation step 330 for the first time. At parity generation step 330, for example:
Parity generation is performed by combining read data and write data.

In this embodiment, the period length of the read operation READ and the write operation WRITE is the same, and both have a length of time T. FIG. The length of time T is two column selection periods, eg 2*tC
Equal to OR or 2*tCOW. For read operation READ and write operation WRITE, the length of time of each stage operation of the two-stage operation can both equal one column select period. When the memory device 200 performs a read-modify-write operation 301 or 302 on the selected bit line pair, the selected bit line pair read operation REA.
The start time to perform D is at least two times the length of time T earlier than the start time to perform the write operation WRITE of the selected bit line pair, i.e., the memory device 200 is at least Write operation WR after four column selection cycles
Start running ITE. In other words, in the read-modify-write operation of the present embodiment, the point in time at which the read operation READ is initiated is m*T earlier than the point in time at which the write operation WRITE is initiated, where m is greater than or equal to 2. is an integer of

It should be mentioned that the time interval tCCD between the first mask write command MWR1 and the second mask write command MWR2 can be shortened to n*T, where n is an integer greater than or equal to one. That is, the minimum delay time between column addresses in this embodiment is at least 2
The operation speed of the memory device 200 can be improved since it can be shortened to one column selection period.

FIG. 6 is a timing diagram of a write mask operation according to an embodiment of the invention. The memory device 200 can implement the embodiment of FIG. 6, and reference is made to FIG. 6 in conjunction with FIG. The memory device 200 receives the first masked write command MWR1 and the second masked write command MWR2 in sequence and performs read modify-write operation 401 and read-modify-write operation 402 correspondingly. In the course of performing a read-modify-write operation 401 or 402, after performing a read operation READ, the ECC circuit 210 performs an error checking and correction step 310 on the read data. Similar to the flow of the embodiment of FIG. 5, memory device 200 performs data transmission step 320 and parity data generation step 330 before data is written back to the memory cells.

In this embodiment, the memory device 200 has read/write capabilities. Memory device 200 performs a write read synchronous operation RWW after step 330 .
When memory device 200 performs an operation to write data back to a memory cell in read-modify-write operation 401 , it can simultaneously perform an operation to read data from the memory cell in read-modify-write operation 402 . In this manner, the access speed of memory device 200 can be accelerated. Write read synchronous operation RWW
, the implementation details of the read operation READ and the write operation WRITE can be referred to the above embodiments.

In this embodiment, the write/read synchronous operation RWW, the read operation READ, and the write operation WRITE have the same cycle length, and all have a length of time T. FIG. Here the length of time T is equal to two column selection periods, eg 2*tCOR or 2*tCOW. When the memory device 200 performs a read-modify-write operation 401 or 402 on the selected bit line, the point in time of the start of the read operation READ is m*T earlier than the write read synchronous operation RWW or the write operation WRITE. , where m is an integer greater than or equal to 2.

It should be mentioned that the time interval tCCD between the first mask write command MWR1 and the second mask write command MWR2 is also shortened to m*T. That is, the delay time between minimum column addresses in this embodiment can be reduced to at least four column selection periods.

FIG. 7 is a flow diagram of a memory device operating method according to an embodiment of the present invention. Referring to FIG. 7, the method of operation of FIG. 7 is applied to the read operation READ of the embodiments of FIGS. 1-6.
The operation method of FIG. 7 will be described below using the reference numerals of the members of the above embodiment.

In step S710, the data of the selected bit line pair stored in the sense amplifier data latch SADL in the first stage operation ST1 is transferred to the input/output data latch circuit 110.
latch to In step S720, the data of the selected bit line pair latched in the input/output data latch circuit 110 in the second stage operation ST2 is transferred to the main input/output line pair MIO.
and performs a read operation READ.

FIG. 8 is a flow diagram of a method of operating a memory device according to another embodiment of the invention. 8, the method of operation of FIG. 7 is applied to the write operation WRITE of the embodiments of FIGS. 1-6. The operation method of FIG. 8 will be described below using the reference numerals of the members of the above embodiment.

In step S810, the write data of the main input/output line pair MIO is latched in the input/output data latch circuit 110 in the first stage operation ST1. In step S820, in the second stage operation ST2, the write data latched by the input/output data latch circuit 110 is transmitted to the sense amplifier data latch SADL corresponding to the selected bit line pair,
Perform a write operation.

Each step in FIGS. 7 and 8 has been described in detail in the embodiments of FIGS. 1 to 6, and those skilled in the art can obtain sufficient suggestions and teachings from the foregoing description, so they are described again here. do not do.

In summary, the memory device of the present invention performs an access operation by an input/output data latch circuit provided between a main input/output line pair and a local input/output line pair, and inputs data from a bit line pair sense amplifier data latch. It is divided into two stages: sending to the output data latch circuit and sending the data latched in the input/output data latch circuit to the main input/output line pair. Therefore, the memory device has a pipeline structure and can execute multiple commands in parallel. This improves the access speed of the memory device. Embodiments of the present invention also present operating directions that apply to the above memory devices.

Although the present invention has disclosed embodiments as described above, it is not intended to limit the present invention, and those skilled in the art can make some changes and modifications without departing from the spirit of the present invention. Therefore, the scope of protection of the present invention is based on the following claims.

100 memory device 110 input/output data latch circuit 120 main sensing drive circuit 210 ECC circuits 301, 302, 401, 402 read-modify-write operation 310 error check correction step 320 data transmission step 330 parity data generation step BLSA bit line sense amplifier circuit BL1, BL2 Bit line pair BLT1, BLBT2 Bit lines BLB1, BLB2 Complementary bit lines CSL1, CSL2 Column selection signal DR_EN Drive enable signal LIO Local input/output line pair LIOT Local input/output line LIOB Complementary local input/output line MA Memory cell array MIO Main input Output line pair MIOT Main input/output line MIOB Complementary main input/output lines MC1, MC2 Memory cell MWR1 First mask write command MWR2 Second mask write command M Integer RD Read data RDIN Read input signal RDOUT Read output signal RDL Read data latch circuit READ Read operation RWW Write read synchronous operation SADL Sense amplifier data latch SA_EN Sensor enable signal ST1 First stage operation ST2 Second stage operation TC Switch T0 Time tCCD Time interval tCOR, tCOW, T Length of time WL Word line WD Write data WDL Write data latch circuit WDIN write input signal WDOUT write output signal WRITE write operations S710, S720, S810, S820 steps of the memory device operating method

Claims (12)

an input/output data latch circuit coupled between the main input/output line pair and the local input/output line pair;
a bit line sense amplifier circuit;
including
the local input/output line pairs are coupled to a plurality of bit line pairs via the bit line sense amplifier circuits;
When the memory device performs either a read operation or a write operation, the memory device performs a two-step operation to input data on selected bit line pairs of the plurality of bit line pairs. or output
The selected bit line pair is conducted to the local input/output line pair only in one stage operation of the two-step operation, and in another stage operation of the two-step operation, the input/output data latch circuit. the data of the selected bit line pair latched in is transmitted to the main input/output line pair;
when the memory device performs a write-read synchronous operation, a write-time read cycle includes two column selection cycles, and the input/output data latch circuit includes a read data latch circuit and a write data latch circuit;
In the first column select period of the read-at-write period, the read data latch circuit receives data on a first bit line pair from the first sense amplifier data latch, and the write data latch circuit The write data latch circuit receives write data from an input/output line pair, and provides the write data to a second sense amplifier data latch in the second column selection cycle of the read-at-write cycle, and a data latch circuit for transmitting data on the first bit line pair to the main input/output line pair;
The first bit line pair and the second bit line pair are two of the plurality of bit line pairs, and the first sense amplifier data latch and the second sense amplifier data latch are respectively connected to the first bit line pair. A memory device that stores data on a line pair and the second bit line pair. the bit line sense amplifier circuit includes a plurality of sense amplifier data latches for storing data of the plurality of bit line pairs;
the two-stage operation includes a first stage operation and a second stage operation;
When the memory device performs a read operation, in the first stage operation, data on the selected bit line pair are latched from the corresponding sense amplifier data latches to the input/output data latch circuits and In the stage operation, the data latched by the input/output data latch circuit is transmitted to the main input/output line pair,
When the memory device performs a write operation, write data is latched from the main input/output line pair to the input/output data latch circuit in the first stage operation, and the input/output data is latched in the input/output data latch circuit in the second stage operation. 2. The memory device of claim 1, wherein said write data latched in a latch circuit is sent to said sense amplifier data latch corresponding to said selected bit line pair. The input/output data latch circuit
a read data latch circuit coupled between the main input/output line pair and the local input/output line pair;
a write data latch circuit coupled between the main input/output line pair and the local input/output line pair;
including
When the memory device performs the read operation, in the first stage operation, the read data latch circuit receives data on the selected bit line pair, and in the second stage operation, the read data latch circuit. data latched in the circuit is transmitted to the main input/output line pair;
When the memory device performs the write operation, the write data latch circuit receives write data in the first stage operation, and the write data latched in the write data latch circuit receives the write data in the second stage operation. 3. The memory device of claim 2, sent to said sense amplifier data latches corresponding to selected bit line pairs. further comprising an error correction circuit for performing error checking and correction on data on the selected bit line pair;
The memory device performs the write-read synchronous operation in the course of performing a read-modify-write operation, and the start time of the read operation performed on the selected bit line pair is determined by the read operation performed on the selected bit line pair. 2. The memory device of claim 1 , at least two of said read-on-write periods earlier than a start time of said write-read synchronous or write operation. 5. The memory device of claim 4, wherein a delay time between column addresses is at least one of said write-read synchronization periods and is an integer multiple of said write-read synchronization periods. further comprising an error correction circuit for performing error checking and correction on data on the selected bit line pair;
A cycle length of a read operation and a write operation are both equal to two column selection cycles, a time length of each stage operation of the two-step operation is both equal to one column selection cycle, and the memory When the device performs a read-modify-write operation on the selected bit line pair, the start time of the read operation performed on the selected bit line pair is the write operation performed on the selected bit line pair. 2. The memory device of claim 1, at least four of said column select periods earlier than a start time of operation. 7. The memory device according to claim 6, wherein a delay time between column addresses is at least two periods of said column selection period and is an integer multiple of two periods of said column selection period. 2. The memory device of claim 1, wherein the length of time of each said stage operation of said two-step operation is the same. 9. The memory device of claim 8, wherein the length of time of the two-step operation is the same for write and read operations. a step of latching data of a selected bit line pair stored in a sense amplifier data latch in an input/output data latch circuit in a first stage operation;
In a second stage operation, transmitting data of the selected bit line pair latched in the input/output data latch circuit to a main input/output line pair to perform a read operation;
The read-on-write cycle of the write-read synchronous operation includes two column selection cycles, the method of operation comprising:
In the first column selection period of the read period during writing, the read data latch circuit of the input/output data latch circuit receives the data of the first bit line pair from the first sense amplifier data latch, and reads the input/output data. a write data latch circuit of a latch circuit receiving the write data from the main input/output line pair;
In the second column selection period of the read-at-write period, the write data latch circuit provides the write data to the second sense amplifier data latch, and the read data latch circuit provides the write data to the first bit line pair. data to the main input/output line pair;
further comprising
The first bit line pair and the second bit line pair are two of the plurality of bit line pairs, and the first sense amplifier data latch and the second sense amplifier data latch are respectively connected to the first bit line pair. A method of operating a memory device to store data on a line pair and said second bit line pair . latching write data on the main input/output line pair in the input/output data latch circuit in the first stage operation;
further comprising transmitting the write data latched in the input/output data latch circuit to the sense amplifier data latch corresponding to the selected bit line pair in the second stage operation, and performing a write operation. Item 11. Operation method according to item 10. performing the read and write operations comprises:
When the memory device performs the read operation, in the first stage operation the read data latch circuit of the input/output data latch circuit receives data on the selected bit line pair, and in the second stage operation , the step of transmitting the data latched in the read data latch circuit to the main input/output line pair;
When the memory device performs the write operation, the write data latch circuit of the input/output data latch circuit receives the write data in the first stage operation, and the write data latch circuit in the second stage operation. sending the write data latched in the circuit to the sense amplifier data latch corresponding to the selected bit line pair;
12. The method of operation of claim 11, further comprising:

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